Posted:1 day ago|
Platform:
Work from Office
Full Time
The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools.
The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF.Candidate with LBIST and Mixed Signal Radar IC experience is highly desirableMust be proactive, collaborative and detail-oriented capable of exercising independent judgmentThe engineer with experience on debug and root cause the problem in simulation failuresSelf-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills.
Shashwath Solution
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