806 Rtl Jobs

Understand the design specification, Power On Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verificationChip reset sequence and initialization, and/or Power management. Knowledge of verification methodology, Knowledge of HDLs (VHDL,Verilog) Good programming skills in C++/C/OOPs, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge High Speed Serdes Phy, PCIe, DDR, Ethernet protocol Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Expertise in ASIC RTL Design Expertise in ASIC IP Design Expertise in CDC and Lint tools Expertise in design and simulation tools Expertise in Video processing algorithms / interfaces Expertise in CXL / PCIe Protocol, 5G, Datacenter

**Job Description** **Role Overview:** In this role, you will work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. **Key Responsibilities:** - Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios. - Identify and write all types of coverage measures for stimulus and corner-cases. - Debug tests with design engineers to deliver functionally correct design blocks. - Measure to identify verification holes and to show progress towards tape-out. - Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM). **Qualifications Required:** - Bachelor's degree in Electrical Engineering or equivalent practical experience. - 4 years of experience in Verification, verifying digital logic at RTL level using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or ASICs. - Experience in verification and debug of IP/subsystem/SoCs in the Networking domain such as packet processing, bandwidth management, congestion control desired. - Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems). **About the Company:** The ML, Systems, and Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.,

As a member of the team at Cadence, your role will involve: - Designing and implementing DFT IP with Verilog/SystemVerilog and/or VHDL - Designing and implementing RTL for DFT IP including POST, IST - Developing synthesis automation for DFT IP, which includes synthesis and timing constraints, RTL insertion, and verification - Owning and maintaining, extending, and enhancing existing DFT IP like LBIST At Cadence, you will be part of a team that is focused on doing work that matters and solving challenges that others may find difficult. Join us in making an impact on the world of technology.,

Role Overview: As a Senior React.js Developer at Prometteur Solutions Pvt. Ltd., you will play a pivotal role in leading and mentoring a team of React developers. Your expertise in front-end development and leadership skills will contribute to the growth and scalability of the team. This position offers an opportunity to shape a strong and high-performing team while working on cutting-edge technology solutions. Key Responsibilities: - Write clean, high-performance, and reusable React.js code. - Drive component architecture and scalable design implementation. - Optimize performance for maximum speed and responsiveness. - Integrate with RESTful APIs and third-party libraries. - Lead cross-browser and cross-platform compatibility efforts. - Guide a team of React developers. - Review PRs and help improve code quality, test coverage, and standards. - Facilitate knowledge-sharing sessions and peer learning. - Help in setting performance standards and improving team KPIs. - Be the go-to person for problem-solving and design discussions. - Work closely with UI/UX Designers, Product Managers, Backend Engineers, and QA teams. - Participate in sprint planning, grooming, estimation, and retrospectives. - Translate product requirements into scalable front-end solutions. - Contribute to internal tools, design systems, and documentation. Qualification Required: - 5 - 7 years of strong JavaScript experience with deep React.js expertise. - Solid understanding of Redux / Context API / React Query. - Strong command over HTML5, CSS3, Sass/LESS, and responsive frameworks. - Experience in state management, performance tuning, and code splitting. - Familiarity with unit testing tools like Jest, Enzyme, or RTL. - Experience with version control (Git), code review processes, and CI/CD. - Exposure to Agile environments and product-focused development. - Prior experience mentoring or leading a team is highly preferred.,

1. Minimum of three years of hands-on Test Development experience (DFT, EDA tools, etc..) 2. Solid knowledge & experience in defining test solutions for multi-million gate SOC (Scan & MBIST) with Mixed Signal IPs (PLL, High Speed SERDES, DDR) 3. Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test 4. Strong understanding of relationships between Hardware, Firmware and Software in FPGA and/or multi-processors SOC. Past experience in leading the team to successful silicon bring-up and problem solving in a complex system 5. Strong planning, project, and people management skills required. Must have experience developing managers and individual contributors 6. Experienced hands-on technical manager not afraid to dig into details to provide technical direction Proven track record of delivering results and meeting quality, cost, and time-to-market objectives 7. Ability to collaborate with overseas colleagues to define strategy, plan, and execute across the larger, global organization 8. Stakeholder influencing and people skills must be excellent. 9. Needs to be able to set aggressive goals and manage risks effectively 10. Must have a thorough understanding of tool development methodology. 11. Ability to manage software development tasks associated with specifying, developing, scheduling, and debugging according to current and future tool requirements. 12. MS or Ph.D. Engineering degree (EE or equivalent) with 3-7 years semiconductor industry experience.

Job Specs : Work with design and architecture teams to define and generate timing constraints that specify the desired timing requirements for the design. Set up and configure STA tools ( PrimeTime, StarRC, Tempus, Innovus and QRC ) for the analysis, including library characterization, delay models, and clock definitions Perform static timing analysis to evaluate setup and hold times, clock-to-q delays, and other timing metrics. Ensure that the design meets timing requirements for various corners and operating conditions (e.g., process, voltage, temperature variations). Identify and analyze asynchronous signals crossing between different clock domains to ensure proper synchronization and to avoid metastability issues. Define and analyze multicycle paths and false paths to accurately capture the designs timing constraints. Collaborate with RTL and physical design teams to achieve timing closure by optimizing the design or constraints. Perform incremental and formal ECO (Engineering Change Order) analysis to address timing issues. Work with CTS engineers to ensure that the clock tree meets timing requirements and minimizes clock skew and jitter. Perform post-layout STA to account for parasitic capacitance and resistance effects introduced during the physical design phase. Identify and resolve timing violations and sign-off on the final timing closure. Analyze timing margins to account for variability and manufacturing process variations, ensuring robust operation. Prepare detailed timing analysis reports, including timing paths, violations, and suggestions for timing optimization. Collaborate closely with RTL designers, physical designers, DFT (Design for Test) engineers, and verification teams to resolve timing-related issues. Contribute to the development and improvement of STA methodologies and flows to enhance efficiency and accuracy.Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Vietnam are the preferred work locations Preferred resources with valid regional work permit.

The Core design and verification team is responsible for development of High performance and Ultralow power x86 microprocessor core . The role provides a unique opportunity to work at the micro-architectural level of the next-gen Core, with exposure to designs that defines the next wave of client (laptops / ultra-books / think-clients) and custom designs. The multi-billion gate complexity and high-frequency (GHz) design development gives the learning experience of the latest and greatest design and verification methodologies, using cutting edge advanced technology nodes. THE PERSON: Candidates should have solid track record of working on complex designs with hands on experience on architecting and developing test-bench, test-bench components, test-planning and execution of testplan, coverage development and closure. Candidate should have working experience with global teams spread across different geography and time-zones. KEY RESPONSIBILITIES: ASIC design verification experience 6 to 10 years. Verification of high performance x86-core ISA features Architecting and development of testbench, test-bench components for high performance Cache, x86 ISA features, clock/reset/power features of processor. Development of detailed test plans and driving the execution of test plan, including functional coverage. Understanding the existing test bench setup and look for opportunities to improve the existing test bench. Adhering to coding guideline practices, develop and implement code review process. Collaborate with global design verification teams and drive effectively the execution of the verification plans. Your commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion. PREFERRED EXPERIENCE: Strong understanding the design and verification life cycle. Hands on verification experience with C/C++/SystemVerilog testbench development. Hands on experience with coverage planning, coding and coverage closure. Experience with x86, ARM or any other industry standard microprocessor ISA. Experience with Cache, Coherency and Data-Consistency verification. Experience in clocking, reset, power-up sequences and power management verification. Knowledge of microprocessor design-for-debug (DFD) logic will be a plus. Understanding of low power design verification techniques is a plus. ACADEMIC CREDENTIALS: Master s degree preferred with emphasis in Electrical/Electronics Engineering, Computer Engineering, or Computer Science with a focus on computer architecture

Desired Profile : Bachelor's / Master's degree in engineering from EEE / E&C Expertise in managing and leading technical teams across different continents Expertise in leading business strategy in the VLSI / Semiconductor Services / foundry business industry Expertise in managing end to end projects including tape outs Must be willing to travel at short notice, relocate as per business needs Must be willing to work onsite (customer premises) as per business needs Expertise in working on any of the following technologies is mandatory : ANALOG MIXED SIGNAL LAYOUT - finfet / high speed / planar technology nodes ANALOG DESIGN - data converter / power management / pll ANALOG VERIFICATION ASIC PHYSICAL DESIGN ASIC RTL DESIGN DFT DESIGN - jtag / mbist / lbist / scan DIGITAL VERIFICATION - OVM / UVM / VMM EDA CAD FLOW - tcl / primetime / design compiler Job Specs : Responsible for meeting delivery, revenue, operational, customer satisfaction targets and team management Hire and manage high caliber technical teams across GCC, ODC and onsite Develop, Drive high quality business / technology strategy and oversee the translation of this strategy into tactical action Uphold the organization's culture and long term missions Liaise and negotiate with various partners around the world to bring in new partnership. Synergize all company's resources and talents for the growth of company's business Oversee all sectors and fields of the business to ensure the company's competitiveness Provide leadership, direction, major decision making and resolution support to operations, projects and staff. Build strategic business partnerships and execute these opportunities through collaboration with external partners Location - Bengaluru,Bhubaneswar,Kolkata,Kochi,Mysuru

Minimum of ten years of hands-on Test Development experience (DFT, EDA tools, etc..) Solid knowledge & experience in defining test solutions for multi-million gate SOC (Scan & MBIST) with Mixed Signal IPs (PLL, High Speed SERDES, DDR) Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test Strong understanding of relationships between Hardware, Firmware and Software in FPGA and/or multi-processors SOC. Past experience in leading the team to successful silicon bring-up and problem solving in a complex system Strong planning, project, and people management skills required. Must have experience developing managers and individual contributors Experienced hands-on technical manager not afraid to dig into details to provide technical direction Proven track record of delivering results and meeting quality, cost, and time-to-market objectives Ability to collaborate with overseas colleagues to define strategy, plan, and execute across the larger, global organization Stakeholder influencing and people skills must be excellent. Needs to be able to set aggressive goals and manage risks effectively Must have a thorough understanding of tool development methodology. Ability to manage software development tasks associated with specifying, developing, scheduling, and debugging according to current and future tool requirements. MS or Ph.D. Engineering degree (EE or equivalent) with 3-10 years semiconductor industry experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: GPU Design and micro-Architect who will work across functions like GPU architecture and Systems in design and micro-architecture of the next generation GPU features. Work very closely with Architecture teams to come up with micro-architecture and hardware specification for features Design and RTL ownership Work very closely with Design Verification teams to review test plans and sign off the validation of all design features across products Work closely with physical design teams to achieve the right power, performance and area metrics for the GPU blocks Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Overview Developing emulation testbenches to support necessary DV scenarios and firmware/software/hardware bring up Responsibilities Build emulation models from RTL and release/support those models Develop emulation tools such as debugger and monitor features Work closely with verification and software development teams Develop emulation and verification strategy Develop test framework and test cases Write documents such as verification specification and reports Coach younger colleagues Emulation and Prototyping technologies such as Palladium, Veloce, Zebu, HAPS, (these names are registered trade marks of their respective owners) Requirements Experience - minimum 15+ yrs and above with minimum of 5+ yrs of experience of woking on any one of the Emulation platform. Education QualificationBE/BTech

Overview Lead Verification engineer Responsibilities As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Requirements Bachelors/ Masters degree or higher in EEE/ECE 7+ years or more of practical semiconductor design verification including System Verilog, UVM, GLS, assertions and coverage driven verification. Experience using multiple verification platforms: UVM test bench, emulator, software environments Experience with industry standard IO interfaces like AMBA, CXL, USB, MIPI, PCIE, DDR etc. Experience defining verification methodologies Experience with test plan development, test bench infrastructure, developing tests and verifying the design Experience with writing directed/constrained-random tests Experience identifying bugs in architecture, functionality, and performance with strong overall debug skills Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python) for automation Experience in SOC Architecture is a strong plus Experience with ARM/RISCV Experience with debugging system level issues Experience with industry standard IO interfaces like AMBA, USB, MIPI, PCIE etc. Experience with formal verification techniques Excellent verbal and written communication skills

Key Responsibilities Expert level technical support in the resolution of FPGA design and application issues Design or modify electrical/electronic engineering assemblies, layouts/schematics and/or detailed drawings/specifications of moderate scope under general supervision. Create design and specification documents, test plans and progress reports. Conduct obsolescence risk assessment for prompt risk mitigation strategy and implementation to ensure product manufacturability and sustenance. Coordinate the procurement and assembly of electrical/electronic components/equipment and identify sources of critical parts and subsystems to resolve technical issues. Participate in resolving customer complaints & escalations through root-cause analysis and corrective-preventive actions. Functional Knowledge (Required Skills/Experience): Extensive knowledge of RTL design language. Hands on experience on design, simulation and testing of FPGA application. Good knowledge of electrical design engineering, Digital/Analog/Mixed signals, Power electronics, Controls and Instrumentation. Good knowledge of electrical engineering design concepts and applications - components, schematics, electrical system. Good understanding on communication interface such as I2C, SPI, USB, Wi-Fi, IoT and Bluetooth, memory device such as SRAM, DDR3+, and high speed communication protocols such as ETHERCAT, ETHERNET, PCIe Experience on microcontrollers and microprocessor design. Interpersonal Skills Demonstrate strong written, oral, and interpersonal communication skills. Excellentaptitude formulti-tasking and willing to learn. Qualifications Bachelor''s Degree in Electrical Engineering / Electronics & Communication Qualifications Education: Bachelor''s Degree Skills: Certifications: Languages: Years of Experience: 4 - 7 Years Work Experience: Additional Information Time Type: Full time Employee Type: Assignee / Regular Travel: Yes, 10% of the Time Relocation Eligible: Yes Applied Materials is an Equal Opportunity Employer committed to diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.

Lead the architecture, design and development of a server class, high- performance Processor CPU for IBM Systems. - Architect and design Instruction caches, Branch Predictors, Issue queues, Register Renaming, Load Store Execution and other areas of the IBM processor CPU - Research novel instruction/data prefetching and branch prediction architectures. - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Doctorate Degree Required technical and professional expertise Expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Nice to haves - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Knowledge of object oriented languages and scripting languages - Understanding of Agile development processes - Experience with DevOps design methodologies and tools Preferred technical and professional experience Expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Nice to haves - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Knowledge of object oriented languages and scripting languages - Understanding of Agile development processes - Experience with DevOps design methodologies and tools

Lead the architecture, design and development of Processor Core Front end of pipeline units for high-performance IBM Systems. - Architect and design I-Cache, Instruction Fetch, Branch Prediction and Decode units of a high performance processor CPU - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Doctorate Degree Required technical and professional expertise .12 or more years of demonstrated experience in architecting and designing specific CPU unit(eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) - Hands on experience of different Branch Prediction techniques - Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - At least 1 generation of Processor Core silicon bring up experience - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Knowledge of at least one object oriented or functional programming language and scripting language. - Nice to haves - Knowledge of instruction decode and handling pipeline hazards - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Understanding of Agile development processes - Experience with DevOps design methodologies and tools Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

Responsibilities: As a Logic design lead in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL ... Good understanding of HW / SW co design / accelerators to enhance system level performance. Collaborate with the Chip development, Unit Verification, Physical design, testgen, millcode teams to develop the feature. Pre-Silicon: Signoff the Design that meets all the functional, area and timing goals. Post Silicon: Validate the hardware functionality Required Professional and Technical Expertise: Minimum 8 20 + years of experience in Chip design and development. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, multipliers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core. Experience with VLSI Design in VHDL / Verilog logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. Requirements : Masters in VLSI with demonstrated experience in the micro archite As a Logic design lead in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL Good understanding of HW / SW co design / accelerators to enhance system level performance. Collaborate with the Chip development, Unit Verification, Physical design, testgen, millcode teams to develop the feature. Pre-Silicon: Signoff the Design that meets all the functional, area and timing goals. Post Silicon: Validate the hardware functionality cture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Required technical and professional expertise Minimum 8 20 + years of experience in Chip design and development. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, multipliers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core. Experience with VLSI Design in VHDL / Verilog logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. Preferred technical and professional experience Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance.

Role Description: This is a full-time on-site role for a Senior Lead Physical Design Engineer based in Hyderabad. The Senior Physical Design Engineer will be responsible for tasks related to physical design, physical verification, logic design, circuit design, and RTL design in the development of silicon products. Qualifications: He/She should be able to do block level PNR including PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. Minimum of 7-15 years of experience in physical design. He/She should have worked on 7nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design engineers. Lead a team of Physical design engineers and be responsible for their blocks closure Interface with front-end ASIC teams to resolve issues. Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques. Expertise in Timing closure on high speed interfaces is a plus Excellent communication skills. Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure. Extensive experience and detailed knowledge in Cadence or Synopsys. Expertise in scripting languages such as PERL, TCL. Strong Physical Verification skill set. Static Timing Analysis in Primetime or Primetime-SI. Good written and oral communication skills. Ability to clearly document plans. Ability to interface with different teams and prioritize work based on project needs.

Required Skills Experience in Logic design / RTL coding is a must. Experience is SoC design and integration for complex SoCs is a must. Experience in Verilog/System-Verilog is a must. Experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint and CDC. Experience in Synthesis / Understanding of timing concepts is a plus. Experience in ECO fixes and formal verification. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture. Excellent oral and written communications skills. Proactive, creative, curious, motivated to learn and contribute with good collaboration skills

As an Electrical Engineer with 4 years of experience in Verification, you will play a crucial role in shaping the future of AI/ML hardware acceleration. Your responsibilities will include driving cutting-edge TPU (Tensor Processing Unit) technology for Google's demanding AI/ML applications. You will be part of a dynamic team that focuses on developing custom silicon solutions to power Google's TPU, contributing to innovative products loved by millions worldwide. Your key responsibilities will involve: - Planning the verification of digital design blocks and collaborating with design engineers to identify critical verification scenarios. - Identifying and implementing various coverage measures for stimulus and corner-cases to ensure thorough verification. - Debugging tests with design engineers to ensure the delivery of functionally correct design blocks. - Creating a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM). Preferred qualifications for this role include a Master's degree in Electrical Engineering or a related field, experience with industry-standard simulators and regression systems, as well as familiarity with AI/ML Accelerators or vector processing units. Excellent problem-solving and communication skills will be essential for success in this role. About the company: The ML, Systems, and Cloud AI (MSCA) organization at Google focuses on designing, implementing, and managing hardware, software, machine learning, and systems infrastructure for all Google services and Google Cloud. With a commitment to security, efficiency, and reliability, the organization drives innovation in hyperscale computing, including Google Cloud's Vertex AI platform. In this role, you will have the opportunity to own the full verification life-cycle, from planning and test execution to coverage closure, with a specific emphasis on meeting stringent AI/ML performance and accuracy goals. By collaborating closely with design and verification engineers, you will contribute to verifying complex digital designs, particularly focusing on TPU architecture integration within AI/ML-driven systems.,

As a Senior Member of Technical Staff (SMTS) Silicon Design Engineer at AMD, you will play a crucial role in designing high-precision custom circuit blocks for AMD's microprocessor designs. Your responsibilities will include owning individual circuit blocks in a DDR PHY design, ensuring circuit design quality, performing electrical and timing analysis, and collaborating with cross-functional teams. Your expertise in DDR circuit designs, power-performance trade-offs, design analysis, and variation impact will be essential for success in this role. Key Responsibilities: - Complete ownership of individual circuit blocks in a DDR PHY design in cutting-edge process technology nodes - Responsible for circuit design, layout quality, electrical and timing analysis, and reliability checks - Interface with cross-functional teams like RTL, Verification, and Physical Design Preferred Experience: - Strong hands-on experience in DDR circuit designs in the latest process technology nodes - Good technical knowledge of power-performance trade-offs in high-speed DDR and/or SerDes architectures - Direct experience in all phases of design analysis including functional, static timing, and electrical sign-off - Strong understanding of the impact of variation on design performance Qualifications: - Desired: Masters in Electrical/Electronics Engineering, with specialization in microelectronics or a related field In this role, you will join a team that offers a competitive atmosphere for learning and growth, with a strong focus on innovation and work-life balance. Your passion for innovation and efficiency, coupled with your circuit design expertise, communication skills, and dedication to meticulous documentation, will set you apart as an ideal candidate for this position. Please note that the benefits offered at AMD are described in detail under "AMD benefits at a glance.",

About The Role This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; About The Role - Grade Specific Focus on Electrical, Electronics and Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in straight forward situations and generates solutions. Contributes in teamwork and interacts with customers.

About The Role About The Role Should be good in Integration of SOC & RTL coding. Should be aware of SOC flow like Spyglass-Lint/Synthesis (DC)/CDC. Should be aware of scripting language. Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP. Should have good understanding of SoC flows. Primary Skills: VHDL, Verilog,Micro-architecture, R TL coding,CDC, Lint, Synthesis, STA,IP development , SoC integration,VCLP,scripting -Perl,Python,Shell, and Tcl. Secondary Skills: Synopsis/Cadence tool flow,ARM Coretex,DMA, DDR, SPI, I2C, UART,AHB/AXI/APB,Ethernet, USB, PCIe,Mipi CSI/DSI, LPDDR. Education B.E/B.Tech/ Any Engineering.

Perform Sub system level floor planning, placement, and routing for high-performance microprocessor design. Collaborate with cross-functional teams to achieve design goals. Close the design to meet timing, power, and area requirements. Implement engineering change orders (ECOs) to rectify functional bugs and timing issues. Ensure the quality and efficiency of the RTL to GDS2 implementation process. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8+ years of industry experience Good knowledge and hands on experience in physical design , timing and methodology which include logic synthesis, placement, clock tree synthesis, routing , post route closure. Should be knowledgeable in physical verification ( LVS,DRC. etc) ,Noise analysis, Power analysis and electro migration . Good knowledge and hands on experience in static timing analysis (closing timing at chip level) good understanding of timing constraints . Should have experience in handling asynchronous timing, multiple corner timing closure.

Job Requirements Experience 4-8 yrs in Design Verification. Strong SV UVM Verification exp in real projects. Peripheral I/O, Ethernet ARM SOC-based Experience in Physical design with block level and familiar with ASIC design flow from synthesis to GDSII. Experience in handling High utilized critical blocks and Congestion mitigation Work very closely with Architecture teams to come up with micro-architecture and hardware specification for features Design and RTL ownership Work very closely with Design Verification teams to review test plans and sign off the validation of all design features across products. Work closely with physical design teams to achieve the right power, performance and area metrics for the GPU blocks. WFO mandated.