1614 Sta Jobs

Domain :: STA (Static Timing Analysis) Work Experience :: 3 6 years Location :: Noida Tool Expertise :: PrimeTime & PT-ECO Technical Expertise :: • Block level Timing Constraints enablement & analysis ; • Clocking & Data flow understanding ; • Well versed in reviewing check_timing and Constraints QoR checks + Constraints Validation understanding ; • Able to interact with Implementation team counterparts for block timing closure ; • CTS building understanding along with Clock Tree spec review/closure ; • Timing ECOs & Final Timing last mile closure at block level ; • Scripting like TCL, Unix et

STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs. Timing analysis, validation and debug across multiple PVT conditions using Tempus. Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. Hands-on experience with STA tools Tempus In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling.

Radiant Semiconductors is looking for Physical Verification to join our dynamic team and embark on a rewarding career journey. Perform physical verification of semiconductor designs using CAD tools. Verify layout and design rules compliance. Conduct DRC (Design Rule Check) and LVS (Layout vs. Schematic) verification. Analyze and debug physical verification errors and violations. Work with design and layout teams to resolve physical design issues. Implement and optimize physical verification methodologies. Generate and review physical verification reports. Stay updated with semiconductor manufacturing processes and technologies. Disclaimer : This job description has been sourced from a public...

Radiant Semiconductors is looking for Physical Design Professional to join our dynamic team and embark on a rewarding career journey Develop and implement physical design methodologies for integrated circuits (ICs). Perform floor planning, power planning, and placement for IC layout. Conduct timing closure, optimization, and signal integrity analysis. Generate and verify detailed routing to meet performance targets. Collaborate with RTL designers and verification engineers to resolve design issues. Utilize EDA tools for layout and verification tasks. Ensure compliance with design rules and standards. Document and maintain design specifications and guidelines. Disclaimer: This job description...

Radiant Semiconductors is looking for STA Engineer to join our dynamic team and embark on a rewarding career journey Analyzing customer needs to determine appropriate solutions for complex technical issues Creating technical diagrams, flowcharts, formulas, and other written documentation to support projects Providing guidance to junior engineers on projects within their areas of expertise Conducting research on new technologies and products in order to recommend improvements to current processes Developing designs for new products or systems based on customer specifications Researching existing technologies to determine how they could be applied in new ways to solve problems Reviewing existi...

Full time with century old top Japanese MNC JOB SUMMARY ( Full time with Super Top Japanese MNC) Job Title : Principal Engineer Chip Design Back End Job Overview: : As a Backend (Physical Design) Principal Engineer specializing in Semiconductor Chip Design, you will lead and coordinate the execution of the back-end stages of integrated circuit development. This role requires a strong technical background in physical design, a deep understanding of semiconductor processes, and exceptional project management skills. You will oversee teams engaged in physical design, synthesis, DFT, place and route, power integrity, and other back-end aspects to ensure the successful realization of semiconducto...

This Position reports to: Global Product Marketing Manager In this role, you will plan and implement proactive promotional/spec influencing activities for the assigned target audience to create market demand and need for specific features or products. Build long-term customer relationships and identify and develop sales opportunities by introducing, presenting, and educating the target audience about ABB products and tools. Be directly and independently responsible for homologation of ABB LVS system with identified customers in defined segments. Key Responsibilities: Having deep domain knowledge of IEC Low Voltage systems. Implementing proactive promotional activities, including technical pr...

Job Description: Job Description, As part of TLR team (top-level-route), R&D Engineer is primarily responsible for :- Place and Route, CTS, Routability analysis with respect to congestion. Well versed in physical verification aspect, DRC, LVS, Antenna, LUP, ( chip finishing and Tapeout) Meeting RC requirements for manual/special signals Good understanding of Calibre DRC/LVS/DFM, DFY, ERC and ESD latchup. Responsible for all the integrity checks (chip-finishing) and post Tapeout eJob view release, Good scripting knowledge perl and TCL, familiar with Caliber, Innovus, Understanding of VLSI fabrication process, Implementing timing ECOs. Implementing IR drop fixes, RC extraction, signal EM fixes...

1. Semiconductor Design: Design and develop MCUs and MPUs for performance, low power, and reliability. Work with cross-functional teams to integrate components into integrated circuits (ICs) and ensure compatibility. Create and maintain technical documentation, including design specs, circuit diagrams, and test plans. 2. Semiconductor Testing: Perform testing and validation of MCUs , MPUs , and other semiconductor devices. Develop test plans, troubleshoot, and debug systems to identify issues. Use testing equipment like oscilloscopes and logic analyzers for signal integrity and performance analysis. 3. Procurement: Manage procurement of semiconductor components (MCUs, MPUs) from global suppl...

We are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs Key Responsibilities Perform Synthesis, floor planning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and area targets. Conduct detailed analysis of timing, power, and area, and drive de...

Roles and Responsibilities: 1. Handling request from vessel or TSI for Adding / amending /removal of PMS routines: Amendment request from vessel is sent to TSIs approval and as technical committee member same will be forwarded to PMS DB (by referring technical manuals, makers manual, makers circular). Activation of calendar-based work order while new job is added. For counter-based work order liaising with vessel and activating the same. on completion making sure amendments are reflecting in shore end as requested and intimating the same to vessel /TSI. 2. On signers briefing: For newly joining officers briefing on Shippalm v3 for all 5 modules provide on daily basis via MS teams and physica...

Responsible for meeting agreed market metrics - Fill rate (Line & Piece), Inventory Turns, Back orders etc. Perform all daily/weekly/monthly processes diligently without any backlog thereby meet key deliverables. Work closely with sources for schedule adherence and ensure timely receipt of parts at warehouse. Handle Vehicle off road orders promptly and provide accurate information to dealers. Select parts for A/F based on its function code and its criticality. Maintain Inventory at optimal level and thereby meet inventory turn targets. Perform denial analysis and work towards implementing the containment actions. Review forecast changes, stock order suggestions and validate Ensure all open i...

Responsibilities & Key Deliverables Description of the job and key result areas: Function related: Capability Building of STA domains in platform teams Ensure future readiness by continuously upgrading teams with new technological skills Ensure a Technology roadmap is created along with COE and relevant SSU stakeholders using a structured forum and deploy them to live projects Improvisation of processes and systems through various means such as Digitization, IT enablement, Analytics etc. Create required domain expertise in commodity to help deliver on projects Supplier relationship management Platform related: Manning/Resource Allocation - Enable platform teams to deliver on TCP objectives t...

Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking Analyzes results and makes recommendations to fix violations for current and future product archi...

Job Requirements Roles & Responsibilities Ownership of end-to-end Physical Design flow from RTL to GDSII for complex SoC/ASIC designs. Responsible for floorplanning, partitioning, placement, CTS, routing, and physical verification (DRC/LVS/Antennas etc.). Timing closure activities across PVT corners, multi-mode multi-corner (MMMC) analysis. Work on power planning and optimization (IR drop, EM analysis, low-power design methodologies). Handle STA (Static Timing Analysis) using tools like PrimeTime/Tempus and drive closure. Collaborate closely with RTL designers, DFT, STA, and verification teams to resolve issues proactively. Experience in synthesis and formal equivalence checking (LEC) to ens...

• SoC/Blocks Synthesis/STA methodology & flow for meeting PPA goals • Work with Backend team in realizing PPA goals during PnR & IP & SoC Design team in optimizing the design to meet PPA goals. • Feedback on design issues & solutions. Required Candidate profile • Exp in front end design implementation. • Design flows like Synthesis, Constraint Devel., STA, UPF implementation, Power estimation, Formal verification, timing ECO, Functional ECO generation..

As a Hardware Engineer at Qualcomm India Private Limited, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems. You will work on a variety of systems including circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge products. Collaboration with cross-functional teams will be essential to develop solutions and meet performance requirements. **Key Responsibilities:** - PNR implementation for Qualcomm SoC's - Hands-on experience on Floorplanning, PNR, and STA flows - Knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc - Understanding of ...

As a Hardware Engineer at Qualcomm India Private Limited, you will be part of a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation. Your role will involve planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other cutting-edge technologies to launch world-class products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. **Key Responsibilities:** - Front-End implementation of MSIP (Temp/Voltage/Security Sensors, Controllers) designs - RTL development and validation for lint...

Job Requirements Roles & Responsibilities Ownership of end-to-end Physical Design flow from RTL to GDSII for complex SoC/ASIC designs. Responsible for floorplanning, partitioning, placement, CTS, routing, and physical verification (DRC/LVS/Antennas etc.). Timing closure activities across PVT corners, multi-mode multi-corner (MMMC) analysis. Work on power planning and optimization (IR drop, EM analysis, low-power design methodologies). Handle STA (Static Timing Analysis) using tools like PrimeTime/Tempus and drive closure. Collaborate closely with RTL designers, DFT, STA, and verification teams to resolve issues proactively. Experience in synthesis and formal equivalence checking (LEC) to ens...

You will be working as a Qualcomm Hardware Engineer, where your main responsibilities will include planning, designing, optimizing, verifying, and testing electronic systems to launch cutting-edge products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. To be eligible for this role, you must have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with at least 3 years of experience in Hardware Engineering. Alternatively, a Master's degree with 2+ years of experience or a PhD with 1+ year of experience will also be considered. **Key Responsibilities:** - Lead a team of engineers i...

Job description : Looking for experienced Physical Design Engineer with 2+ years in block-level implementation. Key Requirements: - Floorplaning/Placement/CTS/Routing/STA/PV.

Should have indepth experience in Floor-planning, CTS, Power routing, place and route, timing closure, DRC and LVS Should have worked on latest technology nodes (14nm or lesser) Should have worked on block level and top-level designs Good to have worked on designs without a customer flow. Strong problem-solving skills and communication skills. Ability to mentor and work closely with junior engineers Will be responsible for building a highly capable team of PD engineers at Ignitarium.

Job Requirements At Quest Global, it's not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better placeto make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster. Key Responsibilities Key Responsibilities: Delivery Leadership Lead the Define and drive end-to-end RTL-to-GDSII flows, tai...

Job Description: Job Description, As part of TLR team (top-level-route), R&D Engineer is primarily responsible for :- Place and Route, CTS, Routablity analysis with respect to congestion. Well versed in physical verification aspect, DRC, LVS, Antenna, LUP, ( chip finishing and Tapeout) Meeting RC requirements for manual/special signals Good understanding of calibre DRC/LVS/DFM,DFY, ERC and ESD latchup. Responsible for all the integrity checks (chip-finishing) and post Tapeout eJob view release, Good scripting knowledge perl and TCL, familiar with caliber, Innovus, Understanding of VLSI fabrication process, Implementing timing ECOs. Implementing IR drop fixes, RC extraction, signal EM fixes, ...

Job Requirements We are looking for the engineers with 5+ years of experience in the Physical Design Domain having flow tracer experience. This is a fulltime on-site role based in Bangalore or Hyderabad. Job Description: Engineer should be able to guide the team(sub-lead or lead based on experience), analyse/document the issues/give fixes and track the milestones. One should have the basic experience in analyzing the calibre reports too. Qualifications 5+ years of experience as a Physical Design Engineer. Bachelor's or Masters degree in the related field. Good at the basics of Digital Electronics. Implementation, STA and Physical Verification skills. Experience in tapeout using the implement...