372 Rtl Coding Jobs

You will be responsible for demonstrating expertise in RTL Coding using Verilog, System Verilog, or VHDL. Your role will involve a strong understanding of FPGA flow, Logic design, and Digital design. It is essential to have knowledge in FPGA architecture and proficiency in Tcl and Python scripting. You will be conducting Vivado testing of synthesis tool and other stages. This position does not entail Silicon RTL development or any HW flow or testing. Your communication skills are crucial, as you will be expected to communicate technical information in an organized and understandable manner. A customer-oriented approach is necessary, along with a demonstrated concern and willingness to assist customers. Good organizational skills, multitasking abilities, prioritization, and activity tracking are essential. Exceptional oral and written communication skills are also required. TekWissen Group is committed to equal employment opportunities and supports workforce diversity.,

ViewRay Systems is looking for a Senior FPGA Design Engineer to join our team in Chandigarh, India. As a Senior FPGA Design Engineer at ViewRay Systems, you will be instrumental in our mission to innovate and develop cutting-edge cancer therapy systems. You will play a crucial role in developing electrical system solutions from the conceptual stage to production, ensuring high-quality requirements for components and modules, and collaborating with the team to achieve project goals and architecture. Your responsibilities will include developing FPGA modules that cover a range of functionalities such as sensor interfaces, data acquisition systems, communication modules, signal processing, adaptive controls, memory management, and software-hardware interfaces. You will work closely with fellow engineers to expand FPGA design and integrate hardware effectively. Additionally, you will be responsible for leading electrical-software integration efforts, performing data analysis, and developing test methods to ensure the safe and effective operation of new products. To be successful in this role, you should hold a BSEE or related degree with at least 6 years of experience and demonstrate a strong understanding of FPGA development platforms like AMD/Xilinx Vivado, VHDL, RTL coding practices, and basic circuit design principles. Excellent communication skills, both verbal and written, are essential to effectively convey ideas and collaborate with team members. Experience with standards such as IEC 60601, proficiency in Python for analyzing and testing FPGA modules, and technical leadership skills are highly preferred. This is a full-time position that requires in-person work at our office in Chandigarh, India. Relocation to the area before starting work is mandatory. We offer health insurance, Provident Fund benefits, and day shift schedules. If you have a minimum of 3 years of experience as an FPGA Design Engineer and are ready to contribute to groundbreaking cancer therapy innovations, we encourage you to apply for this exciting opportunity at ViewRay Systems India Private Limited. #Job Type: Full-time #Work Location: In person in Chandigarh, India: Relocate before starting work VIEWRAY SYSTEMS INDIA PRIVATE LIMITED PLOT NO. A-40A, INDUSTRIAL FOCAL POINT, PHASE 8-EXTN, Sector 59, S.A.S.Nagar (Mohali), Distt. Mohali, Punjab -160059,

Are you looking for a unique opportunity to be a part of something great Want to join a 20,000-member team that works on the technology that powers the world around us Looking for an atmosphere of trust, empowerment, respect, diversity, and communication How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization We offer all that and more at Microchip Technology, Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchips nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and its won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Create System and FPGA designs to exercise all the use models targeted for each product mimicking end applications in a customer setting. Write system and product level validation plans for new and existing silicon products and projects; execute per plan, record and communicate results. FPGA prototyping and emulation. Understanding spec., writing emulation plan and executing per plan. Record and communicate results. Understand hardware architectures, use models and system level design implementations required to utilize the silicon features. Be an effective contributor in a cross-functional team-oriented environment. Write high-quality code in Verilog, VHDL, and C code for embedded processors. Maintain existing code. Learn new system designs and validation methodologies. Understand FPGA architectures. Be conversant with on-chip debug tool. Requirements/Qualifications: - Excellent verbal and written communication skills in English - 5+ Years experience in Design with RTL coding in Verilog and VHDL and Verification of RTL - Possess an in-depth understanding of hardware architectures, system-level IC design implementation, knowledge of how to create end-use scenarios - Optimizing code for FPGA architectures - Experience using Simulation (ModelSim) and Synthesis (Synplicity) tools - Basic knowledge of embedded processors such as ARM Cortex-M3 or RISC and familiarity with AMBA protocols APB, AHB, AXI, ACE - Working knowledge of embedded software C/C++ is also a plus - Strong technical background in FPGA prototype emulation, and debug - Strong technical background in silicon validation, failure analysis, and debug - Excellent Board level debug capabilities in a lab environment: hands-on troubleshooting skills for digital logic and analog circuit on PCBs using oscilloscopes, digital analyzers, protocol exercisers and analyzers, integrated logic analyzers (e.g. Synopsys Idenitfy, Xilinx Chipscope, Altera Signalscope, Lattice Reveal - Design with RTL coding in Verilog and VHDL is a must - Experience using Simulation (ModelSim) and Synthesis (Synplicity) tools - Hands-on systems level design and debug experience with at least two of the following high-speed serial communications protocols: PCIe Gen1/2/3, Interlaken (10.3125 Gbps), CPRI (614.4Mbps - 12.672 Gbps), SGMII or QSGMII, XAUI or HiGig/+/II, 10GBASE-R/-KR, Serial Rapid IO Travel Time: 0% - 25% To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.,

Job Overview In Arm&aposs Solutions Engineering group, our primary focus extends beyond the development of advanced System-on-Chips (SoCs). In the endeavor to deliver quality silicon we need to ensure all our sign-off checks across various domains are diligently performed. Delivering quality silicon leads to quality rewards and every effort and skill is recognized and appreciated at ARM. Our responsibilities also encompass improving methodologies, influencing EDA tools and building a knowledge base which will help with our product design. Learning and sharing knowledge is part of ARM culture and is very much appreciated and encouraged. If youre interested in working with a team of collaborative and smart engineers in developing silicon that defines the future then, you belong in ARM! Responsibilities Setting up and running Logic Equivalence check which is of signoff quality. Analyzing low power results and signing off on the structural checks run using Conformal Low Power. Provide feedback to relevant teams to ensure successful closure of blocks on time. ECO is part of every silicon now a days and the engineer needs to own up generating functional ECO for quick closure Collaborate with RTL, Synthesis and PnR implementation team to successfully close on different hard macros Work with methodology team to improve the flow Develop automation using python/perl/tcl scripting to avoid repetitive tasks and thus improve your work life balance Supporting and enabling other sign-off team members to attain efficient and quality outcomes Required Skills and Experience Bachelors/Masters with 3-5 years of minimum experience in Logic Equivalence check (Formality / LEC) and Low power (VCLP / CLP) Values communication as a key medium to nurture learning, builds trust with others and solves sophisticated problems with dependencies. Strong understanding in RTL coding (SystemVerilog, Verilog & VHDL) and RTL for Synthesis Good understanding of the concepts related to Low power synthesis, place & route, DFT. Should be proficient in any of the scripting or automation languages such as Python, Perl, TCL, Sed or Awk. Nice To Have Skills and Experience Working on ARM CPU and GPU designs would be added value Experience working on generating functional ECO using EDA tools will add value In Return ARM is proud to be an equal opportunity employer. We are committed to fostering a culture of respect, inclusion, and fairness for all. We welcome applications from all individuals, regardless of race, ethnicity, gender, age, disability, sexual orientation, religion, or background. We believe that diverse teams drive innovation, and we work hard to ensure that all our employees can thrive in an environment built on mutual respect and equal opportunity. At ARM, you get to Learn and Innovate! Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email [HIDDEN TEXT]. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodation. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and dont discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. Hybrid Working at Arm Arms hybrid approach to working is centered around flexibility, where we split our time between the office and other locations to get our work done. Within that framework, we empower groups and teams to determine their own particular hybrid working pattern, depending on the work and the teams needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email [HIDDEN TEXT] . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Hybrid Working at Arm Arms approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the teams needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and dont discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. Show more Show less

Job description About The Role As technology manager and director you would be expected to manage a team of full stack development including logic designers, micro architects, and/or verification engineers engineers responsible for developing PCIe, CXL, UXI, UCIe controllers or similar high complexity IP & subsystem development targeted for Data centers and AI business group & is reused in other Intel BUs including clients and NEX too . Responsibilities includes 1. Overall Program Execution , Stake holder management and deliver high quality first time PRQable IP solutions to demanding products in DC and AI domains including custom Silicon & IP requirements.2. You would be expected to manage team of high performing engineer and oversee end to end IP development including logic RTL design, architecture and microarchitecture and Pre-silicon simulation activities. 3. You would also be required to coordinate with FW , Emulation , SoC and Post Silicon teams. 4. You would also be responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results. 5. Drives results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environment. Qualifications Bachelor of Engineering in Electronics engineering with minimum 14-20+ years of experience/Master of Engineering with 12-18+ years of relevant experience in Digital design , UVM based verification methodologies and end to end SoC development cycle. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies'spanning software, processors, storage, I/O, and networking solutions'that fuel cloud, communications, enterprise, and government data centers around the world. Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Job description Job Description Responsibilities may be quite diverse of a technical nature. U.S. experience and education requirements will vary significantly depending on the unique needs of the job. Job assignments are usually for the summer or for short periods during breaks from school. Qualifications Masters students in EC/EE preferred, with Digital Design courses in curriculum. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

You will be responsible for developing the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Additionally, you will participate in defining the architecture and microarchitecture features of the block being designed. You will apply various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals, as well as design integrity for physical implementation. It will be your responsibility to review the verification plan and implementation to ensure design features are verified correctly. You will also resolve and implement corrective measures for failing RTL tests to ensure the correctness of features. Providing support to SoC customers to ensure high-quality integration and verification of the IP block will also be a part of your role. Furthermore, you will drive quality assurance compliance for a smooth IP SoC handoff. Qualifications: - A Master of Science (or a Master of Technology) degree in Electrical Engineering with more than six years of relevant industry experience, or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than eight years of relevant industry experience. - Expertise in microarchitecture, design, development, and integration of design blocks (IP) for system-on-chip (SoC) components. - Knowledge of power management is preferred, and experience with formal apps would be beneficial. - Expertise in Verilog and System Verilog-based logic design. - Experience in synthesis flow and timing closure, CDC, FEV. Knowledge of Python, Perl is a must. - Knowledge of considerations for performance, power, and cost optimization is desirable. - Knowledge of formal property verification using Jasper is preferred. - Demonstrate excellent self-motivation, communication, strong problem-solving, and teamwork skills. - Ability to set aggressive goals and meet/beat commitments. - Flexible enough to work in a dynamic environment and multitask seamlessly, with the ability to work independently and in a team. - Knowledge in IPs like I2C, I3C, SPI, UART, etc., is preferred. - Experience in the field of Dfx (ATPG coverage, SCAN insertion, VISA insertion, etc.) will be an added advantage. In this role, you will work within the Client Computing Group (CCG) at Intel, responsible for driving business strategy and product development for Intel's PC products and platforms. The CCG aims to deliver purposeful computing experiences that unlock people's potential, allowing each person to focus, create, and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. This role will be eligible for a hybrid work model, allowing employees to split their time between working on-site at their assigned Intel site and off-site. Please note that job posting details such as work model, location, or time type are subject to change. ,

We are seeking an experienced RTL Design Engineer to be a part of our advanced ASIC/SoC development team in Bengaluru. As an RTL Design Engineer, you will be responsible for developing high-quality, synthesizable RTL code using Verilog/SystemVerilog and integrating complex IPs and subsystems into high-performance SoCs. Collaboration with system architects, contribution to micro-architecture, and ensuring design quality through checks like Lint, CDC, and Synthesis will be key aspects of this role. Your responsibilities will include leading SoC-level integration activities, providing technical guidance in design reviews, and interfacing with cross-functional teams for smooth bring-up and signoff processes. The ideal candidate should possess a Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering, along with at least 7 years of experience in RTL design and SoC integration. Strong skills in Verilog/SystemVerilog, knowledge of SoC architecture and bus protocols, and proficiency in industry tools like Design Compiler, Spyglass, and VCS are essential for this role. If you have a deep understanding of clock/reset strategies, hierarchical design practices, timing closure, synthesis flows, and constraints development, along with strong analytical and debugging skills to resolve complex RTL and integration issues, we would like to hear from you. Join us and contribute to the design, integration, and verification of cutting-edge IPs and subsystems within high-performance SoCs.,

As an ASIC RTL Engineer at Google, you will be part of a team that is dedicated to developing custom silicon solutions to power Google's direct-to-consumer products. Your role will involve contributing to the innovation that drives the creation of products loved by millions worldwide, shaping the next generation of hardware experiences for unparalleled performance, efficiency, and integration. Your responsibilities will include: - Contributing as an ASIC RTL engineer to sub-system and chip-level integration activities. This will involve task planning, conducting code and design reviews, and contributing to sub-system/chip-level integration. - Working closely with the architecture team to develop implementation strategies that meet quality, schedule, and power performance area requirements for sub-system/chip-level integration. - Collaborating with the subsystem team to plan SOC milestones, quality checks, and guide subsystem teams with SOC level requirements such as IPXACT, CSR, Lint, CDC, SDC, UPF, etc. - Engaging with a cross-functional team of verification, design for test, physical design, emulation, and software teams to make design decisions and provide project status updates throughout the development process. To be successful in this role, you should have a Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. You should also have at least 3 years of experience in RTL coding using Verilog or SystemVerilog language, with experience in high-performance design, multi-power domains with clocking. Preferred qualifications include experience with multiple SoCs with silicon success, knowledge of ASIC design methodologies for front quality checks, and domain expertise in areas such as Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, PinMux. Additionally, an understanding of cross-domain activities involving domain validation, design for testing, physical design, and software will be beneficial. Join us at Google and be part of a team that combines the best of Google AI, Software, and Hardware to create radically helpful experiences. Help us research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful, ultimately aiming to make people's lives better through technology.,

Alternate Job Titles: Senior Staff Applications Engineer Post-Sales Application Engineer Interface IP Technical Solutions Engineer IP Integration Staff Engineer Customer Success (IP) We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a deeply skilled engineering professional with a passion for enabling the success of others You thrive in a dynamic, customer-facing environment, where your technical expertise and problem-solving abilities are tested daily You have a strong foundation in ASIC/SoC front-end design, with hands-on experience in RTL coding, synthesis, timing analysis, and formal verification Youre adept at debugging complex designs?whether in simulation, emulation, or actual silicon?and you understand the intricacies of at least one industry-standard protocol such as USB, Collaboration is at the heart of your work style: you communicate effectively with both customers and internal teams, translating technical needs into actionable solutions You take initiative, anticipate challenges, and enjoy the satisfaction of resolving tough issues Your high degree of self-motivation, personal responsibility, and analytical rigor ensures that you deliver results even under pressure You are eager to share best practices, drive continuous improvement, and contribute to the broader success of your team and customers alike If you are excited about tackling new challenges, committed to excellence, and ready to make a real impact in the semiconductor industry, you will find your place at Synopsys, What Youll Be Doing: Providing expert technical support to customers integrating Synopsys Interface IPs into their SoC designs, Analyzing and resolving complex issues related to IP configuration, integration, and usage across various platforms, Interfacing directly with customers to understand their design and verification flows, identifying both current and future needs, Collaborating with cross-functional teams to address and resolve customer challenges efficiently, Debugging and troubleshooting designs in simulation, emulation, and silicon environments, Driving the adoption of best practices and lessons learned from customer interactions back into product development, Proactively engaging with customers during integration and silicon debug phases to ensure successful deployment, The Impact You Will Have: Accelerating customer time-to-market by providing timely and accurate technical guidance, Enhancing customer satisfaction and trust in SynopsysIP solutions through effective support and problem resolution, Contributing real-world feedback to product development, improving the robustness and usability of Synopsys IP, Reducing post-sales escalations and ensuring smooth IP integration for major industry players, Fostering long-term customer partnerships by consistently exceeding expectations, Helping shape the direction of next-generation IP products based on customer needs and industry trends, What Youll Need: Bachelors or Masters Degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science, Minimum 8 years of relevant experience in ASIC/SoC front-end design, including RTL coding (Verilog), logic and clock tree synthesis, static timing analysis, and equivalence checking, Full understanding of digital design methodologies and tools, including formal verification, Domain knowledge of at least one interface protocol ( e-g , USB); experience with additional protocols (PCIe, DDR, SATA, HDMI, MIPI, Ethernet) is a plus, Experience supporting at least one ASIC/SoC tape-out from concept to full production, Strong silicon debug and troubleshooting skills are highly desirable, Who You Are: Technically creative, results-oriented, and able to manage multiple priorities efficiently, Strong communicator who can explain complex technical concepts to diverse audiences, High degree of self-motivation and personal responsibility, Excellent analytical, reasoning, and problem-solving skills with keen attention to detail, Collaborative team member who thrives in cross-functional environments, The Team Youll Be A Part Of: You will join the Solutions Group at Synopsys, a highly collaborative team dedicated to delivering world-class IP solutions and customer success Working closely with experts in design, verification, applications engineering, and product development, you will be at the forefront of supporting and enabling the most innovative semiconductor companies across the globe Our team values knowledge sharing, continuous learning, and a proactive approach to solving the industrys toughest challenges, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process, Show

This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; - Grade Specific Focus on Electrical, Electronics and Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in straight forward situations and generates solutions. Contributes in teamwork and interacts with customers.

Job Title: Lead RTL Design Engineer Microarchitecture (10+ Years) Company: ACL Digital Experience: 10 to 15 Years Location: [Insert Location or Remote/Hybrid] Job Type: Full Time Contact Email: prabhu.p@acldigital.com Contact Number: +91-8754387484 Job Description: ACL Digital is hiring a Lead RTL Design Engineer with strong expertise in microarchitecture and RTL design . This is a leadership role ideal for professionals with 10+ years of experience in digital design, ASIC/SoC development, and hands-on RTL coding. Key Responsibilities: Own microarchitecture and RTL development of complex IPs or subsystems. Lead block-level design from spec to synthesis and signoff. Drive RTL design using Verilog/SystemVerilog , ensuring quality and PPA targets. Guide and mentor junior RTL engineers across project cycles. Collaborate with architecture, verification, physical design, and firmware teams. Support STA, CDC, lint, synthesis, and design reviews. Contribute to methodology improvements and automation. Required Skills: 10+ years of hands-on experience in RTL design and microarchitecture . Expertise in Verilog/SystemVerilog and digital logic design. Strong knowledge of AXI, AHB , and other AMBA protocols. Experience in low-power design , clock gating, UPF, and STA. Worked on at least 1–2 successful tape-outs in a lead role. Excellent debugging, review, and technical communication skills. Good to Have: Experience with RISC-V, AI/ML accelerators, GPUs, or DSPs . Scripting knowledge: Python, Perl, or TCL. Familiarity with formal verification and FPGA prototyping . Education: B.E./B.Tech or M.E./M.Tech in ECE, Electrical, or Computer Engineering. (Ph.D. is a plus) Why Join Us? Work on cutting-edge technologies at advanced nodes (7nm/5nm/3nm). Lead high-impact projects with global teams. Grow into senior technical or architectural roles. Apply Now: Email: prabhu.p@acldigital.com Phone: +91-8754387484

As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. This will involve working on a variety of components including yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to bring cutting-edge products to the market. Collaboration with cross-functional teams is a key aspect of this role to ensure that solutions meet performance requirements. The ideal candidate should have a minimum of 4 to 6 years of work experience in ASIC RTL Design. Experience in Logic design, micro-architecture, and RTL coding is essential. Hands-on experience with the design and integration of complex multi clock domain blocks is a must. Proficiency in Verilog/System-Verilog and knowledge of AMBA protocols such as AXI, AHB, APB, clocking/reset/debug architecture are also required. Candidates should have experience in Multi Clock designs and Asynchronous interface. Familiarity with ASIC development tools like Lint, CDC, Design compiler, and Primetime is necessary. An understanding of Automotive System Designs, Functional Safety, Memory controller designs, and microprocessors would be advantageous. The role involves close collaboration with Design verification and validation teams for pre/post Silicon debug. Prior experience in Low power design is preferred. Additionally, expertise in Synthesis and a solid grasp of timing concepts for ASIC are must-haves for this position.,

Job Summary: Seeking an experienced FPGA developer to join our team and work on the design and development of complex FPGA-based systems. The ideal candidate will have a strong background in FPGA design, verification, and implementation, as well as experience working with hardware and software engineers to integrate FPGA designs into larger systems.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. About The Role As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Additional About The Role Additional About The Role Job Role * Work with multiple SOC Design teams to rollout robust Logic Synthesis, UPF synthesis, QoR optimization and netlist Signoff flows* Provide implementation flows support and issue debugging services to SOC design teams across various site* Develop and maintain 3rd party tool integration and product enhancement routines * Should lead implementation flow development effort independently by working closely with design team and EDA vendors * Should drive new tool evaluation, methodology refinement for PPA optimization Skill Set * Proficiency in Python/Tcl * Familiar with Synthesis tools (Fusion Compiler/Genus), * Fair knowledge in LEC, LP signoff tools* Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking* Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus* Should be sincere, dedicated and willing to take up new challenges Experience 13+ years of experience in RTL,UPF & Physical aware Synthesis for cutting edge technology nodes, logic equivalence checking, Scripting and Netlist Timing Signoff Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience 3+ years of experience in RTL,UPF & Physical aware Synthesis for cutting edge technology nodes, logic equivalence checking, Scripting and Netlist Timing Signoff Proficiency in Python/Tcl * Familiar with Synthesis tools (Fusion Compiler/Genus), * Fair knowledge in LEC, LP signoff tools * Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking * Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus * Should be sincere, dedicated and willing to take up new challenges Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Good knowledge on AMBA protocols (CHI/AXI/AHB) Knowledge of ARM architecture be an added advantage Exposure to low power methodology with understanding of UPF Execute verification plans, regression enabling for all features and, debug of the test failures Hands-on experience of GLS and timing simulations Exposure to Formal verification Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: 3 to 15 years of work experience in ASIC/SoC Design Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts is a plus. Experience creating padring and working with the chip level floorplan team is an added advantage. Excellent oral and written communications skills Proactive, creative, curious, motivated to learn and contribute with good collaboration skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: About The Role Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in. You will be joining a successful engineering team whose deliveries can be found in billions of mobile, compute and IoT products worldwide. Based out of Qualcomm's Bangalore office, this role offers a position in Low Power controller IP cores and subsystem digital design targeted for variety of industry leading Snapdragon SoCs for mobile, compute, IoT and Automotive markets. Key Responsibilities Micro-architecture and RTL design for Cores / subsystems. Work in close coordination with Systems, Verification, SoC, SW, PD & DFT teams for design convergence. Enable SW teams to use HW blocks. Qualify designs using static tool checks including Lint, CDC, LEC and CLP. Synthesis, LEC and Netlist CLP Report status and communicate progress against expectations. Preferred Qualifications 4 to 10 years of strong experience in digital front end design (RTL design) for ASICs Expertise in RTL coding in Verilog/SV/VHDL of complex designs with multiple clock domains and multiple power domains Familiar with UPF and power domain crossing Experience in Synthesis, Logical Equivalence checks, RTL and Netlist CLP Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI Experience in low power design methodology and clock domain crossing designs Experience in Spyglass Lint/CDC checks and waiver creation Experience in formal verification with Cadence LEC Understanding of full RTL to GDS flow to interact with DFT and PD teams Expertise in Perl/TCL/Python language Experienced in database management flows with Clearcase/Clearquest. Expertise in post-Si debug is a plus Excellent oral and written communications skills to ensure effective interaction with Engineering Management and team members. Team player, self-motivated, should be able to work with minimal supervision. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Required Qualifications Bachelor's degree /masters degree in Electronics & Tele Engineering, Microelectronics, Computer Science, or related field. 9+ years RTL Design/Hardware Engineering experience or related work experience. Skills/Experience Required Strong Domain Knowledge on RTL Design , implementation, and integration. Experience with RTL coding using Verilog/VHDL/System Verilog. Experience in micro-architecture & designing cores and ASICs. Familiar with the Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc. Exposure in scripting (Pearl/Python/TCL). Strong debugging capabilities at simulation, emulation, and Silicon environments. Collaborate closely with cross-function team located in different time zone to research, design and implement performance and power management strategy for product roadmap. Good team player. Need to interact with the other teams/verification engineers proactively. Responsibilities Design and lead all Front-end design activities for Display Sub-system that deliver cutting edge solution for various Qualcomm business unit like VR, AR, Compute, IOT, Mobile. Perform RTL design, simulation, synthesis, timing analysis, lint check, clock domain crossing check, conformal low power check, and formal verification for IP blocks. Work closely with technology/circuit design team to close IP block specification/requirement. Work closely with verification/physical design team to complete the IP design implementation. Support SoC team to integrate Display Sub-system IP solution into various SoC chips and front-end design flows. Work closely with system/software/test team to enable the low power feature in wireless SoC product. Evaluate new low-power technologies and analyze their applications to address requirements. Understand and perform block & chip-level performance analysis & identify performance bottleneck and provide required solution. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Preferred Qualifications 2-9 years of experience in SoC design Educational Requirements2+ years of experience with a Bachelors/ Masters degree in Electrical engineering Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail myhr.support@qualcomm.com or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Principal Design Verification Engineer Job Overview MIPS is seeking a highly experienced Senior Staff Design Verification Engineer with over 15 years of industry experience to lead verification efforts focused specifically on Coherency Manager and Cache Controller components. The successful candidate will have extensive hands-on experience utilizing advanced verification methodologies, including constrained random testing, formal verification, and coverage-driven verification. This senior role involves close collaboration with CPU architects, designers, and cross-functional global teams to ensure high-quality, high-performance processor designs. Key Responsibilities Lead and drive verification activities for Coherency Manager and Cache Controller IP to closure. Collaborate closely with design teams and architects to thoroughly understand and interpret microarchitectural and functional specifications. Develop comprehensive verification plans and execute these plans through testbench creation, test case development, and rigorous analysis. Create directed and constrained random test cases in SystemVerilog, Assembly, and C to verify complex coherency and cache management behaviors. Employ formal verification techniques to augment random verification and ensure exhaustive coverage. Analyze verification coverage metrics to identify and close coverage gaps efficiently. Automate and optimize verification flows and regression environments using scripting languages like Python, Perl, TCL, or Shell. Mentor junior verification engineers, providing technical guidance and leadership within the verification team. Qualifications Master`s degree or higher in Electronics, Electrical, Computer Engineering. 15+ years of relevant verification experience, specifically in CPU or complex SoC verification. Proven expertise in verification of Multicore and Multicluster Coherency, Cache Controllers, or similar blocks. Deep knowledge and practical experience with verification methodologies such as UVM, constrained random, and formal verification. Proficiency in SystemVerilog, Verilog, C, C++, and Assembly. Solid understanding of interconnect and coherency protocols such as AXI, ACE, OCP, CHI. Strong scripting skills in Python, Perl, TCL, or Shell. Experience with CPU architectures, particularly RISC-V, ARM, or MIPS. Preferred Experience Experience with RISC-V architecture. Familiarity with functional safety standards (e.g., ISO 26262). Prior exposure to FPGA prototyping and emulation platforms. What MIPS Offers Opportunity to be part of a dynamic team creating industry-leading RISC-V processors. Autonomy with extensive support from industry experts. Opportunities for significant career growth and technical advancement. Competitive compensation and comprehensive benefits package About MIPS MIPS is a pioneer in RISC-based computing with a legacy of innovation in high-performance microprocessor design. Today, MIPS continues this legacy by leading the adoption and advancement of the RISC-V architecture, delivering scalable processor solutions for cutting-edge computing applications.

To achieve real outcomes, we know that experience is the most important requirement for networking teams and the people they serve Delivering an experience-first, AI-Native Network pivots on the creativity and commitment of our people It requires a consistent and committed practice, something we call the Juniper Way ASIC Engineer Design Silicon Systems Technology Group (SST) seeks ASIC Design Engineers to develop next generation of ASICs for new core routers, switches, and firewalls Opportunity Snapshot: We are looking to hire sharp ASIC Design Engineer with excellent communication and leadership skills You will be part of a fast paced team responsible for delivering high-speed ASICs for large, complex systems You will have a significant opportunity to interact with system design teams across geographies Open communications, empowerment, innovation, teamwork and customer success are the foundations of the team with "pay for performance" culture Thus, you set your own limits for learning, achievements and rewards Responsibilities: Define and architect high-performance blocks for the latest, most advanced networking ASICs Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power Collaborate with the verification team in the development of the testplan and assist in debugging test failures Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes Required Skills: 5+ years of ASIC design experience Strong Verilog RTL coding skills Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus Knowledge of high performance memory subsystems Knowledge of multi-domain clock synchronization and high-speed serial interfaces Strong problem solving and ASIC debugging skills Excellent written and verbal communications skills MSEE or BSEE is required

Role : RTL Software Testing Engineer Role does not involve Silicon RTL development and neither any HW flow or testing. Work Location: Hyderabad Qualification: B.E / B. Tech or M. Tech in ECE / CS / EEE Experience Level : Minimum 2+ years Job Description Excellent Knowledge in Tcl, Python scripting. to test cases.(This would be the primary responsibility) Vivado testing of synthesis tool and other stages. RTL Coding in Verilog, System Verilog, or VHDL Strong understanding of FPGA flow, Logic design, Digital design etc. Knowledge in Xilinx FPGA architecture Communication Skills: Ability to communicate technical information in an organized and understandable fashion. Customer oriented approach with a demonstrated concern and desire to work with and assist customers. Good organizational skills with the ability to multitask, prioritize, and track many activities. Outstanding oral and written communication skills.

FPGA Engineer by Advantal Technologies | Jul 25, 2025 | Jobs | 0 comments Location: Bengaluru (Client Site) Job Type: Full-time Experience: 3-7 years Notice Period: 0-15 days (immediate joiners preferred) No. of Positions: 1 Lead & 4 Engineers About the Role: We are seeking a skilled FPGA Engineer with 3 7 years of experience in RTL design using Verilog, along with expertise in Xilinx MPSoC platforms, MicroBlaze processor development, and embedded system security aspects such as authentication, encryption/decryption, and certificates. The ideal candidate will play a key role in architecting and implementing secure, high-performance digital logic systems. Requirement: Experience band 3-7 years Experience in RTL coding using Verilog Experience on development on Xilinx MPSoC (preferably ZCU 106/104) Hands-on experience with Xilinx Vivado and Vitis Desirable to have experience with MISRA C coding guidelines Desirable to have experience with DO-254 Desirable to have experience with Microblaze Desirable to have experience in security aspects of authentication, certificates, encryption/decryption How to Apply: If you are passionate about embedded systems and meet the above requirements, we would love to hear from you. For more information, connect with us at : +91 91312 95441 Location: Bengaluru (Client Site) Job Type: Full-time Experience: 3-7 years Notice Period: 0-15 days (immediate joiners preferred) No. of Positions: 1 Lead & 4 Engineers About the Role: We are seeking a skilled FPGA Engineer with 3 7 years of experience in RTL design using Verilog, along with expertise in Xilinx MPSoC platforms, MicroBlaze processor development, and embedded system security aspects such as authentication, encryption/decryption, and certificates. The ideal candidate will play a key role in architecting and implementing secure, high-performance digital logic systems. Requirement: Experience band 3-7 years Experience in RTL coding using Verilog Experience on development on Xilinx MPSoC (preferably ZCU 106/104) Hands-on experience with Xilinx Vivado and Vitis Desirable to have experience with MISRA C coding guidelines Desirable to have experience with DO-254 Desirable to have experience with Microblaze Desirable to have experience in security aspects of authentication, certificates, encryption/decryption How to Apply: If you are passionate about embedded systems and meet the above requirements, we would love to hear from you. For more information, connect with us at : +91 91312 95441