115 Scan Insertion Jobs

1. Minimum of three years of hands-on Test Development experience (DFT, EDA tools, etc..) 2. Solid knowledge & experience in defining test solutions for multi-million gate SOC (Scan & MBIST) with Mixed Signal IPs (PLL, High Speed SERDES, DDR) 3. Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test 4. Strong understanding of relationships between Hardware, Firmware and Software in FPGA and/or multi-processors SOC. Past experience in leading the team to successful silicon bring-up and problem solving in a complex system 5. Strong planning, project, and people management skills required. Must have experience developing managers and individual contributors 6. Experienced hands-on technical manager not afraid to dig into details to provide technical direction Proven track record of delivering results and meeting quality, cost, and time-to-market objectives 7. Ability to collaborate with overseas colleagues to define strategy, plan, and execute across the larger, global organization 8. Stakeholder influencing and people skills must be excellent. 9. Needs to be able to set aggressive goals and manage risks effectively 10. Must have a thorough understanding of tool development methodology. 11. Ability to manage software development tasks associated with specifying, developing, scheduling, and debugging according to current and future tool requirements. 12. MS or Ph.D. Engineering degree (EE or equivalent) with 3-7 years semiconductor industry experience.

About MIPS MIPS is a leader in high-performance RISC-V CPU IP, enabling innovation across automotive, AI, data center, and embedded markets Our engineering teams are building the next generation of compute solutions, and we are looking for passionate talent to join us in shaping the future of semiconductors, Position Overview The DFT Manager leads and develops the engineering team responsible for designing and deploying advanced Design-for-Test solutions in semiconductor chip development This role focuses on building robust DFT architectures?including ATPG, MBIST, LBIST, analog test solutions?and implements repeatable methodologies and flows that ensure rapid, optimized test pattern generation and efficient project execution, Key Responsibilities Lead, mentor, and manage the DFT engineering team, overseeing daily operations and technical development, Define and deploy DFT architecture for chips with features such as Automatic Test Pattern Generation (ATPG), Memory Built-In Self-Test (MBIST), Logic Built-In Self-Test (LBIST), and analog test solutions, Develop and optimize test pattern generation methodologies, prioritizing test time reduction and manufacturing efficiency, Establish and maintain standardized, repeatable DFT methodologies and flows to consistently achieve fast turnaround and reliable results across projects, Collaborate cross-functionally to integrate DFT features and requirements throughout the silicon development lifecycle, Automate test program, script development for maximum coverage and reduced test cost, Continuously analyze test performance data and apply lessons learned for iterative improvement, Promote innovation and continuous improvement by evaluating new trends, tools, and best practices, Document DFT specifications, standards, and re-use strategies for knowledge sharing and future use, Required Qualifications Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field, 8+ years of hands-on DFT experience plus proven leadership of DFT teams on SoCs, Expertise in test pattern generation, ATPG, MBIST, LBIST, analog test development, and scan insertion, Significant experience optimizing test time through efficient DFT strategies and tool use, Proven ability to design and implement repeatable DFT flows and reusable test IP, Proficiency with EDA tools (Synopsys, Cadence, Mentor Graphics), and scripting (Python, Perl, TCL), Strong analytical, organizational, leadership, and communication skills, Desired Attributes Strategic thinker who translates customer, product requirements into practical, innovative test solutions, Inspirational leader focused on team growth, technical excellence, and methodology re-use, Proactive, detail-oriented professional committed to efficiency, quality, and process improvement, Why Join MIPS Be part of a team driving innovation in RISC-V CPU IP and SoC development, Work on cutting-edge semiconductor designs with global impact, Collaborative, growth-focused environment with opportunities for innovation and leadership, Show more Show less

Desired Profile : Bachelor's / Master's degree in engineering from EEE / E&C Expertise in managing and leading technical teams across different continents Expertise in leading business strategy in the VLSI / Semiconductor Services / foundry business industry Expertise in managing end to end projects including tape outs Must be willing to travel at short notice, relocate as per business needs Must be willing to work onsite (customer premises) as per business needs Expertise in working on any of the following technologies is mandatory : ANALOG MIXED SIGNAL LAYOUT - finfet / high speed / planar technology nodes ANALOG DESIGN - data converter / power management / pll ANALOG VERIFICATION ASIC PHYSICAL DESIGN ASIC RTL DESIGN DFT DESIGN - jtag / mbist / lbist / scan DIGITAL VERIFICATION - OVM / UVM / VMM EDA CAD FLOW - tcl / primetime / design compiler Job Specs : Responsible for meeting delivery, revenue, operational, customer satisfaction targets and team management Hire and manage high caliber technical teams across GCC, ODC and onsite Develop, Drive high quality business / technology strategy and oversee the translation of this strategy into tactical action Uphold the organization's culture and long term missions Liaise and negotiate with various partners around the world to bring in new partnership. Synergize all company's resources and talents for the growth of company's business Oversee all sectors and fields of the business to ensure the company's competitiveness Provide leadership, direction, major decision making and resolution support to operations, projects and staff. Build strategic business partnerships and execute these opportunities through collaboration with external partners Location - Bengaluru,Bhubaneswar,Kolkata,Kochi,Mysuru

Minimum of ten years of hands-on Test Development experience (DFT, EDA tools, etc..) Solid knowledge & experience in defining test solutions for multi-million gate SOC (Scan & MBIST) with Mixed Signal IPs (PLL, High Speed SERDES, DDR) Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test Strong understanding of relationships between Hardware, Firmware and Software in FPGA and/or multi-processors SOC. Past experience in leading the team to successful silicon bring-up and problem solving in a complex system Strong planning, project, and people management skills required. Must have experience developing managers and individual contributors Experienced hands-on technical manager not afraid to dig into details to provide technical direction Proven track record of delivering results and meeting quality, cost, and time-to-market objectives Ability to collaborate with overseas colleagues to define strategy, plan, and execute across the larger, global organization Stakeholder influencing and people skills must be excellent. Needs to be able to set aggressive goals and manage risks effectively Must have a thorough understanding of tool development methodology. Ability to manage software development tasks associated with specifying, developing, scheduling, and debugging according to current and future tool requirements. MS or Ph.D. Engineering degree (EE or equivalent) with 3-10 years semiconductor industry experience.

About The Role About The Role Will be responsible for Designing and Implementing DFT techniques. Should hava a good understanding of Memory BIST/Scan /OnChip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/LogicBIST on complex SOCs to improve testability. Test Modes implementation and verification, scan insertion including on-chip compression. Implementing, integrating and verifying memory BIST and boundary scan. ATPG Test vector (Stuck-at/At-speed/Path delay/SDD/IDDQ/Bridging fault) generation with high test Coverage and simulations at gate level with timing (SDF). Basic understanding of complete SOC design and flow. Cross functional teams interaction for issue resolution. Participate in driving new DFT methodology and solutions to improve quality, reliability and insystem test and debug capability. Hiring candidate with these specific personal characteristic and qualifications. Mentoring junior engineers and drive innovation/automation. Excellent in problem solving and analytical skills. Excellent communication, team work and networking skills. Primary Skills Should Have Good understanding of Design and DFT Architecture. Should have been part of atlest 3 Tapeout SoC. Well Versed with ATPG Tools & MBIST Tools. Secondary Skills Team Player, Strong Business Acumen with understanding of organizational issues (conflict resolution between stakeholders). Familiarity with Desired Flexibility and adaptability with respect to project management.

Who You'll Work With You will be in the Silicon One development organization as an ASIC DFT Engineer in Bangalore India with a primary focus on Design-for-Test. You will work with DFT Lead, Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL. Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows. The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship. Who You Are You are an ASIC Design for Test Hardware Engineer with 4-8 years of related work experience with a broad mix of technologies. Minimum Qualifications: Bachelor's or a Masters Degree in Electrical or Computer Engineering required with at least 4 years of experience. Knowledge of the latest innovative trends in DFT, test and silicon engineering. Experience with Jtag protocols, Scan insertion and ATPG. Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets. Knowledge of the latest innovative trends in DFT, test and silicon engineering. Experience working with Gate level simulation, debugging with VCS and other simulators. Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687 Strong verbal skills and ability to thrive in a multifaceted environment Scripting skills: Tcl, Python/Perl. Preferred Skills: Test Static Timing Analysis Post silicon validation using DFT patterns.

Job Area :Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum of 5+ years experience in the area of ASIC/DFT -In depth knowledge of DFT concepts -In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors -Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (TK, TetraMax) -Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem solving skills -Excellent communication and team work skills and good English is required

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. 8+ years experience in the area of ASIC/DFT -In depth knowledge of DFT concepts -In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors -Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (TK, TetraMax) -Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem solving skills -Excellent communication and team work skills and good English is required

Job Description: We are looking for DFT Engineers with 3+ years of experience in Scan, MBIST, and ATPG. The role involves developing and implementing advanced DFT methodologies to ensure testability and high-quality silicon. Key Responsibilities: Hands-on experience with Scan insertion and Scan DRC/Coverage debug. Strong background in ATPG pattern generation and fault coverage analysis. Expertise in Gate-level simulations (Zero delay / Timing delay simulations). Worked on JTAG protocols. Experience in MBIST insertion, verification, and debug. Proficiency in Perl/Tcl scripting for automation of flows. Familiarity with timing verification, formal verification, and PD flow (a plus). Ability to debug and optimize DFT implementation for quality silicon.

Job Description Will be responsible for Designing and Implementing DFT techniques. Should hava a good understanding of Memory BIST/Scan /OnChip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/LogicBIST on complex SOCs to improve testability. Test Modes implementation and verification, scan insertion including on-chip compression. Implementing, integrating and verifying memory BIST and boundary scan. ATPG Test vector (Stuck-at/At-speed/Path delay/SDD/IDDQ/Bridging fault) generation with high test Coverage and simulations at gate level with timing (SDF). Basic understanding of complete SOC design and flow. Cross functional teams interaction for issue resolution. Participate in driving new DFT methodology and solutions to improve quality, reliability and insystem test and debug capability. Hiring candidate with these specific personal characteristic and qualifications. Mentoring junior engineers and drive innovation/automation. Excellent in problem solving and analytical skills. Excellent communication, team work and networking skills. Primary Skills Should Have Good understanding of Design and DFT Architecture. Should have been part of atlest 3 Tapeout SoC. Well Versed with ATPG Tools & MBIST Tools. Secondary Skills Team Player, Strong Business Acumen with understanding of organizational issues (conflict resolution between stakeholders). Familiarity with Desired Flexibility and adaptability with respect to project management

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum of 7+ years experience in the area of ASIC/DFT -In depth knowledge of DFT concepts -In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors -Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (TK, TetraMax) -Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem solving skills -Excellent communication and team work skills and good English is required

General Summary: Minimum 4 to 6 years of work experience in ASIC RTL Design. Strong expertise in MBIST insertion, Scan insertion, and ATPG. Proficiency with SMS MBIST insertion tool is mandatory. Must have hands-on experience with handling sub systems with multiple memory types and grouping. Additional experience in memory redundancy, BIRA analysis, and repair solutions is highly desirable. Solid understanding of multi-memory bus interfaces and functional safety BIST requirements is a strong advantage. Exposure to Automotive System Designs, Memory Controller Designs, and Microprocessors is a plus. Experience in low power design and synthesis/timing concepts for ASICs is preferred Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

You have a great opportunity as a DFT Lead Engineer with 6+ years of experience at a work location in Bangalore or Hyderabad. As a DFT Lead Engineer, you will be responsible for the DFT implementation of the latest products, including scan insertion, ATPG, LBIST, and MBIST. Your role will involve verifying the DFT implementation and delivering test patterns for production testing. Additionally, you will support Silicon bring-up activities to ensure the highest stability of the test pattern. In this position, you will contribute to the overall microcontroller DFT methodology and coordinate DFT work packages. You will be required to engage in hands-on work, provide status reports, and collaborate with project management, layout team, and test engineering. Proficiency with Synopsys tools such as TetraMAX, Verdi, and DFT Compiler is essential for this role. The ideal candidate should have a solid understanding of scan chains, stuck-at/fault models, and test coverage. If you are looking for a challenging role that allows you to showcase your DFT expertise and work on cutting-edge technologies, this position is perfect for you.,

We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBM’s chip design team. As a member of DFT team, you will be required but not restricted to insertion, pattern generation, simulation, validation, characterization, delivery to TAE, IBM’s Hardware Bring-up and Silicon Debug Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Hands-on experience in DFT on complex designs involving scan insertion, compression, MBIST, ATPG, simulations and IP integration and validation. Proven expertise in analysing and resolving DRCs/TSVs . Hands-on experience in pattern generation for various fault models, pattern retargeting and debugging techniques to address low coverage issues. Hands-on experience with Gate-Level DFT verification, both with and without timing annotations. Well versed with industry standard test techniques and advanced DFT features like SSN, IJTAG, IEEE 1500, Boundary scan , LBIST and STA constraint delivery . Hands on experience on industry standard tools used for DFT features Proficiency in scripting languages such as TCL, Perl or Python to automate design and testing tasks. Worked with cross functional teams like design, STA & tester teams for ensuring top quality of DFT deliverables and DFT support and hand offs. Excellent analytical and problem-solving skills, with a keen attention to detail. Strong communication and collaboration skills, with the ability to work effectively within cross-functional teams Preferred technical and professional experience Fundamentals in micro controller architecture, embedded firmware, functional verification and RTL design Experience working with ATE engineers for silicon bring up, silicon debug and validation. Experience in Asics/processor flow and post silicon validation

We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBM’s chip design team. As a member of DFT team, you will be required but not restricted to insertion, pattern generation, simulation, validation, characterization, delivery to TAE, IBM’s Hardware Bring-up and Silicon Debug Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Hands-on experience in DFT on complex designs involving scan insertion, compression, MBIST, ATPG, simulations and IP integration and validation. Proven expertise in analysing and resolving DRCs/TSVs . Hands-on experience in pattern generation for various fault models, pattern retargeting and debugging techniques to address low coverage issues. Hands-on experience with Gate-Level DFT verification, both with and without timing annotations. Well versed with industry standard test techniques and advanced DFT features like SSN, IJTAG, IEEE 1500, Boundary scan , LBIST and STA constraint delivery . Hands on experience on industry standard tools used for DFT features Proficiency in scripting languages such as TCL, Perl or Python to automate design and testing tasks. Worked with cross functional teams like design, STA & tester teams for ensuring top quality of DFT deliverables and DFT support and hand offs. Excellent analytical and problem-solving skills, with a keen attention to detail. Strong communication and collaboration skills, with the ability to work effectively within cross-functional teams Preferred technical and professional experience Fundamentals in micro controller architecture, embedded firmware, functional verification and RTL design Experience working with ATE engineers for silicon bring up, silicon debug and validation. Experience in Asics/processor flow and post silicon validation

At Cadence, we are seeking a talented individual to join our team and contribute to the world of technology. In this role, you will collaborate closely with various cross-functional teams across different locations to ensure alignment on project goals and deliverables. Your responsibilities will also include mentoring junior engineers, fostering innovation, and driving automation initiatives. The ideal candidate should hold a BE/B.Tech/M.E/M.Tech degree with at least 7 years of relevant work experience. A strong understanding of Design for Testability (DFT) concepts and excellent communication skills are essential. Additionally, hands-on experience with industry-standard EDA tools and logic simulators from various vendors is required. Proficiency in ATPG tools like Cadence Modus, RTL lint tools such as Jasper, and scan insertion is highly valued. Candidates with programming skills in Perl, Tcl, Python, or other scripting languages will be preferred. Experience in post-silicon validation, ATE debug, and support is desirable. Familiarity with RTL-to-GDS flow, synthesis, scan insertion, STA, and IR drop tasks is a plus. A good grasp of logic design, RTL implementation, verification, logic synthesis, Logic Equivalent Checking, and Static Timing Analysis is advantageous. As part of the team, you will play a crucial role in developing new DFT methodologies and solutions to enhance quality, reliability, and in-system test and debug capabilities. If you are passionate about making a difference in the technology industry and enjoy tackling complex challenges, we invite you to join us in our mission to solve problems that others cannot.,

Role & responsibilities Handling hierarchical scan insertion ATPG flow. Integration and Verification of MBIST at RTL level. RTL Integration, Verification, gate level Coverage and GLS enablement for LBIST. Implementation and Verification of IEEE1149.1 JTAG, IJTAG standards. Post silicon debug activities for DFT patterns. Collaboration with RTL design, Physical design and verification teams will be a daily aspect of the role. Preferred candidate profile Degree/PG in Electrical/Electronic Engineering, Computer Engineering or Computer Science. At least 12+ years of experience in related domains and have working knowledge of industry standard digital EDA toolkits. Must be conversant on EDA tools such Tessent, Genus, FC, VCS and Conformal/Formality etc. Strong scripting skills for Automation and Flow development using PERL/TCL/Python. Cando attitude, openness to new environment, people and culture. Strong communication skills (written and verbal), problem solving, attention to detail, commitment to task, and quality focus. Ability to work independently and as part of a team. Mentor and guide junior engineers in DFT.

You should have a minimum of 4 years of experience in the field. You must be proficient in using Synthesis and netlist validation tools, particularly LEC and Spyglass checks, as well as scan insertion and DRC debug. It is essential to be well-versed in both Synopsys and Mentor Graphics DFT flows. Your expertise should also include experience in Scan Compression for Hierarchical and Modular EDT, ATPG, and Coverage debug, along with the ability to manage multiple clock domains and familiarity with the OCC flow. You should have practical experience in BIST and BISR insertion and Validation with SMS and MBIST Architect. Hands-on experience with JTAG, IJTAG, and SSN is required. You should be familiar with P1500 and have experience in managing wrapper cells and test integration. Knowledge of INTEST and EXTEST modes, as well as working knowledge on Cell Aware ATPG, is important for this role. Additionally, strong communication and Automation skills are a must for this position.,

Career Opportunity with Burckhardt Compression We are seeking motivated and experienced professional who can effectively contribute to the role deliverables connected with position below In this position you can actively participate to our growth and make a significant impact in a fast-paced environment as: Position: Manager Other IT Applications Location: Pune Your contributions to organisation's growth: Manage the Other IT Applications team across geographies and time zones, Support strategic recruitment and role alignment, while collaborating with HR and matrix managers to define role requirements, conduct interviews, and onboard talent aligned with project needs, Be responsible for our Other IT Applications solution: daily operations, roadmap and strategy, Act as a delivery manager for all delivered solutions: change requests, projects, incident management, process optimization/automation, user support, etc Provide leadership and strategy to the Other IT Applications team, Overlook and monitor team delivery Review, secure, and monitor operational performance in collaboration with other functional managers, Develop and maintain functional and personal competencies of the team, Monitor team morale, conduct regular check-ins, and support initiatives like recognition programs, and career progression plans, Establish solid working relationships with business stakeholders and an understanding of segment business models, Advise senior stakeholders of capabilities and possible solutions to business challenges, Represent the team perspective within the GSC, Global Architecture, Business Process Ecosystem, User community, relevant Boards, and Projects, Apply industry best practices around solutions' demand management, change management, agile operations, and contribute to the establishment of a group wide efficient operating model, Raise standards and promote the Other IT Applications landscape to the function heads for broad buy-in, Drive cultural change towards user adoption of digital processes and tools, Manage suppliers, contracts, and budget allocated to the Other IT Appl landscape, in close collaboration with other delivery managers, the architecture team, Procurement, Legal, etc Actively support the transformation of the Other IT Applications architecture to cloud Expertise you have to bring in along with; Degree in relevant field such as computer science or business administration or equivalent professional qualification, Built, led and developed an application management team, In depth knowledge in application management, Significant experience of managing IT applications, incorporating support and project management, including a number of implementations, Proven track record in system design, setup, implementation and rollout in a multi-geography setup, Significant experience managing teams comprising permanent staff, consultants, and contractors (onand possibly offshore), Leadership experience with globally distributed cross-functional teams, Experience working with senior leadership and confidence in communication at all levels Special requirements: Ability to define key questions and provide answers on optimization of processes and applications, Ability to thrive in a dynamic and changeable industrial environment, Strong business partner, good understanding of the company's business and processes We Offer We have a very free culture, inspiring employees to involve in various activities of their interests, Our flexible working models will allow you to combine private interests with work, Employee Connect, Engagement events and feedback culture enhances our reach and gives us an opportunity to continuously improve, Performance and appreciation awards, Sports activities and Klib Library to energize you, We proudly do encourage diversity and inclusion in thoughts and in spirit, A winner of GreenCo Gold and other various ISO certifications, we encourage you to inhibit the same to contribute in a much greener tomorrow! We do aspire to be Great Place to Work soon to provide you an enticing career with us, HR Team Burckhardt Compression India Burckhardt Compression creates leading compression solutions for a sustainable energy future and the long-term success of its customers The Group is the only global manufacturer that covers a full range of reciprocating compressor technologies and services Since 1844, its passionate, customer-oriented and solution-driven workforce has set the benchmark in the gas compression industry,

About MIPS MIPS is a leader in high-performance RISC-V CPU IP, enabling innovation across automotive, AI, data center, and embedded markets Our engineering teams are building the next generation of compute solutions, and we are looking for passionate talent to join us in shaping the future of semiconductors, Position Overview We are seeking an experienced Lead DFT Engineer to drive the architecture, implementation, and validation of Design for Test (DFT) solutions across complex SoCs This role requires deep technical expertise in DFT flows, strong leadership skills, and proven ability to deliver high-quality, low-cost, and low-power test strategies for production silicon, Key Responsibilities Define and deploy DFT architecture for SoCs, including scan, ATPG, memory BIST, boundary scan, and analog test solutions, Lead project-level DFT execution: schedule planning, task assignment, milestone tracking, and status reporting, Drive pre-silicon verification of DFT IPs, including RTL generation, simulation, scan insertion, ATPG bring-up, and coverage analysis, Collaborate with EDA vendors to optimize simulation and verification flows for DFT, Partner with Test and Product Engineering teams for silicon bring-up, debug, and production test optimization, Support STA constraints development and AMS verification for analog IP trims and characterization, Mentor and ramp up junior engineers through training and technical guidance, Contribute to automation, innovation, and continuous improvement of DFT methodologies, Qualifications Tech Tech 7+ years of hands-on DFT experience, including SoC-level ownership, Strong expertise in ATPG, scan insertion, memory BIST, STA, and analog, AMS test flows, Proven track record of silicon bring-up and post-silicon debug, Experience with DFT tools such as Cadence Genus, Modus, Xcelium, JasperGold, or similar, Proficiency in SystemVerilog, VHDL and scripting languages (Python, Perl, Tcl, C), Strong problem-solving skills, analytical mindset, and ability to lead cross-functional initiatives, Preferred Skills Prior experience driving low-power and cost-sensitive DFT architectures, Contributions to patents, publications, or conference presentations in DFT, test, Ability to work in a fast-paced environment with global teams, Strong communication and leadership skills with a hands-on approach, Why Join MIPS Be part of a team driving innovation in RISC-V CPU IP and SoC development, Work on cutting-edge semiconductor designs with global impact, Collaborative, growth-focused environment with opportunities for innovation and leadership,

As an Engineer (DFT) at eInfochips located in Bangalore, India, you will be responsible for hands-on experience in various DFT aspects including Scan insertion, MBIST and JTAG, ATPG, and Pattern validation at both block level and Fullchip level. You will be proficient in the usage of Synopsys tools such as DFT MAX and TetraMAX, as well as Cadence tools like RTL Compiler, Encounter Test, modus, and Janus. Additionally, experience with Mentor Graphics tools like Tessent tool chain, TestKompress, Debussy, VCS/Questa/IUS, and PT tool from Synopsys will be advantageous. This is a full-time position falling under the category of Engineering Services.,

ROLE & RESPONSIBILITIES: Incumbent will be responsible for Scan insertion and validation, BIST, MBIST insertion and validation, ATPG, IP Tests and Pattern validation w/wo Timing, DFT mode timing Analysis and sign off. Be responsible for a comprehensive DFT plan. Incumbent to work with DFT and cross functional teams. To architect and implement solutions for Scan and built-in self-test (Memory and Logic BIST) circuitry to test devices in the field. ESSENTIAL SKILLS & EXPERIENCE: Strong fundamentals on DFT and ASIC cycle. Sound expertise in Tcl, Perl, Shell scripting. Technically sound & good team player. Hands-on experience with DFT implementation using standard EDA and flow is a must. Experience on latest technology (28nm,16nm,7 nm) EDUCATION BACKGROUND: B.E./ B.S./ B.Tech/ M.S./ M.Tech in VLSI/Electronics/Electrical/Computer/Instrumentation Engineering.

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills. Mandatory Key Skills VHDL,RTL coding,Mentor DfT tools,Cadence tools,scan insertion,JTAG,ATPG,DRC,coverage analysis,simulation debug,timing,SDF,LBIST,Mixed Signal Radar IC,proactive,collaborative,detail-oriented,independent judgment,debug,root cause analysis,Verilog*

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills. Mandatory Key Skills JTAG,ATPG DRC,LBIST,RTL coding,VHDL,DFT

We are looking for a skilled DFT Engineer with 3 to 7 years of experience to join our team in the IT Services & Consulting industry. The ideal candidate will have a strong background in designing and implementing fault detection and testing strategies. Roles and Responsibility Design and develop test plans, test cases, and test scripts for complex systems. Collaborate with cross-functional teams to identify and prioritize testing requirements. Develop and maintain automated testing frameworks and tools. Analyze test results, identify defects, and work with development teams to resolve issues. Participate in agile development methodologies and contribute to process improvements. Stay up-to-date with industry trends and emerging technologies in DFT engineering. Job Requirements Strong understanding of digital logic design principles and microelectronic circuits. Experience with programming languages such as C++, Python, or Java. Familiarity with testing frameworks like JUnit, PyUnit, or Selenium. Knowledge of version control systems like Git. Excellent problem-solving skills and attention to detail. Ability to work effectively in a team environment and communicate technical ideas clearly.