223 Scan Insertion Jobs

Senior DFT Engineers Roles And Responsibilities 10 yrs+ Experience in complex SOC level DFT execution in advanced finFET technology. Strong DFT fundamental knowledge from defect models to ATPG algorithm. Deep knowledge with EDA tools such as Synopsys Tetramax or Mentor Tessent. Knowledge of basic SoC architecture and HDL languages like Verilog to be able to work with logic design teams for timing fixes Required Technical And Professional Expertise: Excellent communication and interpersonal skills. Strong and effective presentation skills, able to operate at multiple levels including senior management. Self-motivated. Take ownership of problems. Creative problem solving

Position Summary: DFT (Design-For-Testability) Engineer Experience: 1015 Years Location: Bangalore About the Role: We are seeking an experienced DFT Engineer to join our ASIC/SoC design team. You will be responsible for developing DFT architectures, integrating test logic, enabling high fault coverage, and supporting silicon bring-up to ensure robust manufacturability and yield. Key Responsibilities: Develop and implement DFT strategies: scan insertion, ATPG, BIST, boundary scan, JTAG. Work closely with RTL, verification, physical design, and layout teams to integrate test features with minimal area/performance impact. Build test plans, test infrastructures, and test patterns; perform automa...

DFT architecture, ATPG, MBIST, BIST, Memory Test, RTL, DFT rule check, gate level simulations, Scan Insertion, Scan Chain, Test Coverage Analysis,STA Contact- gagan@bestnanotech.in

Mirafra Technologies hiring DFT_Engineers for Multiple Projects: Experience - 4+ year onwards Notice period - 0 to 30 days Location - Bangalore Job Description: We are seeking a DFT CAD and Automation Engineer to develop, maintain, and enhance automation infrastructure and CAD tools supporting the Design-for-Test (DFT) flow. The engineer will collaborate with DFT, design, and CAD teams to streamline test insertion, pattern generation, verification, and signoff across complex ASIC RF and connectivity projects. Develop and maintain automation scripts, tools, and workflows to support DFT insertion, ATPG, MBIST, and test coverage analysis Integrate and support commercial EDA tools (Synopsys and ...

Role Purpose The purpose of the role is to create and engineer exceptional product architectural design for existing and new products and enable delivery teams to provide exceptional client engagement and satisfaction. 6 + Yrs Experience in MBIST , scan insertion, DRC analysis and DRC resolving , ATPG and simulations for Asics. Test coverage improvement and Hierarchial test knowledge Good debugging skills Hands-on experience with Synopsys tools - TestMax Manager/ TestMax Atpg/ TestMax Advisor/VCS knowledge on PD/Timing collaterals. Do Define product requirements and design needs by displaying complete understanding of product vision and business requirements Develop architectural designs for...

Eximietas Design is expanding its team and we are currently looking for DFT Engineers to join us at our Bangalore and Ahmedabad locations. If you have 5+ years of experience in DFT (ASIC/SoC) , this could be a great opportunity for you. Role: DFT Engineer Experience: 5+ years Locations: Bangalore / Ahmedabad Key Responsibilities: Develop and implement DFT architecture and methodologies for ASIC/SoC designs Scan insertion, ATPG, scan stitching, MBIST/Logic BIST implementation Boundary scan (IEEE 1149.1), JTAG implementation & validation Test pattern creation & validation (stuck-at, transition, path delay faults) Collaborate with RTL, synthesis, and physical design teams to ensure DFT complian...

Looking experienced DFT Engg to join our ASIC/SoC design team. You'll be responsible for developing DFT architectures, integrating test logic, enabling high fault coverage, and supporting silicon bring-up to ensure robust manufacturability and yield. Required Candidate profile 5+ yrs exp IN DFT/ASIC/SoC test design & infrastructure roles. Aware of digital design, RTL, and SoC design flows. Hands-on exp with DFT tools. Verilog/SystemVerilog and scripting (Python/Perl/TCL).

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. The below client is a semiconductor and product engineering services company that provides silicon, system, and software design services, including digital and analog design and project management Position: DFT Lead - P-MBIST Location: Remote Job Type: Full time Job Description: A senior DFT specialist who can take full ownership of PMBIST planning, insertion, verification, and closure. Someone whos comfortable running end-to-end DFT flows, debugging patterns, and driving coverage targets with minimal supervision. Key Skills required: PMBIST architecture, integration, and ver...

Responsibilities: * Ensure compliance with industry standards and customer requirements. * Develop DFT designs using ATPG, MBIST, scan insertion, JTAG, BIST techniques.

Responsibilities: Willbe responsible forDesigning and Implementing DFT techniques. Shouldhavaa good understanding of Memory BIST/Scan /OnChipCompression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/LogicBIST oncomplex SOCs to improve testability. Test Modes implementation and verification, scan insertion including on-chip compression. Implementing,integratingand verifying memory BIST and boundary scan. ATPG Test vector (Stuck-at/At-speed/Path delay/SDD/IDDQ/Bridging fault) generation with hightest Coverageand simulations at gate level with timing (SDF). Basic understanding of complete SOC design and flow. Cross functionalteamsinteraction for issue resolution. Participa...

NextSilicon is reimagining high-performance computing by leveraging intelligent adaptive algorithms to vastly accelerate supercomputers and drive them into a new generation. The new software-defined hardware architecture enables high-performance computing to fulfill its promise of breakthroughs in advanced research fields. NextSilicon's core values include: - Professionalism: Striving for exceptional results through professionalism and unwavering dedication to quality and performance. - Unity: Fostering a collaborative work environment where every employee feels valued and heard. - Impact: Passionate about developing technologies that make a meaningful impact on industries, communities, and ...

As a DFT Engineer in Bangalore, India with 6+ years of experience, your role will involve the following responsibilities: - In-depth knowledge and hands-on experience in scan insertion, ATPG, coverage analysis, and Transition delay test coverage analysis - Analyzing design and proposing the best compression technique - Debugging and resolving DRC issues - Working with the front-end team to provide solutions and ensure DFT DRCs are fixed - Generating high-quality manufacturing ATPG test patterns for SAF (stuck-at fault), transition fault (TDF), and Path Delay fault (PDF) models through the use of on-chip test compression techniques - Experience in Synopsis TetraMax/DFTMax and Cadence Encounte...

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. To...

Key Skills: DFT, DFT Design, Scan Insertion, ATPG, MBIST Roles and Responsibilities: Develop and implement DFT strategies including scan compression and insertion, Memory BIST, and Logic BIST. Conduct at-speed testing and fault simulation to ensure product quality. Perform back-annotated gate-level verification and silicon debug. Utilize Verilog RTL, TCL, and/or Perl for coding tasks. Work proficiently in Unix/Linux environments. Collaborate with cross-functional teams to integrate DFT solutions into designs. Stay updated with industry standards such as IEEE 1149, 1500, 1687, and 1838. Engage in continuous learning and application of new DFT methodologies and tools. Skills Required: Strong e...

• In Depth of DFT concepts including Analog IP block testing. • EXP in DFT Insertion, includes SCAN, MBIST, BSCAN, IJTAG. • Well versed with RTL level or Netlist level Insertion (Block level/Top level). • ATPG Coverage Analysis & improvement. Required Candidate profile • Strong fundamentals in DFT • Exp in SCAN, MBIST, BSCAN, IP test modes & Post silicon support. • Equivalence check & RTL lint tool (spyglass). • Exp with ATE Pattern Development & ATE support

Mirafra Technologies hiring DFT_Engineers for Multiple Projects: Experience - 4+ year onwards Notice period - 0 to 30 days Location - Bangalore Apply at sayantikamajumdar@mirafra.com Call / Whatsapp: +91 - 9007115796 JD 1: 1. MBIST , scan insertion, DRC analysis and DRC resolving , ATPG and simulations for Asics. 2. Test coverage improvement and Hierarchial test knowledge 3. Good debugging skills 4. Hands-on experience with Synopsys tools - TestMax Manager/ TestMax Atpg/ TestMax Advisor/VCS 5. knowledge on PD/Timing collaterals. JD 2: Worked on ATPG , GLS (No Timing & Timings). exp in Python based Script for ATPG , GLS & Post Si Diagnosis flows. JD 3: DFT Tools flow: Mentor Tessent Implement...

Skillset: Strong background in DFT and DV Hands-on experience with AMD projects Good understanding of scan insertion, ATPG, and verification methodologies Self-motivated to work effectively & should be able to handle work independently. B.E/BTech in ECE, EE or M.E/MTech/MS in Microelectronics, VLSI Design, Integrated Circuits and Systems Engineering, System Level Integration & SoC Good understanding of analog circuits and ability to write behavioral models using Verilog

We are hiring an experienced DFT Engineer with strong hands-on expertise in Mentor Tessent, scan insertion, MBIST, DFT RTL implementation, and SoC-level DFT methodologies. Key Responsibilities: DFT implementation using Mentor Tessent Tools RTL-level DFT implementation and integration LEC (RTL pre-DFT vs post-DFT & Gate-level LEC) Experience in SoC-level and Block/Sub-system level DFT Insertion experience: Scan, MBIST, OCC, EDT (ARM DFT flow) Pattern generation, retargeting & simulations (Block + SoC) Zero-delay + timing simulations with SDF DFT coverage closure ownership Scan synthesis & timing constraints creation SSN experience Mandatory

Role Overview: You will be part of the Silicon One development organization as an ASIC Implementation Technical Lead focusing on Design-for-Test. Your primary responsibility will involve collaborating with Front-end RTL teams and backend physical design teams to comprehend chip architecture and drive DFT requirements early in the design cycle. Additionally, you will participate in crafting innovative next-generation networking chips, leading the DFT and quality process through the entire Implementation flow and post silicon validation phases, with exposure to physical design signoff activities. Key Responsibilities: - Manage the definition, architecture, and design of high-performance ASICs ...

Job Summary: We are seeking a skilled DFT Engineer to join our semiconductor design team. The ideal candidate will have experience in implementing design-for-testability techniques to ensure high-quality and testable silicon designs. You will work closely with RTL designers, verification teams, and test engineers to develop and validate DFT strategies for complex SoC designs. Key Responsibilities: Develop and implement DFT architectures including scan insertion, ATPG (Automatic Test Pattern Generation), BIST (Built-In Self-Test), and boundary scan. Collaborate with RTL designers to integrate test logic efficiently without impacting design performance. Perform test coverage analysis and optim...

Were Hiring: Senior DFT Engineer Location: Bangalore, India Experience: 8+ Years Key Responsibilities: Define and implement IC-level DFT architecture Expertise in JTAG , scan insertion , compression , ATPG , and boundary scan Perform timing & no-timing simulations Implement Memory BIST (RAM & ROM) Collaborate effectively and work independently Requirements: Strong knowledge of DFT methodologies Excellent communication skills (written & verbal) Experience with Memory BIST repair flow (plus) Post-silicon debug experience (plus) Familiarity with Verilog/VHDL , Synthesis , STA , LEC (plus) Experience with Ultra Low Power Designs , Conformal Low Power (plus) Analog DFT experience (plus) Apply Now...

Job Title: DFT Practice Head Location: Bengaluru, India Experience: 12 to 16 years Position Overview The DFT Practice Head will lead the organization's Design for Test (DFT) competency, overseeing strategic direction, technology advancement, and team excellence. This leadership role will be responsible for building and strengthening DFT capabilities to support complex ASIC and SoC programs, ensuring quality, performance, and delivery excellence. Key Responsibilities Define and implement the overall DFT strategy, methodology, and best practices across projects and teams. Lead and mentor a team of DFT engineers, fostering a culture of technical excellence and continuous learning. Drive executi...

As an ASIC/SOC Front End Design Engineer, you will be responsible for setting up ASIC QA flows for RTL design quality checks. Your key responsibilities will include: - Understanding the design intricacies such as top-level interfaces, clock structure, reset structure, RAMs, CDC boundaries, and power domains. - Executing tasks like Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, and CLP steps. - Developing clock constraints, false paths, multi-cycle paths, IO delays, exceptions, and waivers. - Identifying and resolving flow errors, design errors, violations, and reviewing reports. - Debugging CDC, RDC issues, and implementing RTL fixes. - Collaborating with the DFX team for DFX c...

Scan architectures, JTAG(Joint Test Action Group), boundary scan, memory BIST (Built-In Self-Test), ATPG (Automatic Test Pattern Generation) and LBIST,Verilog/VHDL RTL,DRC (Design Rule Checking),Timing,Synopsys Contact- gagan@bestnanotech.in

DFT Lead- Bangalore- 10+ years experience Job Category: Electronic & Semiconductor Job Type: Full Time Job Location: Bangalore Salary: 50- 90LPA Years of Experience: 10+ years We are looking for an energetic, passionate and process oriented DFT Lead who has extensive experience in planning, implementation and verification of DFT features for multiple SoC. Direct Responsibilities of the role, but not limited to, working on various aspects of IP and SoC DFT including the DFT Architecture, Spyglass DFT, RTL implementation, Verification, Scan and ATPG. SCAN insertion, ATPG and pattern simulation/debug. MBIST and Repair implementation and verification TOP DFT architecture Design ATE vector setup ...