1092 Dft Jobs

Company: Eteros Technologies India Private Limited Eteros Technologies, Inc. is a Semiconductor Engineering services startup, head quartered in the heart of the Silicon Valley, San Jose, CA, USA. Eteros Technologies India Pvt Ltd is a wholly owned subsidiary offices in Bangalore, Noida, Hyderabad and Ahmedabad • Our world-wide customers are amongst The Who's who in the semiconductor industry. Eteros works not only with some of the top 20 semiconductor startups in the world but boasts of customers who are among the most respected publicly traded semiconductor companies. • Eteros engineers work on cutting edge technology nodes while working on the state-of-the art designs in the AI/ML, Datacenter, Automotive and 5G domains. Eteros engineers work with some of the brightest, innovative and successful engineers and leaders around the world. A one-of-a-kind opportunity where young Eteros engineers showcase their ability and experience world-wide from day 1 while learning from some of the world's most well-respected companies. • We are not your traditional design services company offering staff augmentation. Eteros engineers are treated as an integral part of the customer team and routinely are responsible for turnkey, end-to-end ownership and delivery, whether it is Implementation, Digital and Mixed Signal Verification, DFT or Analog Design and Layout. Eteros and our engineers work closely with our customers to define and set methodologies and design flows. • Eteros invests in our engineers. Our engineers are continuously learning, on and off the job. They are able to grow the breadth and depth of knowledge. We believe in preparing our employees for the fast-track in career development as well as longevity ----------------------------------------------------------------------------- Job Title/Role: Synthesis and Static Timing Analysis - Staff Design Engineer/Design Manager Location : Bangalore/Hyderabad/Ahmedabad/Noida Experience Level : 6+ Years Industry : Semiconductors Employment Type : Full-time Job Functions : Engineering ----------------------------------------------------------------------------- Summary Join a development team and lead the synthesis, static timing and DFT efforts for an advanced mixed signal chip for a high-profile Silicon Valley startup. In this highly visible role, as part of a highly talented team you will be at the heart of the Soc design effort interfacing with all disciplines with critical impact in getting functional products to of customers quickly. As a Sr, ASIC STA Engineer, you will be a part of the SOC digital design team responsible for providing integrated solutions into a growth industry Key Qualifications The position requires thorough knowledge of the ASIC design timing closure flow and methodology. • BTech/MTech/PhD with at least 6+ years hands-on experience in ASIC timing constraints generation and timing closure. • Expertise in STA tools (Tempus and Primetime) and methodologies for timing closure with a good understanding of OCV, noise and crosstalk effects on timing. • Familiarity with all aspects of timing closure of high-performance, mixed-signal SoCs in advanced finFET technology nodes, preferably 7nm. • Knowledge of timing corners/modes and process variations. • Knowledge of low-power techniques including clock gating, power gating and millivoltage designs. Proficient in scripting languages (Tcl and Perl). • ECO timing flow • Strong communication skills are a pre-requisite as the candidate will interface with a lot of different groups (e.g. digital design, verification, DFT, physical design, etc.). • Familiarity with RTL, synthesis, logic equivalence, DFT, floor-planning, and backend related methodology and tools. • Must be able to solve complex problems and independently drive tasks to completion in a timely manner. • Be able to work under limited supervision and take complete accountability. Responsibilities Include • Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation). • Develop and maintain methodology and flows related to timing verification and closure. • Generation of block and full chip timing constraints. • Analyze timing reports and utilize scripting techniques to develop insights and drive rapid Eteros Technologies, Inc. Confidential Sep 2020 timing closure. • Support digital chip integration work and flows What's in it for you • Work on leading edge technologies • An opportunity for career development and growth • Competitive compensation • Medical Benefits and more

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Be a member of the team that plays a significant role in ensuring the quality of Connectivity SoCs through structured DFT, Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST) techniques. Primary responsibilities will include, Interface with design team to ensure DFT design rules and coverages are met. Generating high quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models through the use of on-chip test compression techniques. MBIST verification (including repair), test pattern generation through Mentor tool. ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations. Work with the Product/Test engineering teams on the delivery of manufacturing test patterns for ATE. Responsible for supporting post silicon debug effort, issue resolution. Responsible for Diagnostic Tool generation for ATPG, MBIST and bring-up on ATE. Developing, enhancing and maintaining scripts as necessary Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 1-6 years’ experience in ASIC/DFT – simulation and Silicon validation Detailed knowledge on DFT concepts, pattern simulation, Silicon debug and yield enhancement In depth knowledge and hands-on experience in ATPG - coverage analysis. In depth knowledge of Memory verification, repair and failure root-cause analysis. Experience with any of these tools is required ATPG - TestKompress MBIST - Mentor ETVerify Simulation - VCS (preferred), modelsim. Expertise in scripting languages such as Perl, shell, etc. is an added advantage Ability to work in an international team, dynamic environment with good communication skills Ability to learn and adapt to new tools, methodologies. Ability to do multi-tasking & work on several high priority designs in parallel Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

At Adben Industries Pvt. Ltd. , we’re not just designing circuits — we’re powering the future of embedded innovation. With a global client base and a deep focus on high-performance, production-ready designs, we’re looking to expand our team with a skilled PCB Design Engineer who thrives on precision, complexity, and engineering excellence. What You’ll Be Doing: Circuit and schematic design for embedded systems, analog/digital blocks, power supplies, and mixed-signal modules Designing multilayer (6+ layers) PCBs using Altium Designer and KiCad Working with HDI , flex , and rigid-flex PCB designs Designing boards that integrate switching regulators (buck, boost, buck-boost) and ensuring proper thermal layout and filtering Working with high-speed digital interfaces like USB, Ethernet, SDIO, SPI, QSPI, DDR traces (optional) Performing impedance matching , differential pair routing , and length tuning where required Creating and managing component libraries , including schematic symbols and IPC-compliant footprints Implementing robust grounding strategies , return path management , and signal integrity principles Selecting components and validating power/clock budgets for embedded boards Supporting hardware bring-up , debugging using oscilloscopes, logic analyzers , and multimeters Collaborating with firmware, mechanical, and test engineers for end-to-end product delivery Generating and reviewing manufacturing deliverables: Gerber/ODB++, BOMs, Assembly drawings Must-Have Skills: 2+ years of hands-on experience in professional PCB design Strong proficiency in Altium Designer and KiCad Experience with HDI , flex , and 6+ layer stack-up-based PCB layouts Solid grasp of switching regulator layouts , filtering, and decoupling practices Confident in routing and debugging high-speed interfaces (USB, Ethernet, SDIO, SPI) Clear understanding of blind/buried vias , controlled impedance , and differential signaling Experience designing and reviewing schematics , and generating custom footprints Hands-on debugging with oscilloscopes , logic analyzers , and rework tools Strong understanding of signal integrity , EMI mitigation , and power integrity Bonus (Nice to Have): Experience building test jigs , or validating hardware in production setups Familiarity with DFM/DFT practices , fab/assembly drawing standards Knowledge of thermal design , power estimation , or compliance prep (CE/FCC/EMC) Job Types: Full-time, Permanent Pay: ₹30,000.00 - ₹60,000.00 per month Schedule: Day shift Monday to Friday Supplemental Pay: Overtime pay Application Question(s): What is your current CTC in Lacs per annum? What is your notice period? Have you designed PCBs with 6 or more layers? Do you have hands-on experience with HDI or Flex PCBs? How comfortable are you debugging hardware using lab equipment like oscilloscopes or logic analyzers? Which PCB manufacturer you have last worked with ? Work Location: In person Expected Start Date: 18/08/2025

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Knowledge in Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Good knowledge of Tcl/Perl Scripting Strong problem-solving skills and good communication skills. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3- 6yrs years of experience in Physical Design/Implementation Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Bachelor's/Master’s degree in Electrical/Electronic Engineering from reputed institution 2-10 years of experience in Physical Design/Implementation Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

At Allegion, we help keep the people you know and love safe and secure where they live, work and visit. With more than 30 brands, 12,000+ employees globally and products sold in 130 countries, we specialize in security around the doorway and beyond. Allegion India is the Engineering and Technology center in Bangalore. It plays a pivotal role in the development of Allegion solutions via its 600+ competent and committed talent pool. A typical Allegion product development effort requires our various engineering groups to work together, beginning with the product requirements (systems engineering), the mechanical and electronics systems (mechanical, hardware, and firmware engineering), the mobile and cloud integrations (software engineering), and finally the rigorous validation (system testing, reliability testing, and software testing) required before our product goes to the market and our customers. Highlights: • Allegion has been honoured with the prestigious Gallup Exceptional Workplace Award (GEWA) for two consecutive years 2024 & 25, which recognizes the most engaged workplaces across the globe. • Allegion has been honoured with two 2024 SEAL Business Sustainability Awards for environmental initiatives in one of our U.S. distribution center as well as one of our fire-rated glass manufacturing facilities. About the role Allegion India is looking for a highly motivated Lead Engineer - Mechanical, who will lead mechanical product and platform development to deliver innovative products to meet complex global business needs. What you’ll do • Act as a project delivery lead • Act as a technical lead for Mechanical team • Work closely with global engineering stakeholders to manage all the phases of the product development. • Create environment that builds Employee Engagement and fosters Employee Growth and Development • Set individual and team goals in Alignment with Organizational goal and monitor progress through regular performance feedback sessions with their organizations. • Ensures engineering solutions meet requirements for cost, time, and quality. • Acts as escalation point to resolve issues within the team and to help coordinate resolution of issues with cross functional teams. • Works with the organization to provide the tools and resources to enable team members to be successful in execution. • Drives collaboration across individuals, teams, and groups. • Break competency development deliverables down into key tasks and work them independently. • Proactively provide instruction to others on routine work and are accountable to peers to provide design feedback and accountable to junior team members to provide guidance on tasks and schedules. • Keep abreast of technology, materials and process development in related and aligned areas to our business. • Create subsystem strategies and requirements from reference architectures and product roadmaps • Own the subsystem’s success across its entire product lifecycle • Work with architects, global business, and engineering teams across the company to ensure platform and subsystem goals are met. • Make trade-offs as necessary to ensure the highest level of subsystem performance and quality when considering cost, manufacturability, and available technologies • Technically mentoring team members in systems competency and process related activities • Contribute to multiple projects, involving single components or subsystems. • Actively seek out opportunities to increase productivity by suggesting and driving improvements within the platform, technical practices, and delivery procedures What we are looking for • Experience in playing the role of Lead Engineer for a team – managing their day to day execution plans, technical mentoring, providing feedback, leading the overall team growth. • Project management experience and complete knowledge of Mechanical Product Development Lifecyle. • A role model in effective Communication, Collaboration, Networking, Candor, Emotional Resilience, Negotiation, working within a team environment and cross functionally • Ability to relate to others, demonstrated resourcefulness and flexibility, active participation in decision making process, ability to assess risk and act with a sense of urgency. • Self-directed and able to direct others. • Solid knowledge on electronic / electromechanical product development, and understands the interfaces between software / firmware / hardware / mechanical systems. • Experienced and proficient with 3D CAD software (preferably PROE/ CREO) • Good working knowledge of DFMEA, DVP&R, PPAP, GD&T, tolerance analysis, Engineering Calculations and other product development associated techniques and tools. • Good knowledge on different manufacturing processes • Experience with Finite Element Analysis (FEA) is a plus. • Specialization in Electromechanical Product Design – specifically motor actuation system, Sensor/Monitoring systems, ESD/ESI, miniaturization et., • Good working knowledge in Design for Reliability, Design of experiments. Nice to have: (At least one) Expert in Plastic, Certification Credentials on TRIZ, GD & T or DOE • Experience in Structured Root Cause Analysis techniques. • Quickly learn established engineering processes (like Product development process - preferable Windchill, ECN, BOM, RFQ, etc.), standards, methods and procedures needed to accomplish assigned tasks with discipline. • Knowledge of statistical quality methods like Six Sigma, TQM is a plus. Location Bangalore/ Hybrid Experience- 13-18 years of relevant experience Preferred Skills - Mechanical Product Design & Development - Mechanical Design tools like CREO, SOLIDWORKS - DFM, DFA, DFT Techniques - Tooling & Manufacturing Knowledge - PLM Tools like Windchill - Engineering Change Management processes Education B.Tech / M.Tech in Mechanical Engineering What we offer Allegion is a Great Place to Grow your Career if: You are seeking a rewarding opportunity that allows you to truly help others. With thousands of employees and customers around the world, there’s plenty of room to make an impact. As our values state, “this is your business, run with it”. • You value personal well-being and balance because we do too! • You’re looking for a company that will invest in your professional development. As we grow, we want you to grow with us. Work Culture Allegion is committed to building and maintaining a diverse and inclusive workplace. Together, we embrace all differences and similarities among colleagues, as well as the differences and similarities within the relationships that we foster with customers, suppliers, and the communities where we live and work. Whatever your background, experience, religion, age, gender, gender identity, disability status, sexual orientation, or any other characteristic protected by law, we will make sure that you have every opportunity to impress us in your application and the opportunity to give your best at work, not because we’re required to, but because it’s the right thing to do.

The DFX Verification Lead position is located in Bangalore and requires 4 to 8 years of experience. The ideal candidate should have a strong understanding of DFT requirements such as Scan, BIST, and JTAG Debuggers. In this role, you will collaborate with IP and integration teams to ensure the successful implementation and verification of design elements. Your responsibilities will include working closely with designers and verification engineers to guarantee functionality and design features for future projects. To excel in this role, you must have a deep knowledge of verification flows and be proficient in debugging at both SoC and system levels. Additionally, expertise in Verilog, System Verilog, or System C for test-bench/model development is required. If you are passionate about chip design and semiconductor projects, we invite you to apply for this exciting opportunity. To express your interest, please submit your resume to krishnaprasath.s@acldgitial.com.,

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Join SanDisk India as a Technical ASIC Project Leader and take charge of developing cutting-edge ASICs that power the next generation of SD cards for imaging, gaming, mobile, and data storage. This is a high-impact leadership role where your technical expertise and strategic vision will drive projects from concept to mass production. Key Responsibilities Lead Full-Cycle SoC Development: Own the end-to-end development of high-performance ASIC controllers, from architecture definition to production ramp-up. Translate Product Vision into Technical Execution: Collaborate with product, firmware, and system teams to define ASIC requirements aligned with SanDisk’s storage solutions. Drive Cross-Functional Collaboration: Partner with SoC Design, Verification, Validation, DFT, Physical Design, Mixed-Signal IP, Foundry, Hardware, Firmware, and Test Engineering teams to deliver industry-leading SoC solutions. Ensure Technical Excellence: Conduct in-depth technical reviews, identify risks early, and implement mitigation strategies to ensure project success. Mentor and Inspire: Provide technical leadership and mentorship to engineering teams, fostering a culture of innovation, accountability, and continuous improvement. Communicate with Impact: Deliver clear, concise, and transparent project updates to stakeholders, ensuring alignment and enthusiasm across all levels. Qualifications Master’s degree in electrical engineering, Computer Engineering, or a related field. Proven experience leading complex ASIC or SoC development projects. Strong technical background in digital design, verification, and silicon validation with understanding of the SD, UHS and SD-Express standards. Excellent cross-functional leadership and communication skills. Ability to manage technical risks and drive execution in a fast-paced environment. Passion for innovation and delivering high-quality, scalable solutions. Preferred Qualifications Proficiency with EDA tools and methodologies for ASIC development. Familiarity with industry standards and best practices in semiconductor design. Expertise in low-power design techniques and high-speed interfaces. Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

Department: Quality Control / Coatings Reports To: QA/QC Manager / Project Manager Location: Chhattisgarh, Rajasthan, UP Employment Type: Full-time --- Job Purpose: To ensure that all painting and coating activities on site meet project specifications, industry standards, and client requirements. The Painting Inspector Engineer will monitor surface preparation, coating application, and finishing processes to ensure the highest level of corrosion protection and aesthetic standards. Key Responsibilities: Review project specifications, coating procedures, material data sheets, and method statements. Inspect surface preparation, including blasting and cleaning, to ensure compliance with standards (e.g., SSPC, NACE, ISO). Monitor application of paints and coatings (e.g., epoxy, polyurethane, zinc-rich, etc.) in accordance with approved procedures. Verify correct environmental conditions (humidity, temperature, dew point) before and during application. Check dry film thickness (DFT), wet film thickness (WFT), adhesion, and holiday/pinhole testing using calibrated equipment. Maintain inspection records, daily reports, and photographic evidence. Coordinate with client representatives, third-party inspectors, and project teams. Conduct final walkthroughs and prepare punch lists for coating defects. Ensure proper storage and mixing of paints and consumables. Provide guidance to applicators and supervisors for rectification and best practices. Participate in root cause analysis for coating failures or non-conformities. Ensure compliance with safety, environmental, and health regulations. Qualifications: Bachelor’s Degree / Diploma in Mechanical, Civil, Chemical, or related Engineering field. NACE Level I, II, or III / SSPC / BGAS certification (preferred or required depending on role level). Minimum 3–5 years of experience in painting/coating inspection (varies with position seniority). Knowledge of international standards (ISO 12944, SSPC, ASTM, NORSOK, etc.). Familiarity with coating systems for steel structures, pipelines, tanks, offshore, or marine assets. Skills and Competencies: Strong knowledge of surface preparation and coating systems. Proficient in inspection tools and documentation. Ability to read and interpret drawings, standards, and specifications. Good communication and reporting skills. Attention to detail and quality-oriented. Knowledge of HSE practices related to coating and paint handling. Work Conditions: On-site/offshore or workshop environment (depending on project). May involve working in confined spaces or at heights. Use of personal protective equipment (PPE) required. Shift or extended hours may be needed depending on project demands.

As a Design Manager at Texas Instruments, you will have the opportunity to lead a team of RTL front end, Digital Back end & Design verification engineers. Your primary responsibilities will include directing and guiding the activities of a research or technical design function, overseeing the design, development, modification, and evaluation of digital electronic parts, components, or integrated circuitry for electronic equipment and hardware systems. You will evaluate the final results of research and development projects to ensure the accomplishment of technical objectives. Additionally, you will be involved in preparing and presenting reports outlining the outcomes of technical projects and making recommendations for actions necessary to achieve desired results. In this role, you will play a key part in selecting, developing, and evaluating personnel to ensure the efficient operation of the function. Joining Texas Instruments as a Design Manager (RTL, P&R, Design Verification) will allow you to work with a team of enthusiastic engineers focused on developing highly complex and industry-leading devices for audio applications. You will be involved in developing new Audio converters catering to PE, Automotive, and Industrial market segments, with the digital content including a DSP for digital filters and audio signal processing blocks among various other IPs. Collaboration with various engineering teams within the product line, including analog design, layout, firmware, verification, validation, test, systems, applications, and marketing, will be a part of your role to successfully execute new products from concept to volume production and subsequent support. As a core member of the design team, you will drive flawless execution by finding innovative design architecture and solutions through out-of-the-box thinking to deliver highly differentiated products. This is an exceptional opportunity to be part of a team that is continuously seeking growth opportunities, working with leading customers globally, and developing cutting-edge solutions in consumer electronics, industrial, and automotive markets. To qualify for this position, you must hold a minimum bachelor's degree in electrical engineering and have at least 7 years of experience. Strong aptitude, hands-on experience in RTL frontend design, excellent command of RTL design concepts, and the ability to work with dynamically evolving requirements are some of the key qualifications needed for this role. You should also possess a result-driven attitude, the ability to mentor team members, and familiarity with digital backend flow and design verification flow. Preferred qualifications for this role include establishing strong relationships with key stakeholders, strong verbal and written communication skills, hands-on experience with Digital Back end tools, and the ability to quickly ramp up on new systems and processes. Demonstrated interpersonal, analytical, and problem-solving skills, ability to collaborate effectively with cross-functional teams, and strong time management skills are also desirable qualities for this position. As a Design Manager at Texas Instruments, you will be responsible for leading a team of 7+ engineers and multiple contractors, driving results while striving for excellence in the complete Digital (Front and Backend) & Design verification team. Your role will also involve overseeing the career growth of your team members. If you are passionate about engineering and shaping the future of electronics, Texas Instruments offers a collaborative environment where employees are empowered to own their career and development. Join us to work with some of the smartest people in the industry and contribute to creating a better world through affordable semiconductor technology. Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company dedicated to designing, manufacturing, and selling analog and embedded processing chips for various markets. Our core passion is to make electronics more affordable through innovative semiconductor solutions. We value diversity and inclusion in our work environment and strive to empower our employees to drive innovation forward. At Texas Instruments, we believe in creating a diverse, inclusive work environment and are an equal opportunity employer. If you are interested in this position, please apply to this requisition.,

At Cadence, we are constantly seeking talented and motivated individuals to join our team and contribute to the ever-evolving world of technology. As part of the Modus R&D team at Cadence Design Systems, we are currently looking for an engineer who is passionate about validating and supporting Design-for-test (DFT) technologies. The ideal candidate should have a minimum of 2 years of experience in DFT/ATPG/ASIC Design flows, along with a solid understanding of RTL Verilog/VHDL coding styles and Synthesis. In this role, you will be responsible for working on complex problems that require innovative thinking and collaborating with various teams to propose out-of-box solutions focusing on robustness, PPA, and scalability. Excellent communication skills, both written and oral, are essential as you will be required to interface with Product Engineers (PEs) and R&D, with occasional direct customer support responsibilities. Key Responsibilities: - Validate and support DFT technologies such as 1500 Wrapper, Compression, RTL DFT, Low Pin Count Test, Hierarchical Test, LBIST, etc., using Cadence Synthesis tool Genus and ATPG using Cadence Test tool Modus on both in-house and customer designs. - Develop testplans for verifying new features, create and execute test cases, and report bugs/enhancements in tools. - Collaborate with R&D and Product Engineering teams to review feature specifications, testplans, and customer issues. - Debug customer-reported issues and propose/implement solutions to address them effectively. Requirements: - B.E/B.Tech with 2+ years or M.E/MTech in Electronics/Electrical engineering. - Proficiency in Digital electronics and Verilog. - Strong understanding of DFT techniques and methodologies. - Familiarity with Test standards like 1149.1, 1500, 1687 is a plus. - Experience with Cadence Test or other Test tools is preferred. Join us in our mission to tackle challenges that others can't. Your contributions will make a difference in shaping the future of technology.,

You should have experience in designing and implementing test methodologies for large, complex SoCs. You must be capable of resolving scan issues in complex multi-clock domain designs, developing DFT strategies for complex System-On-Chip designs, and generating & integrating Memory BIST, JTAG, SCAN/ATPG. You should be an expert in analyzing fault coverage, delay fault, and enhancements. Experience in developing and running scan insertion scripts, performing ATPG simulation & analyzing results is required. Expertise in Mentor / Synopsys DFT tools and debug skills in a Verilog design environment is essential. Experience with static timing analysis (STA) & formal verification is desirable. Proficiency in common UNIX scripting languages (perl, tcl, csh, sh) is a must. Kindly email your resume to careers@perfectus.com with Job Code DFT in the subject line.,

As a Senior Design/Verification - Subsystems Lead at Synopsys, you will be part of the Digital IP Subsystem team that has experienced significant growth. We are seeking talented engineers to join us in Bangalore/Hyderabad, India and be a part of our exciting journey in the SysMoore era. **Design Lead:** In the role of an RTL Design lead, you will experience the thrill of achieving bug-free RTL from requirements or specifications. Your expertise in driving the design effort for complex IP/Subsystem/SoC blocks, with a track record of multiple tape-outs, will be invaluable in delivering high-quality results. **Verification Lead:** As a Verification lead, you will enjoy the challenge of identifying and rectifying bugs to ensure the design intent is realized. Your role is critical in ensuring the flawless operation of chips, such as those on space telescopes capturing stunning images of galaxies. Your experience in leading multiple tape-outs and closing verifications of complex IP/Subsystem/SoC blocks will be instrumental in our success. **Design role:** In the position of a Senior RTL Subsystems Designer Lead with over 8 years of experience, you will be responsible for driving the Subsystem life cycle from requirements to final release phases. This includes crafting functional specifications, defining micro-architectures, coding RTL using best practices, conducting RTL quality checks, collaborating with Verification and implementation teams, and overseeing project completion. Proficiency in standard protocols like PCIe, DDR, UFS, USB, AMBA, as well as hands-on experience in low power design and understanding of DFT requirements and architecture are essential. Your ability to work effectively with cross-functional teams will be crucial in delivering successful projects. **Verification role:** In the role of a Senior Verification lead with over 8 years of experience, you will lead the complete Verification cycle by crafting test plans, architecting verification environments, developing test infrastructure, and executing plans to closure with coverage. Proficiency in Functional Verification of standard protocols like PCIe, DDR, UFS, USB, AMBA, as well as power-aware Verification with UPF, is required. Hands-on experience in Gate Level Verification is a valuable addition. Your collaboration with cross-functional teams will be key to driving projects to completion.,

The ideal candidate for this role will be an RTL engineer with over 8 years of practical design and verification experience using SystemVerilog UVM and ASIC verification. You should have hands-on experience with Synopsys and/or Cadence simulation tools, as well as proficiency in RTL and possibly Gate level debug. Desirable skills for this position include experience with Synopsys and/or Cadence Synthesis, STA, DFT, Formal Equivalence tools, and familiarity with JIRA. It would be beneficial to have knowledge of scripting languages such as Python or equivalent, understanding of PLLs, and experience with mixed-signal design modelling and debugging. Keywords: UVM, RTL, SystemVerilog, Synthesis, Analog.,

Eridu AI India Private Limited, a wholly owned subsidiary of Eridu Corporation, Saratoga, California, USA, is seeking highly motivated and talented professionals for its R&D center in Bengaluru. Eridu AI is a Silicon Valley hardware startup focused on accelerating training and inference performance for large AI models. The company introduces innovative solutions across semiconductors, software, and systems to enhance AI data center performance, increase GPU utilization, and reduce capex and power consumption. Led by a team of experienced Silicon Valley executives and engineers, Eridu AI's solution has been widely recognized by hyperscalers. We are currently looking for an RTL Design Director to lead our Networking IC team in Bengaluru. As a part of the Design Group, you will play a crucial role in defining, specifying, architecting, executing, and productizing cutting-edge Networking devices. This position offers a unique opportunity to shape the future of AI Networking and work on real-world problems. Responsibilities: - Lead the offshore RTL team and provide technical guidance. - Collaborate with Chip and System Architects to translate architecture requirements into microarchitecture and design implementation. - Conduct RTL coding, code reviews, and debugging. - Document microarchitecture and RTL subsystems. - Define development flows to enhance efficiency and quality. - Coordinate with other teams for successful RTL implementation. - Utilize domain experience in Ethernet, PCIe, and protocols for informed design decisions. Qualifications: - MS/BS degree with a minimum of 15+ years of experience. - Demonstrated success in tape-outs and productization, preferably in networking devices. - Ability to translate architecture-level descriptions into implementable designs with clear documentation. - Proficiency in addressing clock/reset/power domain challenges and safe design practices. - Experience in optimizing hardware for product performance. - Strong knowledge of industry tools and best practices for RTL development. - Understanding of networking protocols and ASIC design flow. - Familiarity with DFT and physical implementation requirements. Join us at Eridu AI to be a part of a world-class team working on groundbreaking technology that shapes the future of AI infrastructure. Your work will directly contribute to transforming data center capabilities and developing next-generation AI networking solutions. The starting base salary will be determined based on relevant skills, experience, qualifications, and market trends. For more information, visit our website at eridu.ai.,

About Newton School Come be part of a rocket ship that’s creating a massive impact in the world of education! On one side you have over a million college graduates every year with barely 5% employability rates and on the other side, there are thousands of companies struggling to find talent. Newton School aims to bridge this massive gap through its personalized learning platform. We are building an online university and solving the deep problem of the employability of graduates. We have a strong core team consisting of alumni from IITs and IIM, having several years of industry experience in companies like Unacademy, Inmobi, Ola, and Microsoft - among others. On this mission, we are backed by some of the most respected investors around the world, - RTP Global, Nexus Venture Partners, and a slew of angel investors including CRED’s Kunal Shah, Flipkart’s Kalyan Krishnamoorthy, Unacademy and Razorpay founders, Udaan’s Sujeet Kumar among others. About the Role: We are looking for VLSI engineers with a strong foundation in digital systems and computer architecture to take on an academic teaching role. This full-time position is ideal for engineers with hands-on experience in RTL design, processor components, or SoC architecture who are excited to teach how computers are built—from logic gates to microarchitectures. You will lead classroom instruction, mentor student projects, and help shape curriculum at the intersection of digital logic, hardware systems, and architectural design. Key Responsibilities Teach Computer Architecture by drawing from real-world VLSI design experience covering instruction sets, pipelining, memory systems, and microprocessor implementation. Guide students through lab simulations and RTL projects that explore how architectural concepts are implemented in hardware (e.g., datapaths, control units, cache design). Design and evaluate lab work, assessments, and hands-on student projects that simulate industry applications. Mentor and support students in their academic and professional development journeys. Continuously update course content to reflect current industry trends and technologies. Contribute to curriculum development, academic research, and internal learning initiatives. Host technical workshops, design challenges, and guest sessions to extend classroom learning. Collaborate with fellow faculty, industry mentors, and curriculum designers to enrich learning outcomes Must-Have Skills & Qualifications B.Tech / M.Tech / Ph.D. in Computer Engineering, Electronics, Electrical, or a related field. 4 - 7 years of experience working on processor subsystems, SoC integration, RTL for custom compute blocks, or related architecture-level VLSI work. Strong technical command over topics such as: ○ Computer Architecture: Instruction sets, microprocessors, memory hierarchy, pipelining, cache systems. ○ VLSI Design: CMOS circuits, RTL design, ASIC/FPGA flow, timing analysis, layout. Proficiency in tools such as Cadence, ModelSim, Synopsys, Xilinx, Mentor Graphics, etc. Working knowledge of HDL languages (Verilog/VHDL) and scripting (Tcl, Shell, Python). Excellent communication and classroom delivery skills. Demonstrated interest in teaching and mentoring students. Good-to-Have Skills: Prior experience as a faculty member or technical trainer. Familiarity with RISC-V, ARM-based processors, SoC Design, or low-power systems Exposure to DFT, verification methodologies, and EDA flows. Contributions to open-source, academic publications, or online technical content. Comfort with digital tools, LMS platforms, and collaborative teaching formats.

About Newton School Come be part of a rocket ship that’s creating a massive impact in the world of education! On one side you have over a million college graduates every year with barely 5% employability rates and on the other side, there are thousands of companies struggling to find talent. Newton School aims to bridge this massive gap through its personalized learning platform. We are building an online university and solving the deep problem of the employability of graduates.We have a strong core team consisting of alumni from IITs and IIM, having several years of industry experience in companies like Unacademy, Inmobi, Ola, and Microsoft - among others. On this mission, we are backed by some of the most respected investors around the world, - RTP Global, Nexus Venture Partners, and a slew of angel investors including CRED’s Kunal Shah, Flipkart’s Kalyan Krishnamoorthy, Unacademy and Razorpay founders, Udaan’s Sujeet Kumar among others. About the Role: We are looking for VLSI engineers with a strong foundation in digital systems and computer architecture to take on an academic teaching role. This full-time position is ideal for engineers with hands-on experience in RTL design, processor components, or SoC architecture who are excited to teach how computers are built from logic gates to microarchitectures. You will lead classroom instruction, mentor student projects, and help shape curriculum at the intersection of digital logic, hardware systems, and architectural design. Key Responsibilities Teach Computer Architecture by drawing from real-world VLSI design experience covering instruction sets, pipelining, memory systems, and microprocessor implementation. Guide students through lab simulations and RTL projects that explore how architectural concepts are implemented in hardware (e.g., datapaths, control units, cache design). Design and evaluate lab work, assessments, and hands-on student projects that simulate industry applications. Mentor and support students in their academic and professional development journeys. Continuously update course content to reflect current industry trends and technologies. Contribute to curriculum development, academic research, and internal learning initiatives. Host technical workshops, design challenges, and guest sessions to extend classroom learning. Collaborate with fellow faculty, industry mentors, and curriculum designers to enrich learning outcomes Must-Have Skills & Qualifications B.Tech / M.Tech / Ph.D. in Computer Engineering, Electronics, Electrical, or a related field. Experience working on processor subsystems, SoC integration, RTL for custom compute blocks, or related architecture-level VLSI work. Strong technical command over topics such as: ○ Computer Architecture: Instruction sets, microprocessors, memory hierarchy, pipelining, cache systems. ○ VLSI Design: CMOS circuits, RTL design, ASIC/FPGA flow, timing analysis, layout. Proficiency in tools such as Cadence, ModelSim, Synopsys, Xilinx, Mentor Graphics, etc. Working knowledge of HDL languages (Verilog/VHDL) and scripting (Tcl, Shell, Python). Excellent communication and classroom delivery skills. Demonstrated interest in teaching and mentoring students. Good-to-Have Skills: Prior experience as a faculty member or technical trainer. Familiarity with RISC-V, ARM-based processors, SoC Design, or low-power systems Exposure to DFT, verification methodologies, and EDA flows. Contributions to open-source, academic publications, or online technical content. Comfort with digital tools, LMS platforms, and collaborative teaching formats.

We are seeking skilled engineers to join our semiconductor verification and simulation team. This role focuses on functional, gate-level, DFT, and timing simulations, along with validating SoC and IP blocks. Ideal candidates will have hands-on experience with Synopsys EDA tools, and domain-level knowledge of IC packaging and analog layout design will be a strong plus. Roles & Responsibilities: Develop and execute RTL test benches using VCS/SystemVerilog/UVM Perform functional and gate-level simulation, debug with Verdi Run DFT pattern simulations, scan insertion validations Conduct Static Timing Analysis (STA) with PrimeTime Execute power-aware and multi-mode multi-corner (MMMC) simulations Validate interfaces considering IC package parasitic (SiP/2.5D/3D-IC understanding is a plus) Collaborate with teams to correlate package- and board-level effects with chip-level behavior Analyze analog layout impact on mixed-signal simulation accuracy (awareness of layout parasitic) Requirements Strong hands-on experience with Synopsys tools: VCS (RTL simulation), Verdi (debug), PrimeTime (timing), TetraMAX/TestMAX (DFT), HSPICE/FineSim (analog simulation exposure is a plus) Familiarity with IC packaging technologies, chip-package co-simulation, and signal/power integrity considerations Understanding of analog layout practices and their influence on simulation/verification Strong scripting skills (TCL, Perl, Python) for automation Excellent debugging, documentation, and communication skills Preferred Qualifications: Bacheloror Masterin Electronics, VLSI, or Electrical Engineering & 5-8 Years of Relevant Experience is mandatory Awareness of multi-die, chip let, or 3D IC architectures Basic understanding of EM/IR effects, package substrate modeling, or layout vs schematic (LVS) Strong analytical and collaborative mindset Master in VLSI / Microelectronics Benefits -Challenging job within a young and dynamic team. -Performance-driven, Career Progression Opportunities. -Attractive remuneration package: On par with Industry Standards. -Opportunity to join an organization experiencing year on year growth.

Note: Applicants must have Semiconductor Recruiting experience. Job Title: Semiconductor Recruiter Location: Remote Employment Type: Full-time Experience: 3-8 years (customizable based on requirement) About the Role: We are seeking a skilled and driven Semiconductor Recruiter to join our talent acquisition team. You will be responsible for identifying, engaging, and hiring top talent across a wide range of roles within the semiconductor industry—including design, verification, validation, and product engineering. This role demands a strong understanding of semiconductor skillsets, hiring cycles, and technical nuances. Key Responsibilities: Partner with hiring managers and business leaders to understand role requirements and define recruitment strategies. Source candidates through multiple channels including LinkedIn, Boolean search, networking events, job boards, and internal databases. Screen and assess candidate qualifications, both technical and behavioral. Manage the end-to-end recruitment lifecycle including sourcing, interview coordination, offer negotiation, and onboarding handover. Build and maintain a strong pipeline of passive and active semiconductor professionals. Stay updated on market trends, compensation benchmarks, and talent availability in the VLSI/semiconductor space. Drive diversity-focused hiring and ensure adherence to recruitment SLAs and compliance standards. Work closely with internal teams and external partners to scale hiring initiatives for R&D and product development groups. Key Requirements: 3–8 years of recruitment experience, with at least 2+ years in semiconductor or hardware/VLSI hiring . Strong understanding of roles such as Design Engineer, DV Engineer, DFT, RTL, PD, Validation, etc. Experience hiring for startups, product companies, or global semiconductor firms preferred. Excellent sourcing skills with hands-on expertise in LinkedIn Recruiter, Github, Boolean search, etc. Proven ability to manage high-volume hiring with quality and speed. Strong communication, stakeholder management, and negotiation skills. Ability to thrive in a fast-paced, dynamic, and tech-centric environment. Why Join Us: Work with cutting-edge semiconductor clients and tech innovators Opportunity to scale niche hiring programs from the ground up Flexible work environment with a high-performance culture Attractive compensation with performance-linked incentives Apply now if you're passionate about tech hiring and want to shape the future of semiconductor talent!

Minimum qualifications: Bachelor's or Master's degree or equivalent practical experience, 5 years of experience with Design for Testability/Design for Debugging (DFT/DFD) flows and methodologies, Experience in developing DFT specifications and DFT architecture, Experience in fault modeling, test standards and industry DFT/DFD/Automatic Test Pattern Generation (ATPG) tools with Application-Specific Integrated Circuit (ASIC) DFT, synthesis, simulation and verification flow, Preferred qualifications: Experience with DFT for a subsystem with multiple physical partitions, Experience with Internal JTAG (IJTAG) ICL, Procedural Description Language (PDL) terminology, ICL extraction, Instrument Connectivity Language (ICL) modeling with Siemens Tessent Tool, Experience with Spyglass-DFT, DFT Scan constraints and evaluating DFT Static Timing Analysis (STA) paths, Experience with coding language like Perl or Python, Knowledge of DFT techniques like SSN, HighBandwidth IJTAG, About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products You'll contribute to the innovation behind products loved by millions worldwide Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration Google's mission is to organize the world's information and make it universally accessible and useful Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful We aim to make people's lives better through technology, Responsibilities Work with Design for testing (DFT) engineers, Register-Transfer Level (RTL), Physical Designer Engineers, System on a chip (SoC) DFT and Product Engineering team, Work on Subsystem level DFT scan, Memory Built-In Self Test (MBIST) Architecture with multiple voltage, power domains, Write scripts to automate the DFT flow, Develop tests that can be used for Production in the Automatic Test Equipment (ATE) flow, Work with members of the DFT team to deliver two or more Subsystems in a SoC, Google is proud to be an equal opportunity workplace and is an affirmative action employer We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status We also consider qualified applicants regardless of criminal histories, consistent with legal requirements See also Google's EEO Policy and EEO is the Law If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form , Show

To set up and lead quality control inspectionsystems across all structural steel fabrication activities, ensuring all jobsmeet dimensional, visual, and specification standards, while supporting projectflow and on-time delivery through effective coordination, documentation, andcontinuous improvement. Key Responsibilities A. System Setup Shift Supervision Develop and implement QC inspection plans formachining, welding, painting, and final assembly stages Plan and supervise daily inspections fit-up,welding, paint DFT across shifts in line with QAP and ITP Guide and monitor QC Coordinators andTechnicians to maintain consistency and shift-wise accountability Maintain job-wise and project-wise inspectionreports, rejection logs, and repair records B. Inspection Execution Documentation Conduct dimensional and visual inspections usingvernier, micrometre, fillet gauges, templates, and DFT meters Ensure inspection readiness from production only accept jobs that are fully prepared, and avoid idle QC time Support NDT coordination (PT, UT, RT) inconsultation with the Welding Expert and QA Lead Issue NCRs for deviations with cleardescriptions and support timely closure with corrective actions Prepare inspection reports and organize clientfolders in compliance with project documentation norms C. Client, TPI InternalCoordination Lead walkthroughs during client and third-partyinspections ensure availability of records and inspection checkpoints Coordinate with Section In-Charges for jobofferings and manage sequence alignment with PPC Work closely with the Welding Expert to clarifyWPS-related checks and interpretation of weld acceptance standards D. Analysis, Escalation Improvement Track and report recurring quality issues orinspection bypass attempts; escalate to the Quality Head Use basic QC tools (Pareto, RCA, checklists,SPC) to identify trends and support QA in system updates Support the Quality Head in preparing for ISO,client, or regulatory audits through proper record maintenance Responsibilities Outsidethe Scope of This Role Does not define QA systems or standards, butenforces them through inspection. Does not control job release or execution order aligns with PPC and production plan. Does not approve material procurement or designissues escalates unclear points to QA or Detailing. Does not supervise operators, but canstop/reject work that fails acceptance criteria. Qualifications Experience Diploma / B.Tech in Mechanical / Welding /Fabrication 610 years of experience in QC roles withinstructural steel fabrication, EPC, or infrastructure projects Strong hands-on inspection experience: dimensional(vernier, micrometre), visual (weld, paint), DFT/NDT coordination Exposure to ISO 9001 systems, traceabilitystandards, and client inspection procedures Comfortable setting up QC systems in a greenfieldor startup context Preferred but notmandatory: CSWIP / AWS / NDT Level II and certifications Good Familiarity with basicquality tools : checklists, defect tracking sheets, rootcause identification (RCA), Pareto, Fish Bone Diagram, Design and ManufacturingFMEA, SPC, SQC, Gage RR, 8D Problem Solving, Six Sigma Green BeltCertification

To set up and lead quality control inspectionsystems across all structural steel fabrication activities, ensuring all jobsmeet dimensional, visual, and specification standards, while supporting projectflow and on-time delivery through effective coordination, documentation, andcontinuous improvement. Key Responsibilities A. System Setup ShiftSupervision Develop and implement QC inspection plans formachining, welding, painting, and final assembly stages Plan and supervise daily inspections fit-up,welding, paint DFT across shifts in line with QAP and ITP Guide and monitor QC Coordinators andTechnicians to maintain consistency and shift-wise accountability Maintain job-wise and project-wise inspectionreports, rejection logs, and repair records B. Inspection Execution Documentation Conduct dimensional and visual inspections usingvernier, micrometre, fillet gauges, templates, and DFT meters Ensure inspection readiness from production only accept jobs that are fully prepared, and avoid idle QC time Support NDT coordination (PT, UT, RT) inconsultation with the Welding Expert and QA Lead Issue NCRs for deviations with cleardescriptions and support timely closure with corrective actions Prepare inspection reports and organize clientfolders in compliance with project documentation norms C. Client, TPI InternalCoordination Lead walkthroughs during client and third-partyinspections ensure availability of records and inspection checkpoints Coordinate with Section In-Charges for jobofferings and manage sequence alignment with PPC Work closely with the Welding Expert to clarifyWPS-related checks and interpretation of weld acceptance standards D. Analysis, Escalation Improvement Track and report recurring quality issues orinspection bypass attempts; escalate to the Quality Head Use basic QC tools (Pareto, RCA, checklists,SPC) to identify trends and support QA in system updates Support the Quality Head in preparing for ISO,client, or regulatory audits through proper record maintenance Responsibilities Outside the Scope of This Role Does not define QA systems or standards, butenforces them through inspection. Does not control job release or execution order aligns with PPC and production plan. Does not approve material procurement or designissues escalates unclear points to QA or Detailing. Does not supervise operators, but canstop/reject work that fails acceptance criteria. Qualifications Experience Diploma / B.Tech in Mechanical / Welding /Fabrication 610 years of experience in QC roles withinstructural steel fabrication, EPC, or infrastructure projects Strong hands-on inspection experience: dimensional(vernier, micrometre), visual (weld, paint), DFT/NDT coordination Exposure to ISO 9001 systems, traceabilitystandards, and client inspection procedures Comfortable setting up QC systems in a greenfieldor startup context Preferred but notmandatory: CSWIP / AWS / NDT Level II and certifications Good Familiarity with basicquality tools : checklists, defect tracking sheets, rootcause identification (RCA), Pareto, Fish Bone Diagram, Design and ManufacturingFMEA, SPC, SQC, Gage RR, 8D Problem Solving, Six Sigma Green Belt Certification

Description The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and re-imagined user experience through Echo and Alexa We want you to help us build on the success of our first generation of ML accelerator at edge, Work hard Have fun Make history, We are seeking a seasoned and strategic Sr DFT Engineer to Lead end-to-end Design-for-Test (DFT) planning, execution, and silicon readiness for complex SoCs This role demands deep technical expertise, hands-on ownership, and proven leadership in taking chips from design to volume production, As a Senior DFT Engineer, you will be both the technical owner and hands-on driver of the DFT strategy and execution across complex, high-performance SoCs This role requires deep technical expertise, the ability to architect scalable and robust DFT solutions, and the discipline to personally engage in implementation and debug You will work alongside world-class design, validation, and test teams to ensure first-pass silicon success and scalable production test readiness Ideal for a seasoned leader, this role combines strategic ownership with direct execution, driving full lifecycle accountability from early DFT architecture planning to high-volume silicon bring-up and yield ramp, Lead development & implementation of DFT architecture including system level DFT for a full chip Write and guide others in writing design flow and project documentation, Own DFT planning, milestone tracking, and cross-functional checklist reviews, Oversee design, insertion, and verification of DFT logic and components into full SoC and subsystem RTL netlists, Review and sign-off SoC level DFT mode timing closure using static timing analysis Drive the sign-off on a generation of high-quality test and debug patterns for high coverage on silicon Keep informed on and introduce new technology into Design-for-Test process as appropriate, Education BASIC QUALIFICATIONS BS/BE or MS/ME in Electrical Engineering, Computer Engineering, or related field, Experience 15+ years in SoC/ASIC DFT, including 3+ years Leading DFT, Proven DFT experience leading multiple SoCs/ASICs (end-to-end) from architecture to high-volume production, DFT Architecture Expertise Proven capability in architecting and implementing DFT strategies at both subsystem and top-level, including: Scan architecture, compression, and ATPG implementation for high fault coverage and test quality, MBIST, BISR, and BIHR flows, including advanced shared-bus memory BIST integration, IEEE 1149 x (Boundary Scan), IEEE 1500, and IEEE 1687 (IJTAG) test architectures, DFT-Aware STA closure, including constraint generation and timing convergence strategies for shift and capture paths, RTL and gate-level debug, including mismatch triage and simulation correlation, Insertion and Validation of EFUSE & OTP controllers and related structures during DFT implementation, Tool Proficiency Deep hands-on experience with Tessent / Industry Std EDA tools, including: IJTAG ICL extraction and PDL modeling, DFT logic insertion, pattern generation, and diagnostics, Design Background Experience in writing verilog/system verilog RTL related to DFT logic design, ATE Test Readiness Lead DFT-to-ATE handoff, including: Drive generation and sign-off of high-quality test and debug patterns to meet DFT coverage targets, Pattern validation, format conversion, and debugging across wafer sort and final test, Collaboration with PE/Test teams for silicon correlation and production test optimization, yield improvements, Silicon Debug Drive post-silicon validation, failure triage, and yield learning using SCAN diagnosis and MBIST repair signature analysis, Automation Skills Ability to build and maintain scalable DFT automation flows using Python, Tcl, or Perl, Collaboration Proven success driving cross-functional teams involving RTL, physical design, validation, PE, and manufacturing, Execution Excellence Known for being proactive, detail-oriented, and independently accountable for tapeout and post-silicon success, Leadership PREFERRED QUALIFICATIONS Led multi-site/global DFT teams, mentoring engineers and managing design reviews, Drove design-for-test planning in collaboration with customers or design services partners, Technical Depth Strong understanding of DFT-Aware yield improvement and FA, including DPPM reduction strategies, Ability to correlate pre-silicon vs ATE pattern behavior and debug marginality/escape issues, Exposure to Design-for-Debug (DfD) features like trace buffers, signature capture, and observability enhancement, Our inclusive culture empowers Amazonians to deliver the best results for our customers If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, amazon jobs / content / en / how-we-hire / accommodations for more information If the country/region youre applying in isnt listed, please contact your Recruiting Partner, Company ADCI BLR 14 SEZ Job ID: A3037331 Show

Flex is the diversified manufacturing partner of choice that helps market-leading brands design, build and deliver innovative products that improve the world. We believe in the power of diversity and inclusion and cultivate a workplace culture of belonging that views uniqueness as a competitive edge and builds a community that enables our people to push the limits of innovation to make great products that create value and improve people's lives. A career at Flex offers the opportunity to make a difference and invest in your growth in a respectful, inclusive, and collaborative environment. If you are excited about a role but don't meet every bullet point, we encourage you to apply and join us to create the extraordinary. To support our extraordinary teams who build great products and contribute to our growth, we’re looking to add a Engineer- DFM located in Chennai. What a typical day looks like: Doing DFM analysis in PCBA and fabrication analysis in PCB. Analysis of testability and generate DFT report. Simulation mechanical assembly process and create DFA report Creating DFx procedure and check list as per customer requirements Generating DFx reports according to findings, observations as per standards. Work with customer and internal manufacturing team to define DFx requirements and rules. Ensure adherence to targets set for all Process Metrics Ensure timely generation and circulation of DFx Reports to stakeholders. Mentor the team and guide them towards effective deliverables. Train new and existing team members on an ongoing basis on relevant software and tools. Perform root cause analysis to expedite the resolution of service issues. Prepare KPI Reports for Weekly / Monthly for operation review. Skilled in PCBA process, such as: Stencil, Solder paste printing, SMT, wave-soldering, assembly, box build. Should have very good knowledge in IPC standards. Knowledge in PCB fabrication process, PCB layers, PCB design and electronics component packages in all levels. Able to define DFx procedures and check lists Knowledge in PCBA Test development process such as ICT, FCT , Flying Probe Test etc. Knowledge in DFx tools and hands on experience in DFM module software such Vayopro, Valor NPI , Solidworks etc Knowledge in 3D designs of product and simulation of product assembly process. Aptitude to work with a multi-functional team to define requirements and suitable metrics for the performance of new products and process. Knowledge & direct experience in NPI operations and manufacturing engineering. Able to perform root cause analysis and resolve problems Experience with Continuous Process Improvement, Kanban and Lean manufacturing principals. Flexibility and adaptability to work in a dynamic startup environment Work with other engineering team members to improve existing design or Process. The experience we’re looking to add to our team: Minimum 4-7 years’ experience in DFx methodologies, PCBA DFM process, DFT and DFA analysis. B. Tech (Elec / Electronics), Diploma (Elect / Electronics) Knowledge of MS office and MS outlook Excellent written and oral communication skills MANDATORY. Good analytical skills. Coaching & mentoring skills. Conflict resolution. Reporting & Decision-making skills. Open for night Shift Here are a few examples of what you will get for the great work you provide: Paid Time Off Health Insurance MR03 Site Flex is an Equal Opportunity Employer and employment selection decisions are based on merit, qualifications, and abilities. We celebrate diversity and do not discriminate based on: age, race, religion, color, sex, national origin, marital status, sexual orientation, gender identity, veteran status, disability, pregnancy status, or any other status protected by law. We're happy to provide reasonable accommodations to those with a disability for assistance in the application process. Please email accessibility@flex.com and we'll discuss your specific situation and next steps (NOTE: this email does not accept or consider resumes or applications. This is only for disability assistance. To be considered for a position at Flex, you must complete the application process first).

You have an exciting opportunity to join a dynamic team at MarvyLogic in Bengaluru/Bangalore. With over 10 years of experience in ASIC RTL Design and a Graduate Degree in Electrical/Electronics Engineering (Post Graduate degree is a plus), you will be a valuable addition to our team. As a member of our team, you will be responsible for various tasks related to ASIC RTL Design. Your expertise in Verilog/System Verilog proficiency, experience with multiple clock and power domains, and integration and validation of high-speed PCIe IP core will be crucial. You will also need familiarity with PCIe protocol analyzers and debug, as well as PCIe driver and application software for Linux/Windows. Your role will involve RTL Design and implementation of interface logic between PCIe controller and DMA engines for high-performance networking applications. You will be creating block-level micro-architecture specifications, reviewing vendor IP integration guidelines, and running integrity check tools to ensure compliance throughout the design flow. In addition to your technical responsibilities, you will also need to work and communicate effectively with multi-site teams. Your experience in ASIC product life cycle, including requirements, design, implementation, test, and post-silicon validation, will be essential in this role. If you are passionate about technology solutions and enjoy working in a collaborative environment, we encourage you to apply for this position. Join us at MarvyLogic and be a part of building futuristic and impactful solutions that make a difference in various industries. Your experience with emerging technologies and your contributions to our team may help you evolve both professionally and personally, leading to a more fulfilling life.,