We are looking for a dynamic sales professional with a sharp eye for hunting new logos and farming key accounts in the semiconductor services space. The ideal candidate thrives on relationship-building , consultative selling , and driving service-led engagements especially securing Offshore ODC partnerships. Key Focus Areas: Win new clients and grow existing accounts through strategic, consultative sales Drive ODC business by showcasing scalable delivery models Collaborate with cross-functional teams (TA, Delivery, Legal, Finance) to ensure client success Own end-to-end sales cycles—from prospecting to closure and performance tracking What You Bring: 8–18 years in B2B services sales (semiconductor or engineering domain) Proven success in client acquisition, farming, and winning high-value deals Strong negotiation, relationship, and stakeholder management skills Understanding of remote delivery, managed services, and ODC models If you are passionate about winning logos , crafting client success stories , and creating long-term value , we would love to connect.
Job Description Job Summary: We are looking for a highly experienced and motivated Senior Design Verification Engineer with a deep understanding of the PCIe protocol and hands-on experience in SystemVerilog and UVM. The ideal candidate will lead verification activities for complex PCIe subsystems or SoCs, and contribute to building scalable, reusable verification infrastructure. Key Responsibilities: Develop UVM-based verification environments for PCIe IPs or SoCs . Define and execute comprehensive verification plans for PCIe Gen3/Gen4/Gen5/Gen6 features. Drive testbench development, stimulus generation, scoreboarding, and coverage closure. Validate protocol compliance including LTSSM, TLP/DLLP, BAR/Address decoding, and interrupt mechanisms. Work closely with RTL, DFT, and system validation teams for debug and feature bring-up. Conduct assertion-based verification and participate in formal verification as needed. Collaborate with cross-functional teams to ensure successful first-silicon quality. Required Skills & Experience: B.E./B.Tech or M.E./M.Tech in ECE 8+ years of experience in ASIC/SoC design verification. Proven expertise in SystemVerilog, UVM, and complex testbench development. Deep knowledge of PCIe protocol (Gen3/Gen4/Gen5/Gen6). Experience in verifying Root Complex (RC) and Endpoint (EP) configurations. Familiarity with AMBA protocols (AXI, AHB) and memory-mapped IO. Proficiency with EDA tools like VCS, Questa, Verdi, SimVision. Strong debugging and analytical skills, particularly with PCIe protocol analyzers and simulation waveforms. Scripting proficiency in Python, Perl, TCL, or Shell for automation. Nice to Have: Knowledge of low power (UPF) and DFT concepts. Familiarity with Formal Verification, Portable Stimulus, or Emulation. Exposure to hardware validation, bring-up, or post-silicon debug. Domain experience in datacenter, storage, networking, or automotive industries. Soft Skills: Strong communication and documentation skills Problem-solving mindset and attention to detail Leadership in driving verification tasks and mentoring junior engineers
What are the responsibilities in this role? Develop and execute pre-silicon verification test plans for DFT features of the chip. Develop directed and random verification tests to validate the functionality. Verify DFT design blocks and subsystems (such as MBIST, high speed IO PHY, fuse, clocks, reset) using complex SV or C++ verification environments. Construct SystemVerilog and/or C/C++ models and test sequence libraries for simulation. Build test bench components including agents, monitors, scoreboards for DUT. Compose tests, assertions, checkers, validation vectors and coverage bins to ensure verification completeness. Debug regression test failures to expose specification and implementation issues. Identify and address areas of concern to meet design quality objectives. Develop high coverage and cost effective test patterns, and take part in ATE bring-up. Post silicon ATE and System level debug support of the test patterns delivered. Optimize the test patterns to improve the test quality and reduce test costs. What is the experience and knowledge you should have? 3 to 6 year experience in DFT feature verification (such as JTAG, MBIST, SCAN, fuse, IO-PHY loopback testing) Strong background in Verilog, SystemVerilog (SV), SVA, UVM verification methodologies and C++ Strong debug skills and experience with debug tools such as Verdi. Experience with EDA simulation tools like Synopsys VCS, Cadence NCSIM, Verdi Experience with scripting languages like Tcl/Perl/Ruby/Python Working knowledge of Unix/Linux OS, file version control. Additional skills: Experience in ATE debug, Synthesis, formal/LEC, or power analysis will be a plus. Strong analytical/problem solving skills and pronounced attention to details Knowledge of STA Constraints for various DFT modes. Excellent written and verbal communication
Job Description The person is responsible for ensuring the integrity of a design by analyzing signal connectivity, specifically related to Design for Testability (DFT) features, utilizing Spyglass tools to identify and report potential violations within the test logic. Expertise should include and not limited to the following Strong understanding of digital circuit design principles and timing analysis concepts Experience with RTL design, synthesis Proficiency in scripting languages like TCL, Perl, or Python for automation Excellent problem-solving and debugging skills Strong communication and teamwork abilities to collaborate with cross-functional teams
Role & responsibilities Strong verification expertise using Verilog and SystemVerilog, with solid understanding of UVM methodology and hands-on experience writing test-benches. Proficient in debugging testcases and verifying processor-based subsystems. Knowledge of AMBA protocols (AXI, AHB, APB) is a plus. Exposure to Arm-based SoCs and strong grasp of digital design fundamentals. Experience with scripting in Perl, TCL, Make, and Shell.
Were hiring a talented RTL Design Engineer to join our team in Hyderabad and contribute to advanced ASIC/SoC projects. Key Responsibilities: Perform RTL integration for ASIC/SoC designs Debug CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) violations Analyze and resolve timing and CLP (Clock Level Planning) issues Apply strong digital design fundamentals in RTL development Tackle complex design problems with excellent debugging skills Requirements: 3+ years of experience in RTL design and integration Solid foundation in digital logic design Strong problem-solving and debugging abilities
Position: Design Verification Engineer Experience: 48 Years We are looking for a skilled Design Verification Engineer with hands-on experience in MIPI protocols and Display IP. For any queries or further details, feel free to reach me at karthik.adasu@Proxilera.com Responsibilities: Experience in MIPI protocol verification (e.g., MIPI DSI, CSI). Strong hands-on experience in Display IP verification and validation. Ability to develop and execute verification plans targeting display and MIPI components. Perform RTL, gate-level, low-power simulations; ensure ISO 26262 compliance. Build SystemVerilog/UVM testbenches tailored to MIPI and Display IPs. Perform simulation and debug activities for MIPI/Display-related RTL modules. Collaborate with RTL and integration teams to resolve display and MIPI interface bugs. Integrate MIPI and Display IPs into subsystem or SoC-level test environments. Implement protocol-specific checkers, monitors, and assertions. Analyze functional coverage metrics related to display pipelines and MIPI interfaces. Work closely with post-silicon and firmware teams to validate MIPI and display functionality
Job Information Job Opening ID ZR_105_JOB Industry Engineering Date Opened 06/09/2025 Job Type Full time Work Experience 5-10 Years City Bangalore State/Province Karnataka Country India Zip/Postal Code 560078 Job Description THE ROLE: We are looking for an experienced engineer with an obsession for system software and computer architecture. As part of the role, this engineer will work closely with other diagnostics engineers, developers, and architects across various teams in designing and implementing diagnostics system software that spans across pre-silicon and post-silicon for all AMD SoCs. KEY RESPONSIBILITIES: Development & Testing of Infinity Fabric diagnostic test cases for AMD SoCs Debugging of the test case failures and reporting them to the design team Involvement in test planning of diagnostics Collaboration with various related cross-teams Requirements PREFERRED EXPERIENCE: Expertise in C++ programming Post Silicon diagnostics development & validation Good understanding of data/address bus architecture, caches, memory management. Understanding of PC Hardware, SoC, Chipsets, CPU, GPU, BIOS, firmware etc. Knowledge of x86 / computer architecture Understanding of OS internals Solid knowledge of software development life cycle Strong analytical and problem-solving skills Must be fluent in both written and spoken English.
Job Information Job Opening ID ZR_126_JOB Industry Semiconductor Date Opened 07/01/2025 Job Type Full time Work Experience 5-10 Years City Bangalore State/Province Karnataka Country India Zip/Postal Code 560078 Job Description THE ROLE: As a member of the Computing and Graphics group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. RTL/Integration- Design Engineer The Person: The ideal candidate will have experience developing RTL for IP or subsystems and understand architectural specifications. Responsibilities include IP and subsystem design, integrating multiple IPs, performing quality checks and working collaboratively with the IP/SoC team. Key Responsibilities: Design of IP and subsystems with integration of AMD and other 3rd party IPs Perform quality checks (lint, CDC, and power rule checks) of power-gated digital designs Work collaboratively with other members of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery to SOC Work in partnership with SOC teams to support the IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up Preferred Experience: 5-10 years full-time experience in IP hardware design Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs Verilog lint tools (Spyglass) and verilog simulation tools (VCS) Clock domain crossing (CDC) tools Detailed understanding of SoC design flows Understanding of IP/SS/SoC Power Management techniques – Power Gating, Clock Gating Experience with embedded processors and data fabric architectures (NoC) Outstanding interaction skills while communicating both written and verbally Ability to work with multi-level functional teams across various geographies Outstanding problem-solving and analytical skills
Job Information Job Opening ID ZR_115_JOB Industry Semiconductor Date Opened 06/12/2025 Job Type Full time Work Experience 3-5 Years City Hyderabad State/Province Telangana Country India Zip/Postal Code 500081 Job Description Job Title : DFT Engineer Job Description : Has worked on scan-stitching; and has good knowledge of scan-stitching related concepts.. Has worked on ATPG; and is well conversed with the files required to run ATPG.. Knowledge / experience with Tessent ATPG (mentor) is a plus Has worked on Spyglass-DFT Knowledge on automation scripts like TCL/PERL is a plus. Basic Job Deliverable : Support Spyglass debug and coverage correlation.. Support scan-stitching runs.. Debug DRC / other scan-related issues Support ATPG.. debug ATPG issues.. debug coverage holes.. Support gate-level simulations..
Job Information Job Opening ID ZR_106_JOB Industry Semiconductor Date Opened 06/10/2025 Job Type Full time Work Experience 4-8 Years City Bangalore South State/Province Karnataka Country India Zip/Postal Code 560078 Job Description We are seeking a skilled VLSI MBIST Engineer with approximately 4 years of experience, specialized in Memory Built-In Self-Test (MBIST) methodologies. The ideal candidate will have hands-on experience with Synopsys SMS tool and be proficient in MBIST pattern generation, fault simulation, and test development for various embedded memories in ASIC/SoC designs. Requirements Key Responsibilities: Develop and implement MBIST algorithms and test patterns for embedded memories (SRAM, DRAM, ROM, CAM) using Synopsys SMS tool. Create MBIST test infrastructure and collaborate with design teams to integrate MBIST macros into SoC designs. Perform fault modeling, fault simulation, and analysis to ensure high fault coverage and test quality. Validate MBIST patterns through simulation and silicon validation. Debug MBIST failures at both pre-silicon and post-silicon stages and provide root cause analysis. Work closely with RTL designers, physical design, and test teams to optimize MBIST architecture and test flows. Generate MBIST test reports, documentation, and provide design-for-test (DFT) reviews. Stay updated with latest MBIST methodologies and industry trends. Required Skills & Qualifications: Bachelor’s/Master’s degree in Electronics, Electrical Engineering, VLSI, or related field. Minimum 4 years of experience in MBIST engineering for ASIC/SoC designs. Strong knowledge of MBIST architectures, memory testing algorithms, and fault models. Hands-on experience with Synopsys SMS tool for MBIST pattern generation and validation. Familiarity with other DFT tools and methodologies is a plus. Proficient in scripting languages such as TCL, Perl, or Python for automation of MBIST flows. Good understanding of digital design and RTL coding (Verilog/SystemVerilog). Experience with simulation tools (ModelSim, VCS, etc.) and testbench development. Strong analytical and problem-solving skills with attention to detail. Good communication skills and ability to work in a team environment. Preferred Skills: Experience with other memory test tools or DFT tools like Tessent. Knowledge of ATPG and other DFT methodologies. Exposure to silicon bring-up and failure analysis. Familiarity with industry standards such as IEEE 1149.1 (JTAG), IEEE 1500.
Job Information Job Opening ID ZR_12_JOB Industry Semiconductor Date Opened 06/19/2025 Job Type Full time Work Experience 10+ Years City Bangalore State/Province Karnataka Country India Zip/Postal Code 560078 Job Description Job Summary: We are looking for a highly experienced and motivated Senior Design Verification Engineer with a deep understanding of the PCIe protocol and hands-on experience in SystemVerilog and UVM. The ideal candidate will lead verification activities for complex PCIe subsystems or SoCs, and contribute to building scalable, reusable verification infrastructure. Key Responsibilities: Develop UVM-based verification environments for PCIe IPs or SoCs . Define and execute comprehensive verification plans for PCIe Gen3/Gen4/Gen5/Gen6 features. Drive testbench development, stimulus generation, scoreboarding, and coverage closure. Validate protocol compliance including LTSSM, TLP/DLLP, BAR/Address decoding, and interrupt mechanisms. Work closely with RTL, DFT, and system validation teams for debug and feature bring-up. Conduct assertion-based verification and participate in formal verification as needed. Collaborate with cross-functional teams to ensure successful first-silicon quality. Required Skills & Experience: B.E./B.Tech or M.E./M.Tech in ECE 8+ years of experience in ASIC/SoC design verification. Proven expertise in SystemVerilog, UVM, and complex testbench development. Deep knowledge of PCIe protocol (Gen3/Gen4/Gen5/Gen6). Experience in verifying Root Complex (RC) and Endpoint (EP) configurations. Familiarity with AMBA protocols (AXI, AHB) and memory-mapped IO. Proficiency with EDA tools like VCS, Questa, Verdi, SimVision. Strong debugging and analytical skills, particularly with PCIe protocol analyzers and simulation waveforms. Scripting proficiency in Python, Perl, TCL, or Shell for automation. Nice to Have: Knowledge of low power (UPF) and DFT concepts. Familiarity with Formal Verification, Portable Stimulus, or Emulation. Exposure to hardware validation, bring-up, or post-silicon debug. Domain experience in datacenter, storage, networking, or automotive industries. Soft Skills: Strong communication and documentation skills Problem-solving mindset and attention to detail Leadership in driving verification tasks and mentoring junior engineers
Job Information Job Opening ID ZR_81_JOB Industry Semiconductor Date Opened 05/21/2025 Job Type Full time Work Experience 10-15 Years City Bangalore State/Province Karnataka Country India Zip/Postal Code 560078 Job Description Key Responsibilities: Define and implement verification strategies and test plans for DDR memory interface designs. Develop UVM/SystemVerilog-based testbenches and reusable verification components. Perform protocol-level verification for DDR memory interfaces and validate compliance. Collaborate with architecture, RTL, and system teams to understand design intent and corner cases. Own functional coverage, regression setup, and closure. Integrate DDR models, controllers, PHYs, and validate their interactions. Debug and resolve simulation failures and functional issues. Drive code and functional coverage improvements to ensure thorough verification. Lead or participate in technical reviews and mentor junior engineers. Required Skills: 10+ years of hands-on experience in ASIC/IP/SoC verification. Strong expertise in SystemVerilog, UVM, and functional coverage methodology. In-depth understanding and working experience with DDR3/DDR4/DDR5/LPDDR protocols. Experience with DDR controllers, PHY integration, and JEDEC standards. Proficient in simulation and debug tools such as Synopsys VCS, Cadence Xcelium, QuestaSim, etc. Good scripting skills in Python, Perl, or Shell for automation and regression management. Excellent debugging and problem-solving skills. Familiarity with AXI/AHB protocols and interconnects is a plus. Experience working with memory models and timing analysis. Preferred Qualifications: Experience with post-silicon validation or DDR hardware bring-up. Knowledge of formal verification tools and techniques. Experience with low power verification and timing closure tools.
Job Information Job Opening ID ZR_92_JOB Industry Semiconductor Date Opened 06/02/2025 Job Type Full time Work Experience 5-10 Years City Bangalore State/Province Karnataka Country India Zip/Postal Code 560078 Job Description Job Summary: We are looking for highly skilled RTL Design Engineers with proven hands-on experience in at least three end-to-end production-grade projects. The ideal candidate should have a strong foundation in RTL coding (Verilog/SystemVerilog), with a focus on actual design rather than RTL integration, CDC, or lint activities. This is a critical role contributing to the development of complex SoCs, subsystems, or IPs. Key Responsibilities: Develop synthesizable RTL for high-performance SoC, subsystem, or IP designs Contribute to architecture definition, micro-architecture design, and implementation Collaborate closely with architecture, verification, and physical design teams Own and deliver RTL blocks from spec to tape-out Ensure clean handoff of RTL to verification and synthesis Support post-silicon bring-up and debugging, if required Mandatory Requirements: 5–10 years of hands-on RTL design experience in production-grade projects At least 3 full-cycle design projects (preferably SoC, subsystem, or IP level) Strong expertise in Verilog/SystemVerilog RTL coding Solid understanding of digital design principles including clocking, resets, data-path control, pipelining, etc. Exposure to design closure flow including synthesis and timing closure support Preferred Skills: Familiarity with AMBA (AXI, AHB, APB) or similar interconnects Experience working in cross-functional engineering teams Good understanding of synthesis, STA, and backend interactions Strong problem-solving and debugging skills Excellent communication and documentation capabilities Note: Candidates with only integration, CDC, or lint backgrounds will not be considered . We’re specifically looking for hands-on RTL designers who have delivered real, production-ready logic.
Job Information Job Opening ID ZR_126_JOB Industry Semiconductor Date Opened 07/01/2025 Job Type Full time Work Experience 5-10 Years City Bangalore State/Province Karnataka Country India Zip/Postal Code 560078 Job Description THE ROLE: As a member of the Computing and Graphics group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. RTL/Integration- Design Engineer The Person: The ideal candidate will have experience developing RTL for IP or subsystems and understand architectural specifications. Responsibilities include IP and subsystem design, integrating multiple IPs, performing quality checks and working collaboratively with the IP/SoC team. Key Responsibilities: Design of IP and subsystems with integration of AMD and other 3rd party IPs Perform quality checks (lint, CDC, and power rule checks) of power-gated digital designs Work collaboratively with other members of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery to SOC Work in partnership with SOC teams to support the IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up Preferred Experience: 5-10 years full-time experience in IP hardware design Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs Verilog lint tools (Spyglass) and verilog simulation tools (VCS) Clock domain crossing (CDC) tools Detailed understanding of SoC design flows Understanding of IP/SS/SoC Power Management techniques – Power Gating, Clock Gating Experience with embedded processors and data fabric architectures (NoC) Outstanding interaction skills while communicating both written and verbally Ability to work with multi-level functional teams across various geographies Outstanding problem-solving and analytical skills
Job Information Job Opening ID ZR_93_JOB Industry Semiconductor Date Opened 06/02/2025 Job Type Full time Work Experience 10+ Years City Bangalore State/Province Karnataka Country India Zip/Postal Code 560078 Job Description SoC NoC Verification Lead with 10+ years of experience, the role typically expands to include leadership, strategic planning, and advanced debugging. This role involves developing test plans, writing verification code, debugging issues, and collaborating with design teams to validate complex interconnect systems. Key Responsibilities: Lead verification projects for complex SoC and NoC architectures. Develop advanced verification methodologies using SystemVerilog/UVM . Guide teams in debugging and resolving intricate design issues . Optimize performance, power, and coverage metrics . Work with high-speed interconnect protocols (AXI, CHI, PCIe, Ethernet, CXL, UCIe). Manage testbench architecture and automation frameworks .
Job Information Job Opening ID ZR_13_JOB Industry Semiconductor Date Opened 05/08/2025 Job Type Full time Work Experience 5-15 Years City Bangalore State/Province Karnataka Country India Zip/Postal Code 560078 Job Description Job Summary: We are seeking a passionate and experienced Design Verification Engineer with a minimum of 6 years in pre-silicon verification. The ideal candidate will have strong hands-on experience with SystemVerilog, UVM methodology, and a solid understanding of SoC/IP-level verification flows. This role involves working closely with design, architecture, and post-silicon teams to ensure high-quality and robust product delivery. Key Responsibilities: Develop testbenches, testcases, and verification components using SystemVerilog and UVM. Create and execute detailed verification plans based on design and architecture specifications. Drive constrained-random verification, coverage closure, and debug failures. Collaborate with RTL, DFT, and Firmware teams to debug issues and ensure seamless integration. Build reusable, scalable, and modular verification environments. Analyze code coverage, functional coverage, and provide meaningful feedback for design improvements. Perform assertion-based verification and support formal verification where required. Participate in code reviews, test plan reviews, and contribute to process improvements. Required Skills & Qualifications: B.E./B.Tech or M.E./M.Tech in Electronics. 6+ years of experience in ASIC/IP/SoC verification. Must have good knowledge on the verification flows Experience developing testbenches for block level or IP level or SOC Level verification. Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC Developing and maintaining block level test benches Proficient in SystemVerilog, UVM, and testbench architecture. Strong knowledge of AMBA protocols (AXI, AHB, APB). Hands-on experience with simulation tools (VCS, Questa, XSIM, etc.). Familiarity with debug tools (Verdi, DVE) and waveform analysis. Solid understanding of functional coverage, assertions, and scoreboarding. Experience in writing automation scripts using Python/Perl/TCL.
Job Information Job Opening ID ZR_133_JOB Industry Engineering Date Opened 07/05/2025 Job Type Full time Work Experience 5-7 years City Bangalore State/Province Karnataka Country India Zip/Postal Code 560102 Job Description Key Responsibilities: Develop and implement scalable UVM-based verification environments Lead and execute GLS (Gate-Level Simulation)—timing-aware and glitch-sensitive validation is a core part of this role (must) Perform Clock Domain Crossing (CDC) verification using industry-standard methodologies Collaborate cross-functionally with RTL, DFT, and system teams for end-to-end verification closure Analyze waveforms, root-cause issues, and contribute to debugging complex logic Requirements Required Skills: Solid hands-on experience with SystemVerilog and UVM methodologies Strong understanding and application of GLS (Gate-Level Simulation) techniques Experience with CDC verification and asynchronous domain handling Familiarity with tools such as VCS, Questa, Incisive Scripting knowledge (Python, Perl, or Shell) is a plus
Job Information Job Opening ID ZR_94_JOB Industry Semiconductor Date Opened 06/02/2025 Job Type Full time Work Experience 7+ Years City Bangalore State/Province Karnataka Country India Zip/Postal Code 560078 Job Description SoC NoC Verification Engineer with 7+ years of experience This role involves developing test plans, writing verification code, debugging issues, and collaborating with design teams to validate complex interconnect systems. Key Responsibilities Develop and execute verification plans for SoC and NoC architectures. Write and maintain test benches using SystemVerilog/UVM . Perform functional, performance, and power verification . Debug and resolve design and verification issues . Work with high-speed interconnect protocols (AXI, CHI, PCIe, Ethernet, CXL, UCIe). Work closely with design and architecture teams to ensure compliance with specifications.
Job Information Job Opening ID ZR_105_JOB Industry Engineering Date Opened 06/09/2025 Job Type Full time Work Experience 5-10 Years City Bangalore State/Province Karnataka Country India Zip/Postal Code 560078 Job Description THE ROLE: We are looking for an experienced engineer with an obsession for system software and computer architecture. As part of the role, this engineer will work closely with other diagnostics engineers, developers, and architects across various teams in designing and implementing diagnostics system software that spans across pre-silicon and post-silicon for all AMD SoCs. KEY RESPONSIBILITIES: Development & Testing of Infinity Fabric diagnostic test cases for AMD SoCs Debugging of the test case failures and reporting them to the design team Involvement in test planning of diagnostics Collaboration with various related cross-teams Requirements PREFERRED EXPERIENCE: Expertise in C++ programming Post Silicon diagnostics development & validation Good understanding of data/address bus architecture, caches, memory management. Understanding of PC Hardware, SoC, Chipsets, CPU, GPU, BIOS, firmware etc. Knowledge of x86 / computer architecture Understanding of OS internals Solid knowledge of software development life cycle Strong analytical and problem-solving skills Must be fluent in both written and spoken English.