4 to 10 years experience in ASIC DFT (Simulation and Silicon Validation) Experience with at least 3 of the following core DFT skills is needed (Deep knowledge and hands-on expertise) Scan Insertion BIST, MBIST, LBIST Create test patterns and perform ATPG simulation/analysis to ensure coverage goals are met Gate-level (0-delay and SDF) scan simulations Fault simulations Debug DFT related issues during silicon bring-up Memory verification, repair and failure root-cause analysis Should have worked on at least one full-chip DFT project Experience using two or more of the following EDA tools is required ATPG TestKompress MBIST MentorETVerify Simulation VCS/ModelSim Synopsys TestMAX Synopsys TetraMAX Mentor Graphics Tessent Expertise with at least one scripting language (Tcl, Perl, Python, etc.) for automation is a must Work closely with design, verification, and physical design teams to integrate DFT requirements seamlessly into the overall design process
Role: Physical Design (PD) Engineer 7 10 Yrs Location: Hyderabad Work Mode: WFO Experience Required: 7 10 years of experience in Physical Design Prior AMD experience is highly preferred Role Description: The candidate will be responsible for implementing the place and route of design blocks including floorplanning, placement, clock tree building, routing, timing optimizations, DRC, LVS fixing, IR drop analysis, Formal verification, power intent checks etc. The candidate will also be responsible for block-level physical design closure in terms of timing, power, DRC/LVS etc. Full Chip Floorplan: Bus planning Pin assignments Tile area allocations Repeater planning and Feedthrough push Full chip Tile PnR
Roles and Responsibilities: 4 to 10 years hands-on experience with Zebu/Veloce/Palladium systems Model builds (end-to-end) synthesize RTL and compile them for the emulation system Test runs expertise functional and performance tests Excellent failure debug skills on emulators, experience using waveform debug tools like Verdi and interacting with designers/SW teams as needed Develop or integrate high performance transactors with the emulation test bench using SystemVerilog/UVM and C/C++ Good knowledge of SoC architecture (or) Graphics system architecture Protocol expertise in PCIe or AXI4/CHI is highly desirable (not a must) Proficient with at least one scripting language (Python, Perl, Shell, etc.)
Role Summary: We re bringing in a senior PD engineer who can handle full-chip PnR with confidence. If timing closure, ECO planning, and advanced-node sign-off are things you enjoy, this role gives you full ownership. Responsibilities Own full-chip PnR using tools like Innovus/ICC2 Drive timing closure across all corners Lead floorplanning and partitioning Run CTS, routing, IR/EM checks Handle DRC/LVS sign-off Plan and execute ECOs Automate flows with scripts Mentor junior PD engineers
Lead SoC Verification Engineer (UVM / TB Architecture) Role summary Own end-to-end verification of complex SoCs or large subsystems. This is a hands-on role from testbench architecture to coverage closure, through tapeout and into silicon correlation. What you ll do Architect and build scalable UVM testbenches from scratch at subsystem or SoC level Strong hands-on experience in testbench development Define verification strategy and author test plans from specs and micro-architecture Develop constrained-random and directed tests, scoreboards, checkers, assertions (SVA) , and coverage models Drive functional, code, and assertion coverage closure with discipline Debug complex issues using waveforms, logs, and root-cause analysis Lead SoC-level verification: IP integration, coherency, low-power modes, resets/boot, and performance validation Work closely with RTL, architecture, DFT, and firmware teams Support silicon bring-up and pre-/post-silicon correlation Must-have skills 8+ years of hands-on ASIC verification (FPGA/emulation-only experience does not count) Strong TB Architecture ownership design, reuse strategy, scalability, and maintainability Multiple production ASIC tapeouts with SoC or large subsystem ownership Expert in SystemVerilog, UVM, SVA , and constrained-random methodologies Deep experience with AXI/ACE, DDR, PCIe, coherency, memory and interrupt fabrics Proven strength in test planning, stimulus strategy, checkers/scoreboards, and closure execution Excellent debug skills across simulation and silicon correlation
Proficient on GLS verification using Xcelium and VCS. 3yr+ GLS experience. Good physical design knowledge for GLS domain. Verification knowledge of SV, UVM based test bench. DDR, HBM PHY GLS experience will be a plus. Cadence Xcelium tool experience is mandatory Basic knowledge about SOC design and common bus protocol will be a plus.
Job Summary: We are seeking a creative and results-driven Digital Marketing Executive to join our marketing team. The ideal candidate will be responsible for planning, implementing, and monitoring our digital marketing campaigns across all digital networks to drive online traffic, brand awareness, and lead generation. Key Responsibilities: Develop, implement, and manage digital marketing campaigns across platforms (Google Ads, Meta, LinkedIn, etc.). Optimize website content and landing pages for SEO and user engagement. Manage and grow the company s social media presence on all relevant channels. Plan and execute email marketing campaigns, including newsletters and automation flows. Conduct keyword research and use SEO best practices to increase organic visibility. Measure and report the performance of digital marketing campaigns (ROI and KPIs). Collaborate with designers, content creators, and developers to create engaging marketing assets. Stay updated with the latest trends and best practices in digital marketing and analytics. Monitor and analyze competitor activities to identify opportunities for growth. Key Skills Qualifications: Bachelor s degree in Marketing, Communications, Business, or a related field. 1 3 years of experience in digital marketing or a similar role. Strong understanding of SEO, SEM, Google Analytics, and PPC campaigns. Experience with social media management tools (e.g., Hootsuite, Buffer). Knowledge of content management systems (WordPress, Shopify, etc.). Proficiency in using Google Ads, Facebook Business Manager, and email marketing tools. Excellent communication and analytical skills. Creative mindset with strong attention to detail.
Own UVM-based constrained-random verification for complex SoC/IP subsystems. Develop testbenches, sequences, scoreboards, and checkers; close coverage (FC/CC/SC). Must have SystemVerilog/UVM, assertions (SVA), functional coverage, and regressions. Experience with bus protocols (AXI/AHB/APB/PCIe), cache/Coherency, and interrupts. Debug with waveforms, CDC/RDC awareness, lint, and formal/property checks. Tools: VCS/Questa/Xcelium, Verdi/DVE, Jenkins/CI, code reviews. Strong scripting (Python/Perl/TCL), Make/CMake, version control (Git). Work with architects/design/DFT/PD for spec clarification and sign-off. Mandatory Skills to be checked in CV SystemVerilog / UVM Assertions (SVA) / Functional Coverage Protocols (AXI / AHB / APB / PCIe) VCS / Questa / Xcelium + Python/TCL scripting
Job Role: A senior DFT specialist who can take full ownership of PMBIST planning, insertion, verification, and closure. Someone who s comfortable running end-to-end DFT flows, debugging patterns, and driving coverage targets with minimal supervision. Key Skills required: PMBIST architecture, integration, and verification PMBIST Experience in Cadence Modus tool is mandator y ATPG, fault models, scan insertion, pattern debug Coverage analysis and sign-off Synopsys / Mentor / Cadence DFT tools Experience working on complex SoCs Good to have: LBIST familiarity Silicon bring-up exposure Prior EU/US customer interaction
The Job Role: You ll lead full-custom memory layout work for SRAM compilers, owning layout creation, physical verification, and sign-off quality. This role calls for someone who knows the craft inside out and can turn complex circuits into clean, high-quality layouts. Responsibilities: Full-custom memory layout development for SRAM compiler blocks Complete physical verification across EM, IR, LVS, DRC and related flows Work closely with circuit, architecture, and verification teams Drive layout quality, constraints, and design-rule adherence Support optimization, debug, and design-rule closure Qualifications: MTech/BTech in ECE or related field 7+ years of hands-on SRAM compiler layout experience Strong grounding in full-custom memory layout and sign-off verification flows
At minimum a candidate MUST have solid experience in at least four (4) of the above listed skill areas. Responsibilities Implement/Integrate and verify DFT logic, for example, memory built-in self test (MBIST), scan chains, DFT compression, TAP controller, BSCN, iJTAG instrumentation, functional BIST, logic BIST and eFuse logic on test chips. Work with silicon engineering team to create test plans and generate test patterns Participate in post-silicon activity like bring up, diagnostics and characterization Work with EDA and IP vendors to incorporate state-of-the-art DFT/DFD/DFY flows and methodologies. Provide support to internal teams. Scan insertion, Scan compression, Stuck-At, At-Speed test and coverage analysis MBIST insertion, simulation and debug on RTL and gates netlist Scan ATPG pattern generation, simulation and debug on RTL and gates netlist In-depth knowledge of Verilog HDL and experience with simulators and waveform debugging tools Integrate DFT/BIST insertion flows into synthesis flow Timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation) Must-have qualifications: Minimum 5 years of industry experience Hands on knowledge in state-of-the-art EDA tools for DFT, design and verification (Mentor DFT Tools, Synopsys Simulation Tools) Experience with RTL design and Design verification principles Experience with clock domain crossings, DFT/Scan/MBIST/LBIST and understanding of their impact on synthesis, physical design and timing closure Experience with industry standard simulation tools, including Verilog, and scripting languages like Perl, Python, Shell or Tcl Excellent scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.) Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment Work independently to generate test plans, run simulations and debug failures on RTL and Gate Level Strong fundamental knowledge of various Test standards (such as IEEE 1149.10, 1149.6, 1500, 1687) and test formats (such as BSDL, ICL, PDL, STIL, CTL) Direct experience in silicon bring-up, debug, and validation of DFT features on ATE, debugging ATPG patterns, Compressed ATPG patterns, MBIST and JTAG related issues Experience with User Defined Fault Models (UDFM) generation like Cell-Aware and other fault models like GDD, SDD Experience with STA constraints development and analysis for DFT modes and SDF simulations Ability to communicate and work with multi-disciplined teams across multiple sites and time time zones.
We are looking for a skilled IT Administrator to join our team in Proxelera. The ideal candidate will have experience in managing and maintaining computer systems, networks, and software applications. Roles and Responsibility Manage and maintain computer systems, networks, and software applications. Troubleshoot and resolve technical issues efficiently. Ensure system security and integrity by implementing necessary measures. Collaborate with other teams to achieve organizational goals. Develop and implement new technologies to improve efficiency. Provide technical support and training to employees as needed. Job Requirements Strong knowledge of computer systems, networks, and software applications. Excellent problem-solving skills and attention to detail. Ability to work independently and collaboratively as part of a team. Strong communication and interpersonal skills. Familiarity with industry-standard protocols and procedures. Ability to adapt to new technologies and learn quickly. Disclaimer: This job description has been sourced from a public domain and may have been modified by Naukri.com to improve clarity for our users. We encourage job seekers to verify all details directly with the employer via their official channels before applying.
BE/B.Tech in ECE /M.Tech in VLSI with 3 to 9 years experience in Analog Mixed Signal Verification Very Good experience in Verilog AMS, Verilog-A, WREAL, modeling of Analog blocks Very Good experience in Analog Mixed Signal verification simulation tools. Good experience in System Verilog, UVM methodologies Able to train the team members and guide them to the solutions for problems Good experience in creating the AMS Verification environment and able to create AMS Verification environment from scratch. Good experience in Gate level netlist simulation Experience in Python, Perl, Shell scripting is added advantage. Good communication and documentation skills
Own end-to-end DFT architecture, planning, and implementation for complex SoCs. Develop and integrate scan, MBIST/LBIST, boundary scan (IEEE 1149.1/1500), and compression. Generate ATPG patterns, analyze coverage, and drive defect reduction/yield improvements. Expertise with Tessent / DFTAdvisor / SpyGlass-DFT , ATPG, and fault simulation. Hands-on with RTL/gate-level insertion, constraints, and timing/area/power trade-offs. Silicon bring-up, ATE pattern debug, diagnostics, and failure analysis. Strong RTL (Verilog/SystemVerilog), STA basics, scripting (TCL/Python/Perl). Collaborate with design/PD/ATE teams; excellent communication and documentation. Mandatory Skiils: Scan chain design / ATPG Verilog / SystemVerilog (HDL) MBIST / LBIST / Boundary Scan (JTAG) Tessent / Mentor / Cadence DFT tools + TCL/Python scripting
Job Summary: We are seeking a highly skilled Design Verification Engineer with 6+ years of experience , specializing in building and enhancing testbenches for complex digital designs. The ideal candidate will have strong expertise in verification methodologies, testbench architecture, and debugging, with hands-on experience in UVM-based environments. Required Skills: Strong hands-on experience in testbench development (UVM preferred). Proficient in SystemVerilog , UVM/OVM/VMM methodologies. Strong debugging skills using tools like VCS, Questa, or Xcelium. Good understanding of digital design concepts (RTL, clocking, resets, FIFOs, DMA, etc.). Experience in writing assertions (SVA) and functional coverage. Familiarity with scripting languages (Python, Perl, Shell, etc.) for automation. Strong analytical and problem-solving skills.
Job Role: Lead Static Timing Analysis for complex SoC/ASIC designs, driving sign-off quality across multi-mode multi-corner scenarios while partnering closely with Physical Design, RTL, and Foundry teams. Must-Have Skills 10+ years in STA with deep expertise in PD-STA convergence for advanced nodes (7nm/5nm or similar). Hands-on mastery with PrimeTime (including ECO closure), SDC constraints, MMMC setup, and sign-off methodologies. Strong command of timing concepts: OCV/AOCV/POCV, CTS timing closure, IR/EM-aware timing, derate strategies, false/multicycle paths. Proven experience in block-to-top timing closure, interface timing (DDR/SerDes), and cross-domain CDC/RDC checks. Scripting proficiency in Tcl, Python/Perl for automation, report mining, and ECO generation. Collaborative leadership with PD/RTL/DFT, driving root-cause, waivers, and risk mitigation to tapeout. Excellent debug skills on congestion-driven timing, SI/crosstalk, and variability across PVT corners. Good to have Experience with TSMC sign-off flows and Liberty/tech file nuances. Exposure to low-power timing (UPF/CPF) and ECO flows post-route/post-mask
Job Description: 5+ years of related work experience. You are a detail-oriented Test Timing Engineer with strong analytical skills and a deep understanding of timing constraints, such as clock groups, various exceptions, clock exclusivity. You will collaborate effectively with cross-functional teams, communicate complex timing data clearly. Responsibilities will include: Developing timing constraints at block, sub-chip, and full-chip levels in test modes, performing quality checks such as duplicated constraints, promotion/demotion between block and top level SDCs. Check timing for unconstrained endpoints, no clock, etc. Your role may include SDC validation, CDC delay check, and SDC flow development. Developing methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to ensure progress and accuracy. Minimum Qualifications Bachelor s degree in electrical or computer engineering (or other equivalent field) with Experience with block/full chip SDC development in test modes (scan shift, scan capture, atpg capture modes). Expertise in Static Timing Analysis and prior working experience with STA tools like PrimeTime. Programming skills in at least 2 or more of the following languages: Perl, TCL, Python, Makefile, or other relative scripting languages. Preferred Qualifications Background in debugging and analyzing timing constraints, timing closure of DFT modes such as scan shift/capture and BIST. Prior working experience with SDC debugging & STA tools: Synopsys GCA/TCM/Primetime. Prior working experience with synthesis tools: Synopsys Fusion Compiler. Prior working experience with Tessent tool: DFT insertion in RTL. Strong communication skills and team player.
Job Title: SoC ATPG Engineer Experience: 6 Years Location: Bangalore / Hyderabad Employment Type: Permanent Number of Positions: 1 Key Responsibilities Develop and implement ATPG (Automatic Test Pattern Generation) for complex SoC designs. Perform DFT pattern generation, fault simulation, and coverage analysis . Work closely with DFT and verification teams to improve test coverage and quality. Debug ATPG patterns and support silicon bring-up and test activities. Optimize test methodologies to enhance efficiency and reduce test time. Required Skills Strong hands-on experience in SoC-level ATPG and fault coverage improvement. Proficiency in DFT tools such as Synopsys TetraMAX, Cadence Modus, or equivalent. Good understanding of DFT architectures scan insertion, MBIST, JTAG, boundary scan. Familiarity with STA, synthesis, and RTL design flows . Excellent problem-solving and debugging skills.
Job Title: NOC Verification Engineer Location: Bangalore Experience: 7+ years Domain: DV Open Positions: 3 Job Description SoC NoC Verification Engineer with 7+ years of experience. This role involves developing test plans, writing verification code, debugging issues, and collaborating with design teams to validate complex interconnect systems. Key Responsibilities Develop and execute verification plans for SoC and NoC architectures. Write and maintain testbenches using SystemVerilog/UVM. Perform functional, performance, and power verification. Debug and resolve design and verification issues. Work with high-speed interconnect protocols (AXI, CHI, PCIe, Ethernet, CXL, UCIe). Work closely with design and architecture teams to ensure compliance with specifications.
Job Title: NOC Verification Engineer- Lead Location: Bangalore Experience: 10+ years Domain: DV Open Positions: 1 Job Description: SoC NoC Verification Lead with 10+ years of experience. The role typically expands to include leadership, strategic planning, and advanced debugging. This role involves developing test plans, writing verification code, debugging issues, and collaborating with design teams to validate complex interconnect systems. Key Responsibilities Lead verification projects for complex SoC and NoC architectures. Develop advanced verification methodologies using SystemVerilog/UVM. Guide teams in debugging and resolving intricate design issues. Optimize performance, power, and coverage metrics. Work with high-speed interconnect protocols (AXI, CHI, PCIe, Ethernet, CXL, UCIe). Manage testbench architecture and automation frameworks.