Jobs
Interviews
Proxelera logo

DV Engineer (System Verilog, UVM)

0 - 6 years

0 Lacs

Bengaluru Karnataka

Posted:3 months ago| Platform: Indeed logo

Apply

Skills Required

verilog design verification systemverilog ip architecture drive dft analyze code support test model simulation writing automation python perl

Work Mode

On-site

Job Type

Full Time

Job Description

Job Information

    Job Opening ID

    ZR_13_JOB

    Industry

    Semiconductor

    Date Opened

    05/08/2025

    Job Type

    Full time

    Work Experience

    5-15 Years

    City

    Bangalore

    State/Province

    Karnataka

    Country

    India

    Zip/Postal Code

    560078


Job Summary:
We are seeking a passionate and experienced Design Verification Engineer with a minimum of 6 years in pre-silicon verification. The ideal candidate will have strong hands-on experience with SystemVerilog, UVM methodology, and a solid understanding of SoC/IP-level verification flows. This role involves working closely with design, architecture, and post-silicon teams to ensure high-quality and robust product delivery.

Key Responsibilities:
  • Develop testbenches, testcases, and verification components using SystemVerilog and UVM.
  • Create and execute detailed verification plans based on design and architecture specifications.
  • Drive constrained-random verification, coverage closure, and debug failures.
  • Collaborate with RTL, DFT, and Firmware teams to debug issues and ensure seamless integration.
  • Build reusable, scalable, and modular verification environments.
  • Analyze code coverage, functional coverage, and provide meaningful feedback for design improvements.
  • Perform assertion-based verification and support formal verification where required.
  • Participate in code reviews, test plan reviews, and contribute to process improvements.

Required Skills & Qualifications:
  • B.E./B.Tech or M.E./M.Tech in Electronics.
  • 6+ years of experience in ASIC/IP/SoC verification.
  • Must have good knowledge on the verification flows
  • Experience developing testbenches for block level or IP level or SOC Level verification.
  • Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC
  • Developing and maintaining block level test benches
  • Proficient in SystemVerilog, UVM, and testbench architecture.
  • Strong knowledge of AMBA protocols (AXI, AHB, APB).
  • Hands-on experience with simulation tools (VCS, Questa, XSIM, etc.).
  • Familiarity with debug tools (Verdi, DVE) and waveform analysis.
  • Solid understanding of functional coverage, assertions, and scoreboarding.
  • Experience in writing automation scripts using Python/Perl/TCL.

More Jobs at Proxelera

Business Development Manager

Bengaluru

8.0 - 13.0 yrs
|

INR 0 - 0 Lacs

DV Engineer (PCIE)

Bengaluru

5.0 - 10.0 yrs
|

INR 0 - 0 Lacs

DV MBIST Verification Engineer

Hyderabad

4.0 - 9.0 yrs
|

INR 0 - 1 Lacs

DFT MBIST Engineer

Hyderabad

3.0 - 5.0 yrs
|

INR 0 - 0 Lacs

Design and Verification Engineer

Hyderabad

5.0 - 10.0 yrs
|

INR 10 - 20 Lacs

Mock Interview

Practice Video Interview with JobPe AI

Start Python Interview
cta

Start Your Job Search Today

Browse through a variety of job opportunities tailored to your skills and preferences. Filter by location, experience, salary, and more to find your perfect fit.

Job Application AI Bot

Job Application AI Bot

Apply to 20+ Portals in one click

Download Now

Download the Mobile App

Instantly access job listings, apply easily, and track applications.

Google Play App Store
coding practice

Enhance Your Python Skills

Practice Python coding challenges to boost your skills

Start Practicing Python Now
Proxelera logo
Proxelera

RecommendedJobs for You

DV Engineer (System Verilog, UVM)

Proxelera

Bengaluru, Karnataka