9 Systemverilog Jobs

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with verification methodologies and languages such as UVM and SystemVerilog. Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, caches, hierarchical memory subsystems, DDR/LPDDR). Experience in developing and maintaining verification testbenches, test cases, and test environments. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. 10 years of ...

Experience : 3.00 + years Salary : INR 2680000-3750000 / year (based on experience) Expected Notice Period : 30 Days Shift : (GMT+05:30) Asia/Kolkata (IST) Opportunity Type : Remote Placement Type : Full Time Permanent position(Payroll and Compliance to be managed by: Architect Labs) (*Note: This is a requirement for one of Uplers' client - Architect Labs) What do you need for this opportunity? Must have skills required: emulation, Flexibility, tapeout, Data Analysis, Verilog/System-Verilog, RTL, synthesis, Unit Level testing, Python, typescripts, SoC integration Architect Labs is Looking for: As a RTL/Design Engineer at Architect Labs , you'll redefine the hardware design and verification p...

Experience : 3.00 + years Salary : INR 2680000-3750000 / year (based on experience) Expected Notice Period : 30 Days Shift : (GMT+05:30) Asia/Kolkata (IST) Opportunity Type : Remote Placement Type : Full Time Permanent position(Payroll and Compliance to be managed by: Architect Labs) (*Note: This is a requirement for one of Uplers' client - Architect Labs) What do you need for this opportunity? Must have skills required: emulation, Flexibility, tapeout, Data Analysis, Verilog/System-Verilog, RTL, synthesis, Unit Level testing, Python, typescripts, SoC integration Architect Labs is Looking for: As a RTL/Design Engineer at Architect Labs , you'll redefine the hardware design and verification p...

Experience : 3.00 + years Salary : INR 2680000-3750000 / year (based on experience) Expected Notice Period : 30 Days Shift : (GMT+05:30) Asia/Kolkata (IST) Opportunity Type : Remote Placement Type : Full Time Permanent position(Payroll and Compliance to be managed by: Architect Labs) (*Note: This is a requirement for one of Uplers' client - Architect Labs) What do you need for this opportunity? Must have skills required: emulation, Flexibility, tapeout, Data Analysis, Verilog/System-Verilog, RTL, synthesis, Unit Level testing, Python, typescripts, SoC integration Architect Labs is Looking for: As a RTL/Design Engineer at Architect Labs , you'll redefine the hardware design and verification p...

As a Design Verification Lead, you will play a crucial role in leading verification engineers to guarantee the delivery of high-quality product releases within the specified timelines. Your responsibilities will involve collaborating effectively with cross-functional teams such as design engineering and hardware development. In addition, you will be responsible for developing testbenches utilizing SystemVerilog/UVM OOP principles. Your expertise will be crucial in suggesting optimization techniques for complex HDL code. **Key Responsibilities:** - Lead verification engineers to ensure high-quality product releases within specified timelines. - Collaborate effectively with cross-functional te...

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with Design Verification of Subsystem (SS) or SoC designs. Experience in Python or Perl for automating verification environments, data processing including digital logic, pipeline architectures and common bus protocols (e.g., AXI, AHB). Experience in SystemVerilog (SV) and UVM for ASIC/IP verification. Experience in building Portable Stimuli based test/test bench framework. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis o...

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with digital reasoning design principles, RTL design concepts, and languages like Verilog or SystemVerilog. Experience with micro-architecture and coding in one or more of these areas: memory compression, interconnects, coherence, cache, Dynamic Random Access Memory (DRAM) controller, Physical Layer Devices (PHYs). Experience in performance design, multi power domains with clocking. Experience with multiple System on a chip (SoCs). Preferred qualifications: Master's degree or PhD in Electrical Engineering, C...

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 year of experience with SystemVerilog/Universal Verification Methodology (UVM) and coherency concepts. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science. Experience using formal techniques (e.g., JasperGold or Verification Compiler (VC) Formal) for verifying cache state transitions, credit management, and deadlock scenarios. Experience in defining and closing functional coverage for multi-agent coherency scenarios. Experience with correlating pre-silicon coheren...

Job Requirements Lead RTL design activities for complex digital blocks and guide the team from architecture to tape-out. Key Responsibilities: Own and develop RTL for complex digital designs Define micro-architecture and review design specifications Lead code reviews and ensure high-quality, synthesizable RTL Work closely with verification, architecture, and backend teams Drive timing, power, and area–aware RTL design Support integration, debug, and silicon bring-up activities Required Skills & Experience: 6–9 years of experience in RTL design Strong proficiency in Verilog / SystemVerilog Experience with SoC / IP-level design Good understanding of synthesis and timing concepts Experience men...