849 Systemverilog Jobs

We are hiring....Role: VLSI Engineer - Semiconductor Experience: 5-6YearsLocation: HyderabadFull timeWork from office onlyVLSI Engineer – Semiconductor Experience (5–6 Years)Job Summary:We are looking for an experienced VLSI Engineer with strong knowledge and hands-on experience in semiconductor design and verification. The ideal candidate should have experience in ASIC/FPGA design, RTL design, verification, and semiconductor process knowledge. The role involves working on complex SoC designs, collaborating with cross-functional teams, and delivering high-quality silicon solutions.✅ Key Responsibilities:Design and develop RTL using Verilog / SystemVerilog for ASIC/FPGA.Perform functional verification using UVM / SystemVerilog based testbench.Work on synthesis, timing analysis, power analysis, and design for testability (DFT).Collaborate with physical design, firmware, and validation teams to ensure design quality.Understand semiconductor process technologies and device physics.Participate in design reviews, architecture discussions, and technical problem-solving.Debug issues in silicon bring-up and post-silicon validation.Work on low-power design techniques and optimizations.Ensure adherence to design specifications, quality, and timelines.✅ Required Skills & Experience:5–6 years of experience in VLSI design and semiconductor industry.Strong knowledge of Verilog / SystemVerilog for RTL design and verification.Experience in ASIC design flow (Synthesis, STA, DFT, DFT tool flow).Experience in UVM-based verification environment.Knowledge of semiconductor process technology (CMOS, FinFET, etc.).Hands-on experience with tools like Cadence, Synopsys, Mentor Graphics (Design Compiler, VCS, IC Compiler, SpyGlass, etc.).Familiarity with scripting (Perl, Python, TCL) for automation.Good understanding of Power, Performance, and Area (PPA) optimization.Knowledge of SoC architecture, memory interfaces, and IP integration.Strong debugging skills, especially in post-silicon validation.Interested guys, kindly share your updated profile to pavani@sandvcapitals.com or reach us on 7995292089. Job Type: Full-time Pay: ₹1,000,000.00 - ₹1,600,000.00 per year Experience: VLSI: 5 years (Required) Work Location: In person

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SOC Verification Engineer THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience. Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Job description Job Description: 1. Strong hands-on FPGA Silicon validation experience 2. Must have protocol expertise in one or more of PCIe-Gen4/5, DDR-4/5, Ethernet, Processor based subsystem. 3. Knowledge of RISC-V processor is a plus 4. Proven track record of planning, executing and handling complex FPGA System Project using Processor based test cases 5. Be responsible for self and team level deliverables of assigned Use Model and Use Cases. Manage work assignments for a group of junior and senior engineers. 6.Train and mentor junior team members and bring them upto speed on the validation activity 7.Track and follow up on dependencies for design creation, embedded software drivers, IP, HW etc. 8. Support and provide guidance to junior team members in debugging issues 9. [Serdes] Excellent knowledge of PMA/PCS architecture, DFE, CTLE. Experience with compliance testing, interop testing and usage of Ethernet traffic testers, PCIe exerciser, network traffic testers etc. 10. [DDR] Excellent knowledge of the DDR memory interface training, initialization and controller validation. Use of debug equipment such as logic analyzers. Performance and stress testing of the interface for robustness. 11. [SOC] Excellent knowledge of processor subsystem validation, bus architecture, application development, NOC, vector processor, peripheral interfaces, boot modes, trace debug. Performance and bandwidth testing Role: Post Silicon Test Engineer Industry Type: Electronic Components / Semiconductors Department: Engineering - Software & QA Employment Type: Full Time, Permanent Role Category: Quality Assurance and Testing Education UG: B.Tech/B.E. in Electronics/Telecommunication

Role Overview: You will be a Senior SOC Design Verification Engineer with a focus on PCIE subsystems, responsible for ensuring the robustness and correctness of cutting-edge System on Chip (SoC) designs. Your role will involve developing and implementing verification plans, creating advanced testbenches, writing and executing test cases, debugging issues, enhancing verification environments, and collaborating with cross-functional teams. Key Responsibilities: - Develop and implement verification plans for complex SoC designs, with a focus on PCIE subsystems. - Create and maintain advanced testbenches using SystemVerilog and UVM (Universal Verification Methodology). - Write and execute test cases to verify functional and performance requirements, particularly for PCIE protocols. - Debug and resolve functional and performance issues in collaboration with design and architecture teams. - Develop and enhance verification environments, including reusable components and checkers for PCIE and related interfaces. - Perform coverage-driven verification and ensure coverage closure. - Collaborate with cross-functional teams to define verification strategies and methodologies. - Mentor junior engineers and contribute to the continuous improvement of verification processes. Qualifications: - 10+ years of hands-on experience in SoC design verification, with a strong focus on PCIE protocols. - Expertise in SystemVerilog and UVM (Universal Verification Methodology). - In-depth knowledge of PCIE specifications (e.g., PCIE Gen3/Gen4/Gen5) and verification methodologies. - Proficiency in developing and debugging complex testbenches and test cases for PCIE subsystems. - Experience with coverage-driven verification and achieving coverage closure. - Familiarity with AMBA protocols (AXI, AHB, APB) and other industry-standard interfaces. - Knowledge of low-power verification techniques and power-aware simulation. - Experience with formal verification tools and methodologies is a plus. - Strong problem-solving skills and attention to detail. - Excellent communication and teamwork skills. Additional Details: You will have the opportunity to work on cutting-edge SoC designs and innovative technologies in a collaborative and inclusive work environment. The company offers a competitive compensation and benefits package along with professional growth and development opportunities.,

As a DFT Verification Engineer, your role involves developing and executing pre-silicon verification test plans for DFT features of the chip. This includes verifying DFT design blocks and subsystems using complex SV or C++ verification environments. You will also be responsible for building test bench components, composing tests, assertions, checkers, and validation vectors to ensure verification completeness. Additionally, debugging regression test failures and addressing areas of concern to meet design quality objectives are key responsibilities. Key Responsibilities: - Develop and execute pre-silicon verification test plans for DFT features of the chip - Verify DFT design blocks and subsystems using complex SV or C++ verification environments - Build test bench components including agents, monitors, scoreboards for DUT - Compose tests, assertions, checkers, validation vectors, and coverage bins - Debug regression test failures and identify specification and implementation issues - Develop high coverage and cost-effective test patterns - Post silicon ATE and System level debug support of the test patterns delivered - Optimize test patterns to improve test quality and reduce test costs Qualifications Required: - 3 to 10 years of experience in DFT feature verification (such as JTAG, MBIST, SCAN, fuse, IO-PHY loopback testing) - Strong background in Verilog, SystemVerilog (SV), SVA, UVM verification methodologies, and C++ - Strong debug skills and experience with debug tools such as Verdi - Experience with EDA simulation tools like Synopsys VCS, Cadence NCSIM, Verdi - Experience with scripting languages like Tcl/Perl/Ruby/Python - Working knowledge of Unix/Linux OS, file version control In addition to the preferred experience, having skills in ATE debug, Synthesis, formal/LEC, or power analysis would be a plus. Strong analytical/problem-solving skills, attention to detail, knowledge of STA Constraints for various DFT modes, and excellent written and verbal communication are essential for this role. Your educational background should include a minimum Engineering Degree in Electronics, Electrical, or Computer Science.,

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SOC Verification Engineer The Role The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience. Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

VeriFast Technologies is expanding and hiring Sr SoC Verification Engineers in Ahmedabad with minimum 7+ years of experience in design verification efforts for complex SoC/IP projects, AXI, Processor Knowledge, SystemVerilog and UVM. Feel free to call me at 9934158404 or drop your updated CV to vkeshav@verifasttech.com. Requirements 1. Exp required minimum 7 years 2. SoC 3. DV 4. AXI 5. Processor Knowledge

Principal Verification Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: A highly-skilled ASIC Digital Verification Engineer with a passion for developing functional verification solutions for RTL based IP Cores. You are experienced in handling complex protocols and thrive in a collaborative international environment. With over 15 years of experience, you possess a deep understanding of verification methodologies and are proficient in SystemVerilog (SV) and Universal Verification Methodology (UVM). You are adept at making architectural decisions, implementing test benches, and driving innovation in verification solutions. You are a proactive team player with excellent communication and problem-solving skills, ready to contribute to cutting-edge projects in AI/machine learning, automotive, and server farm applications. What You’ll Be Doing: Making architecture decisions on test bench design. Writing verification plans and specifications. Implementing test bench infrastructure and writing test cases. Utilizing a coverage-driven methodology. Providing technical leadership and guidance to the team. Collaborating with architects, designers, and other verification team members across multiple sites worldwide. The Impact You Will Have: Ensuring the reliability and performance of IP Cores used in critical applications. Driving innovation in verification methodologies and solutions. Contributing to the development of industry-leading technologies in AI, automotive, and server farms. Enhancing productivity and throughput through effective verification strategies. Maintaining high standards of quality and functionality in IP verification. Mentoring and guiding junior engineers, fostering a culture of continuous learning and improvement. What You’ll Need: Extensive knowledge of protocols such as DDR, PCIe, AMBA (AXI, CHI), SD/eMMC, Ethernet, USB, MIPI. Hands-on experience in creating test environments from functional specifications using UVM/VMM/OVM. Proficiency in SystemVerilog (SV), UVM, and object-oriented coding and verification. Ability to provide innovative verification solutions for enhanced productivity and performance. Experience with scripting languages like C/C++, TCL, Perl, Python is an added advantage. Experience of working with Functional safety, ISO26262 , FMEDA is an added advantage Who You Are: You are an independent thinker with a precise approach to work, capable of driving innovation and leading technical projects. Your communication skills are excellent, and you thrive in a team-oriented environment. You are committed to continuous learning and possess a strong problem-solving aptitude. Experience with functional safety standards like ISO26262 and FMEDA is a plus. The Team You’ll Be A Part Of: You will be part of the Solutions Group at our Bangalore Design Center, India. This team is dedicated to developing functional verification solutions for IP used in diverse applications, including server farms, AI/machine learning, and automotive sectors. You will work closely with architects, designers, and other verification team members across multiple international sites, contributing to innovative and challenging projects. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process....Less

Principal IP/RTL Design Engineer for TPU / GPU Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. Position Overview Seeking an IP/RTL Design Engineer with 5+ years of experience to design IP/RTL for TPUs, focusing on high-performance matrix multiplication, low-latency interconnects, and power-efficient AI acceleration. Key Responsibilities Design IP blocks for TPU cores, including systolic arrays, vector units, and memory subsystems. Develop Verilog/SystemVerilog RTL for performance, timing, and area optimization. Implement high-speed interconnects (e.g., AXI, NoC) for TPU / /GPU. data pipelines. Optimize designs for high throughput, low latency, and power efficiency in AI workloads. Integrate LPDDR6, HBM3, DDR5, or chiplet-based memory interfaces. Support synthesis, timing closure, and FPGA prototyping and Design Verification team Document microarchitecture and design specifications. Required Qualifications Education: BS/MS in Electrical/Computer Engineering. Experience: 10+ years in ASIC/FPGA IP/RTL design, with 3+ years in AI accelerators or GPU / TPU-like architectures. Skills: Proficient in Verilog/SystemVerilog RTL design. Knowledge of GPU/TPU architectures, systolic arrays, or matrix multiplication units. Experience with AXI, NoC, or similar interconnect protocols. Familiarity with LPDDR6, HBM3, DDR5, or high-bandwidth memory interfaces. Proficiency with synthesis and timing tools (e.g., Synopsys Design Compiler). Strong problem-solving and teamwork skills. Preferred Qualifications Experience with AI/ML workloads or datacenter TPU designs and GPU architectures Knowledge of CXL, PCIe, UALink, or Ultra Ethernet. Familiarity with power optimization for high-performance chips. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

About the Company - Silicon Interfaces Silicon Interfaces offers Semiconductor Services for IPs/ASICs/multicore, and our skills and activities are in Functional Verification Methodologies (SV/UVM), Portable Stimulus and cross-platform technique Reuse ( PSS/DSL ), Low Power (UPF), Fault Simulation with AI/ML, and Emulation . These skills and experience have been effectively used in the EDA Industry for Product Support/Product Validation and Regression Testing. You can ask Agent Betsie for information on this and more at our website at www.siliconinterfaces.com You can view the latest demos, tutorials, videos, and PredCast™ on https://www.youtube.com/@SiliconInterfaces and look for the Playlist' Silicon Interfaces Conferences'! Description : Silicon Interfaces is looking for VLSI Design Engineers (strictly 2023 or earlier graduates or Master's 2024) experienced as Team Members and (2+ - 6 Years) Experienced as Team Leads. Job Description : Be a part of a specialized team of Engineers working on SystemVerilog/UVM methodology and on new Technologies projects in Portable Stimulus Standards (PSS) based Domain Specific Language (DSL), Fault Simulation, multi-core processor Verification, and Low Power Designs in Data Communications, Wired and Wireless Networking, as well as Interconnect Technologies. Skills Required: Logic Design, SystemVerilog, UVM and Protocols, like I2C, USB, Ethernet, 802.11, PCI/PCEi, Amba/AXI/CHI, etc. as well as Linux, Gvim/VI, Shell Scripting, Etc Education : BE/B.Tech/ME/M.Tech in Electronics and/or Communications Engineering Tier 1/2 Engineering Colleges - strictly 2023 or earlier graduates or Master's 2024 Silicon Interfaces services a global footprint. Semiconductor Services centers in North America, Europe, and the Asia Pacific by VPN-based logins, in-person Customer site deployment (North America, Europe, and Asia Pacific (including India) and also Offshore projects from our state-of-the-art VLSI Design Centers based out of Mumbai. The Job is based in Mumbai, India, and the company is currently doing WfO (Work from Office), subject to Government and Health Officials' permission. Though Safety is the first priority, the Company has an augmented benefits program, including Health and Life Insurance for all employees. If you like to apply please send resume with Subject and Description of your background and the post you have applied for by email to recruit@siliconinterfaces.com

Principal Staff Verification Engineer (VLSI Verification + AV +AI Expertise) Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. Job Description – Staff Verification Engineer (VLSI Verification + AV +AI Expertise) Position: Staff Verification Engineer – VLSI Verification Lead Location: Hyderabad Experience: 12+ years in Functional Verification Key Protocol Experience: MIPI DSI, DisplayPort, HDMI Role Overview We are seeking a highly skilled Staff Verification Engineer with strong expertise in VLSI functional verification and a good understanding of AI model deployment for Audio/Video applications. The candidate will lead verification efforts for complex SoCs/IPs, while also collaborating with cross-functional teams on next-generation multimedia and AI-driven system use cases. Requirements Experience: 12+ years in functional verification; minimum 5+ years in Multimedia (Display, Camera, Video, Graphics) domain . Domain Expertise: Strong knowledge in Display (Pixel processing, composition, compression, MIPI DSI, DisplayPort, HDMI) and Bus/Interconnect (AHB, AXI). Multimedia technologies: Audio/Video codecs, Image Processing, SoC system use cases (Display, Camera, Video, Graphics). Good understanding of DSP, codecs (audio/video), and real-time streaming pipelines. AI accelerators – architecture understanding, verification, and deployment experience across NPUs, GPUs, and custom AI engines. SoC system-level verification with embedded RISC/DSP processors. AI/ML Skills: Experience with AI models (ex. CNN ) and statistical modeling techniques. Exposure to audio frameworks, audio solutions, and embedded platforms. Hands-on in multimedia use cases verification and system-level scenarios. Strong exposure to MIPI DSI-2, CSI-2, MIPI D-PHY, C-PHY. Verification Expertise: Proven expertise in developing/maintaining SystemVerilog/UVM-based testbenches, UVCs, sequences, checkers, coverage models. Strong understanding of OOP concepts in verification. HVL: SystemVerilog (UVM), SystemC (preferred). HDL: Verilog, SystemVerilog. Leadership & Collaboration: Mentor and guide junior verification engineers; drive closure for IP and SoC-level deliverables. Strong written and verbal communication skills; ability to convey complex technical concepts. Proven ability to plan, prioritize, and execute effectively. Debugging & Architecture Knowledge: Excellent debug skills across SoC architecture, VIP integration, and verification flows. Responsibilities AI & Multimedia (AV) Responsibilities Develop, optimize, and deploy AI models for audio and video applications, with strong focus on inference efficiency and performance optimization across NPUs, GPUs, and CPUs. Perform model evaluation, quantization, and compression to enable fast and robust inference on embedded hardware. Collaborate with cross-functional R&D, systems, and integration teams for system use case verification and commercialization support. Evaluate system performance, debug, and optimize for robustness and efficiency. Participate in industry benchmarking and trend analysis; introduce state-of-the-art architectural and technical innovations. ASIC / SoC Verification Responsibilities Lead and contribute to feature, core, and subsystem verification during ASIC design and development phases through RTL and Gate-Level simulations. Collaborate with the design team to define verification requirements, ensuring functional, performance, and power correctness. Develop and execute comprehensive test plans and drive verification closure. Create and maintain SystemVerilog/UVM testbenches, assertions, and functional coverage models. Implement and enhance automation flows to improve verification efficiency. Participate in debug activities throughout the development cycle. Apply ASIC expertise to define, model, optimize, verify, and validate IP (block/SoC) development for high-performance, low-power products. Collaborate with software and hardware architecture teams to develop strategies meeting system-level requirements. Evaluate complete design flows from RTL through synthesis, place-and-route, timing, and power usage. Write detailed technical documentation for verification methodologies, flows, and deliverables. Contact: Uday Bhaskar Mulya Technologies "Mining the Knowledge Community" Email id : muday_bhaskar@yahoo.com

IP/RTL Design Architect for GPU Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. Position Overview Seeking an IP/RTL Design Engineer with 8+ years of experience to design IP/RTL for GPUs/TPUs, focusing on high-performance matrix multiplication, low-latency interconnects, and power-efficient AI acceleration. Key Responsibilities Design IP blocks for TPU cores, including systolic arrays, vector units, and memory subsystems. Develop Verilog/SystemVerilog RTL for performance, timing, and area optimization. Implement high-speed interconnects (e.g., AXI, NoC) for TPU / /GPU. data pipelines. Optimize designs for high throughput, low latency, and power efficiency in AI workloads. Integrate LPDDR6, HBM3, DDR5, or chiplet-based memory interfaces. Support synthesis, timing closure, and FPGA prototyping and Design Verification team Document microarchitecture and design specifications. Required Qualifications Education: BS/MS in Electrical/Computer Engineering. Experience: 15+ years in ASIC/FPGA IP/RTL design, with 3+ years in AI accelerators or GPU / TPU-like architectures. Skills: Proficient in Verilog/SystemVerilog RTL design. Knowledge of GPU/TPU architectures, systolic arrays, or matrix multiplication units. Experience with AXI, NoC, or similar interconnect protocols. Familiarity with LPDDR6, HBM3, DDR5, or high-bandwidth memory interfaces. Proficiency with synthesis and timing tools (e.g., Synopsys Design Compiler). Strong problem-solving and teamwork skills. Preferred Qualifications Experience with AI/ML workloads or datacenter TPU designs and GPU architectures Knowledge of CXL, PCIe, UALink, or Ultra Ethernet. Familiarity with power optimization for high-performance chips. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Principal Staff Verification Engineer (VLSI Verification + AV +AI Expertise) Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. Job Description – Staff Verification Engineer (VLSI Verification + AV +AI Expertise) Position: Staff Verification Engineer – VLSI Verification Lead Location: Hyderabad Experience: 12+ years in Functional Verification Key Protocol Experience: MIPI DSI, DisplayPort, HDMI Role Overview We are seeking a highly skilled Staff Verification Engineer with strong expertise in VLSI functional verification and a good understanding of AI model deployment for Audio/Video applications. The candidate will lead verification efforts for complex SoCs/IPs, while also collaborating with cross-functional teams on next-generation multimedia and AI-driven system use cases. Requirements Experience: 12+ years in functional verification; minimum 5+ years in Multimedia (Display, Camera, Video, Graphics) domain . Domain Expertise: Strong knowledge in Display (Pixel processing, composition, compression, MIPI DSI, DisplayPort, HDMI) and Bus/Interconnect (AHB, AXI). Multimedia technologies: Audio/Video codecs, Image Processing, SoC system use cases (Display, Camera, Video, Graphics). Good understanding of DSP, codecs (audio/video), and real-time streaming pipelines. AI accelerators – architecture understanding, verification, and deployment experience across NPUs, GPUs, and custom AI engines. SoC system-level verification with embedded RISC/DSP processors. AI/ML Skills: Experience with AI models (ex. CNN ) and statistical modeling techniques. Exposure to audio frameworks, audio solutions, and embedded platforms. Hands-on in multimedia use cases verification and system-level scenarios. Strong exposure to MIPI DSI-2, CSI-2, MIPI D-PHY, C-PHY. Verification Expertise: Proven expertise in developing/maintaining SystemVerilog/UVM-based testbenches, UVCs, sequences, checkers, coverage models. Strong understanding of OOP concepts in verification. HVL: SystemVerilog (UVM), SystemC (preferred). HDL: Verilog, SystemVerilog. Leadership & Collaboration: Mentor and guide junior verification engineers; drive closure for IP and SoC-level deliverables. Strong written and verbal communication skills; ability to convey complex technical concepts. Proven ability to plan, prioritize, and execute effectively. Debugging & Architecture Knowledge: Excellent debug skills across SoC architecture, VIP integration, and verification flows. Responsibilities AI & Multimedia (AV) Responsibilities Develop, optimize, and deploy AI models for audio and video applications, with strong focus on inference efficiency and performance optimization across NPUs, GPUs, and CPUs. Perform model evaluation, quantization, and compression to enable fast and robust inference on embedded hardware. Collaborate with cross-functional R&D, systems, and integration teams for system use case verification and commercialization support. Evaluate system performance, debug, and optimize for robustness and efficiency. Participate in industry benchmarking and trend analysis; introduce state-of-the-art architectural and technical innovations. ASIC / SoC Verification Responsibilities Lead and contribute to feature, core, and subsystem verification during ASIC design and development phases through RTL and Gate-Level simulations. Collaborate with the design team to define verification requirements, ensuring functional, performance, and power correctness. Develop and execute comprehensive test plans and drive verification closure. Create and maintain SystemVerilog/UVM testbenches, assertions, and functional coverage models. Implement and enhance automation flows to improve verification efficiency. Participate in debug activities throughout the development cycle. Apply ASIC expertise to define, model, optimize, verify, and validate IP (block/SoC) development for high-performance, low-power products. Collaborate with software and hardware architecture teams to develop strategies meeting system-level requirements. Evaluate complete design flows from RTL through synthesis, place-and-route, timing, and power usage. Write detailed technical documentation for verification methodologies, flows, and deliverables. Contact: Uday Bhaskar Mulya Technologies "Mining the Knowledge Community" Email id : muday_bhaskar@yahoo.com

If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates. Requisition ID: 74922 Description Responsibilities Work with a dedicated team of engineers, using the latest verification practices, to verify the digital design intent of our SOC's at the block and system level. Engage early in the verification process to understand the verification requirements and participate in UVM or SystemVerilog testbench development. Required Experience And Skills 8+ years (BSEE), 6+ years (MSEE), or 3+ years (PhD) of relevant industry experience Expertise in developing testbenches using System Verilog and UVM Experience using directed and constrained-random test methodologies, coverage closure and gate-level simulations Strong object-oriented programming knowledge using SystemVerilog Strong problem-solving and debug skills capable of isolating problems to the block level Expertise in developing test plans, implementing coverage models, and analyzing results Experience in the use of scripts to support automation (Python, Make, Csh, Bash, Tcl, etc) Familiarity with C-code/embedded firmware/debuggers Ability to work in a dynamic environment with changing needs and requirements Ideally You Are Also Experienced In Using Formal verification methods and tools like Jasper Gold. Real-time data processing systems Audio signal processing Audio performance concepts (SNR, THD, SINAD, DR, etc.) Familiarity with standard interfaces (SPI, I2S, PDM, PWM, USB, etc.) Familiarity with wireless protocols (Wi-Fi, BLE, BT, MAC/PHY) Familiarity with wireless different processors (ARM, HiFi, RISC-V) FPGA hardware emulation Desired Experience And Skills Skyworks is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.

Technical Specialist - Design Verification Large Semiconductor Service Organization with revenue over 600 Million USD Location: Bangalore, Pune, Noida Location: Bangalore, Noida, Pune. Experience: 8–14 Years. About the Role: We are looking for an experienced and passionate Senior Design Verification Engineer to join our team in Bangalore, Pune, Noida. The ideal candidate will have a strong background in pre-silicon verification of complex IPs or SoCs and be capable of leading verification efforts across multiple projects. Key Responsibilities: Lead and contribute to the verification of complex IP blocks or SoC subsystems. Develop test plans, verification strategies, and coverage metrics based on design specifications. Build and maintain constrained-random and directed testbenches using SystemVerilog/UVM. Collaborate with architects, designers, and other verification engineers to identify and debug design issues. Develop and maintain verification infrastructure, scripts, and regression systems. Perform functional and code coverage analysis, driving closure. Provide technical guidance and mentorship to junior team members. Participate in silicon bring-up and post-silicon validation when needed. Required Skills and Qualifications: B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering. 8–14 years of hands-on experience in ASIC/SoC verification. Strong expertise in SystemVerilog, UVM, and RTL simulation tools (e.g., VCS, Questa). Solid understanding of verification methodologies, functional coverage, and assertion-based verification. Experience in developing and maintaining testbenches from scratch. Strong debugging skills and familiarity with waveform viewers like Verdi or DVE. Good knowledge of scripting languages (Python, Perl, or TCL) for automation. Familiarity with version control and CI/CD systems. Preferred Qualifications: Experience in formal verification or emulation is a plus. Familiarity with industry-standard protocols like PCIe, USB, DDR, AMBA (AXI/AHB/APB). Prior experience in leading a verification team or acting as a verification lead. Exposure to post-silicon bring-up and validation. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Technical Specialist - Design Verification Large Semiconductor Service Organization with revenue over 600 Million USD Location: Bangalore, Pune, Noida Location: Bangalore, Noida, Pune. Experience: 8–14 Years. About the Role: We are looking for an experienced and passionate Senior Design Verification Engineer to join our team in Bangalore, Pune, Noida. The ideal candidate will have a strong background in pre-silicon verification of complex IPs or SoCs and be capable of leading verification efforts across multiple projects. Key Responsibilities: Lead and contribute to the verification of complex IP blocks or SoC subsystems. Develop test plans, verification strategies, and coverage metrics based on design specifications. Build and maintain constrained-random and directed testbenches using SystemVerilog/UVM. Collaborate with architects, designers, and other verification engineers to identify and debug design issues. Develop and maintain verification infrastructure, scripts, and regression systems. Perform functional and code coverage analysis, driving closure. Provide technical guidance and mentorship to junior team members. Participate in silicon bring-up and post-silicon validation when needed. Required Skills and Qualifications: B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering. 8–14 years of hands-on experience in ASIC/SoC verification. Strong expertise in SystemVerilog, UVM, and RTL simulation tools (e.g., VCS, Questa). Solid understanding of verification methodologies, functional coverage, and assertion-based verification. Experience in developing and maintaining testbenches from scratch. Strong debugging skills and familiarity with waveform viewers like Verdi or DVE. Good knowledge of scripting languages (Python, Perl, or TCL) for automation. Familiarity with version control and CI/CD systems. Preferred Qualifications: Experience in formal verification or emulation is a plus. Familiarity with industry-standard protocols like PCIe, USB, DDR, AMBA (AXI/AHB/APB). Prior experience in leading a verification team or acting as a verification lead. Exposure to post-silicon bring-up and validation. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Job Overview: In Arm's Solutions Engineering group, our primary focus extends beyond the development of advanced System-on-Chips (SoCs). In the endeavor to deliver quality silicon we need to ensure all our sign-off checks across various domains are diligently performed. Delivering quality silicon leads to quality rewards and every effort and skill is recognized and appreciated at ARM. Our responsibilities also encompass improving methodologies, influencing EDA tools and building a knowledge base which will help with our product design. Learning and sharing knowledge is part of ARM culture and is very much appreciated and encouraged. If you’re interested in working with a team of collaborative and smart engineers in developing silicon that defines the future then, you belong in ARM! Responsibilities Setting up and running Logic Equivalence check which is of signoff quality. Analyzing low power results and signing off on the structural checks run using Conformal Low Power. Provide feedback to relevant teams to ensure successful closure of blocks on time. ECO is part of every silicon now a days and the engineer needs to own up generating functional ECO for quick closure Collaborate with RTL, Synthesis and PnR implementation team to successfully close on different hard macros Work with methodology team to improve the flow Develop automation using python/perl/tcl scripting to avoid repetitive tasks and thus improve your work life balance Supporting and enabling other sign-off team members to attain efficient and quality outcomes Required Skills and Experience: Bachelors/Masters with 3-5 years of minimum experience in Logic Equivalence check (Formality / LEC) and Low power (VCLP / CLP) Values communication as a key medium to nurture learning, builds trust with others and solves sophisticated problems with dependencies. Strong understanding in RTL coding (SystemVerilog, Verilog & VHDL) and RTL for Synthesis Good understanding of the concepts related to Low power synthesis, place & route, DFT. Should be proficient in any of the scripting or automation languages such as Python, Perl, TCL, Sed or Awk. “Nice To Have” Skills and Experience: Working on ARM CPU and GPU designs would be added value Experience working on generating functional ECO using EDA tools will add value In Return: ARM is proud to be an equal opportunity employer. We are committed to fostering a culture of respect, inclusion, and fairness for all. We welcome applications from all individuals, regardless of race, ethnicity, gender, age, disability, sexual orientation, religion, or background. We believe that diverse teams drive innovation, and we work hard to ensure that all our employees can thrive in an environment built on mutual respect and equal opportunity. At ARM, you get to Learn and Innovate! Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodation. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. Hybrid Working at Arm Arm’s hybrid approach to working is centered around flexibility, where we split our time between the office and other locations to get our work done. Within that framework, we empower groups and teams to determine their own particular hybrid working pattern, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Hybrid Working at Arm Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

Job Overview: In Arm's Solutions Engineering group, our primary focus extends beyond the development of advanced System-on-Chips (SoCs). In the endeavour to deliver a quality silicon we need to ensure all our signoff checks across various domains are diligently performed. Delivering quality silicon leads to quality rewards and every effort and skill is recognized and appreciated at ARM. Our responsibilities also encompass improvising methodologies, influencing EDA tools and build a knowledge base which will help in our product design. Learning and sharing knowledge is part of ARM culture and is very much appreciated and encouraged. If your interested in working with a team of collaborative and smart engineers in developing silicon that defines the future then, you belong in ARM! Responsibilities Setting up and running Logic Equivalence check which is of signoff quality. Collaborate with RTL, Synthesis and PnR implementation team to successfully close on different hard macros Work with methodology team to improve the flow Develop automation using python/perl/tcl scripting so as to avoid repetitive task and thus improve your work life balance Supporting and enabling other signoff team members to attain efficient and quality outcomes Required Skills and Experience : Bachelors/Masters with 2 years of minimum experience in Logic Equivalence check (Formality / LEC) Values communication as a key medium to nurture learning, builds trust with others and solves sophisticated problems with dependencies. Strong understanding in RTL coding (SystemVerilog, Verilog & VHDL) and RTL for Synthesis Excellent understanding on fundamental Digital Electronics. “Nice To Have” Skills and Experience : Working on ARM CPU and GPU designs would be added value Having knowledge on Synthesis, DFT and PnR flow will help in doing this role better In Return: ARM is proud to be an equal opportunity employer. We are committed to fostering a culture of respect, inclusion, and fairness for all. We welcome applications from all individuals, regardless of race, ethnicity, gender, age, disability, sexual orientation, religion, or background. We believe that diverse teams drive innovation, and we work hard to ensure that all our employees can thrive in an environment built on mutual respect and equal opportunity. At ARM, you get to Learn and Innovate! Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. Hybrid Working at Arm Arm’s hybrid approach to working is centred around flexibility, where we split our time between the office and other locations to get our work done. Within that framework, we empower groups and teams to determine their own particular hybrid working pattern, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Hybrid Working at Arm Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

Technical Specialist - Design Verification Large Semiconductor Service Organization with revenue over 600 Million USD Location: Bangalore, Pune, Noida Location: Bangalore, Noida, Pune. Experience: 8–14 Years. About the Role: We are looking for an experienced and passionate Senior Design Verification Engineer to join our team in Bangalore, Pune, Noida. The ideal candidate will have a strong background in pre-silicon verification of complex IPs or SoCs and be capable of leading verification efforts across multiple projects. Key Responsibilities: Lead and contribute to the verification of complex IP blocks or SoC subsystems. Develop test plans, verification strategies, and coverage metrics based on design specifications. Build and maintain constrained-random and directed testbenches using SystemVerilog/UVM. Collaborate with architects, designers, and other verification engineers to identify and debug design issues. Develop and maintain verification infrastructure, scripts, and regression systems. Perform functional and code coverage analysis, driving closure. Provide technical guidance and mentorship to junior team members. Participate in silicon bring-up and post-silicon validation when needed. Required Skills and Qualifications: B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering. 8–14 years of hands-on experience in ASIC/SoC verification. Strong expertise in SystemVerilog, UVM, and RTL simulation tools (e.g., VCS, Questa). Solid understanding of verification methodologies, functional coverage, and assertion-based verification. Experience in developing and maintaining testbenches from scratch. Strong debugging skills and familiarity with waveform viewers like Verdi or DVE. Good knowledge of scripting languages (Python, Perl, or TCL) for automation. Familiarity with version control and CI/CD systems. Preferred Qualifications: Experience in formal verification or emulation is a plus. Familiarity with industry-standard protocols like PCIe, USB, DDR, AMBA (AXI/AHB/APB). Prior experience in leading a verification team or acting as a verification lead. Exposure to post-silicon bring-up and validation. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS SILICON DESIGN ENGINEER THE ROLE: The Core design and verification team is responsible for development of High performance and Ultralow power x86 microprocessor core. The role provides a unique opportunity to work at the micro-architectural level of the next-gen Core, with exposure to designs that defines the next wave of client (laptops/ultra-books/think-clients) and custom designs. The multi-billion gate complexity and high-frequency (GHz) design development gives the learning experience of the latest and greatest design and verification methodologies, using cutting edge advanced technology nodes. THE PERSON: Candidates should have solid track record of working on complex designs with hands on experience on architecting and developing test-bench, test-bench components, test-planning and execution of testplan, coverage development and closure. Candidate should have working experience with global teams spread across different geography and time-zones. KEY RESPONSIBILITIES: ASIC design verification experience 6 to 10 years. Verification of high performance x86-core ISA features Architecting and development of testbench, test-bench components for high performance Cache, x86 ISA features, clock/reset/power features of processor. Development of detailed test plans and driving the execution of test plan, including functional coverage. Understanding the existing test bench setup and look for opportunities to improve the existing test bench. Adhering to coding guideline practices, develop and implement code review process. Collaborate with global design verification teams and drive effectively the execution of the verification plans. Your commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion. PREFERRED EXPERIENCE: Strong understanding the design and verification life cycle. Hands on verification experience with C/C++/SystemVerilog testbench development. Hands on experience with coverage planning, coding and coverage closure. Experience with x86, ARM or any other industry standard microprocessor ISA. Experience with Cache, Coherency and Data-Consistency verification. Experience in clocking, reset, power-up sequences and power management verification. Knowledge of microprocessor design-for-debug (DFD) logic will be a plus. Understanding of low power design verification techniques is a plus. ACADEMIC CREDENTIALS: Master's degree preferred with emphasis in Electrical/Electronics Engineering, Computer Engineering, or Computer Science with a focus on computer architecture LOCATION: Hyderabad #LI-RR1 #LI-Hybrid Benefits offered are described: . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ THE ROLE: This role will be part of Silicon Applications and Documentation engineering team in AECG. You will be working with a collaborative team focused on enabling customers to succeed when using ACAP/FPGA. You will have the opportunity to focus on Complex IPs and memory interfaces on the ACAP/FPGA platforms for specialty applications such as image sensors, IOT, emulation etc... In this cross-functional position you will interface directly with Design and Software engineering groups, and you will be the primary interface between the engineering teams and escalated customer support issues. THE PERSON: You are a team player who has excellent communication and writing skills. You have experience communicating effectively and working optimally with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are interested in debugging customer issues and leading complex projects. KEY RESPONSIBILITIES: As a member of this team, you will be responsible for the following: Creating customer documentation (datasheets, architecture manuals, product guides, errata, tutorials) Validating and characterizing memory/IO interfaces and other FPGA key features Building custom designs using Verilog, SystemVerilog or VHDL Resolving escalated customer support issues PREFERRED EXPERIENCE: Excellent written and verbal communication skills. Effective project planning and execution FPGA or ASIC design background Strong background in memory interfaces Experience in Silicon Bring-up and Hardware debug Strong background in RTL development and verification Familiarity with programming/scripting language ACADEMIC CREDENTIALS: Bachelors or Masters degree in Computer Engineering/Electrical Engineering #LI-MK1 Benefits offered are described: . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft’s Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality. We are looking for a Sr Design Verification Engineers to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. The candidate must be a highly motivated self-starter who will thrive in this cutting-edge technical environment. Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond #SCHIEINDIA Responsibilities The AISoC silicon team is seeking a passionate, driven, and intellectually curious computer/electrical engineer to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge, custom IP and SoC designs that can perform complex and high-performance functions in an extremely efficient manner. Plan the verification of complex design IP/SoC interacting with the architecture and design engineers to identify verification test scenarios. Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools Develop tests using UVM or C/C++ Analyse and debug test failures with designers to deliver functionally correct design. Identify and write functional coverage for stimulus and corner cases. Close coverage to plug verification holes and meet tape out requirements. Qualifications 8 or more years of experience in design verification with a proven track record of delivering complex CPU or SoC IP’s In depth knowledge of verification principles, testbenches, stimulus generation, and UVM or C++ based test environments. Solid understanding of computer architecture Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments Scripting language such as Python or Perl Desirable Hands on experience in Formal property verification knowledge in high-speed protocols like DDR, PCIe, Ethernet Processor based testbenches and emulation Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Role Overview: As a Junior ASIC Verification Engineer at Kinara, you will be a key member of the dynamic team responsible for leading and executing verification efforts for complex ASIC designs. Your role will involve developing and maintaining verification plans, testbenches, and test cases to ensure the quality and reliability of our products. You will design and implement SystemVerilog/UVM-based verification environments, create and execute test cases, and write testplans at unit or SOC level. Key Responsibilities: - Develop and maintain verification plans, testbenches, and test cases for ASIC designs. - Design and implement SystemVerilog/UVM-based verification environments. - Create and execute test cases to verify functionality, performance, and compliance with specifications. - Write testplans, testcases at unit or SOC level. Qualifications Required: - Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. - Expertise in SystemVerilog, C, C++ languages. - Experience with verification tools such as VCS, QuestaSim, or similar is helpful. - Excellent problem-solving and debugging skills. - Strong communication and teamwork abilities. Additional Details: Kinara fosters an environment of innovation where technology experts and mentors work together to tackle exciting challenges. The team at Kinara values shared responsibilities and diverse perspectives, making it an ideal place to work. Join us and be a part of our journey towards creating a smarter, safer, and more enjoyable world through high-performance AI solutions embedded in edge devices. Make your mark and become a part of the Kinara team!,

Role Overview: As an experienced SoC Verification Engineer at Enphase Energy in Bangalore, India, you will be working on the next generation Control ASIC in 22nm technology. Your role will involve ensuring the verification of the new SOC design, setting the verification methodology, and collaborating with internal/contract verification resources, IP designers, and Full Chip RTL engineers to verify the RTL developed by Enphase engineers and 3rd party IP. Your deep understanding and experience in SoC architecture and verification will be crucial to the success of the project. Key Responsibilities: - Verify the new SOC design and set the verification methodology - Collaborate with internal/contract verification resources, IP designers, and Full Chip RTL engineers - Ensure verification of RTL developed by Enphase engineers and 3rd party IP - Utilize hands-on experience with UVM using SystemVerilog and coverage-driven verification methods - Apply formal verification methods for IP/SoC functional verification - Demonstrate knowledge of RTL verification methods, gate-level verifications, and mixed signal methodologies - Use specific experience in verifying the ARM CM4 and surrounding IP, such as AHB, AXI, RAM and ROM controllers, and DMA controllers - Apply experience in verifying high-speed and high-accuracy analog systems with a mixed signal methodology - Bring complex SOCs into production Qualifications Required: - At least 15+ years of proven experience in SoC verification - Deep understanding and experience in SoC architecture and verification - Experience with ARM CM4 and surrounding IP like AHB, AXI, RAM and ROM controllers, and DMA controllers - Hands-on experience with UVM using SystemVerilog and coverage-driven verification methods - Knowledge of formal verification methods for IP/SoC functional verification - Familiarity with RTL verification methods, gate-level verifications, and mixed signal methodologies - Ability to bring complex SOCs into production - Hands-on experience with RISC-V verification will be an added advantage (Note: Additional details about the company were not explicitly mentioned in the provided job description.),

**Job Description** **Role Overview:** In this role, you will work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. **Key Responsibilities:** - Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios. - Identify and write all types of coverage measures for stimulus and corner-cases. - Debug tests with design engineers to deliver functionally correct design blocks. - Measure to identify verification holes and to show progress towards tape-out. - Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM). **Qualifications Required:** - Bachelor's degree in Electrical Engineering or equivalent practical experience. - 4 years of experience in Verification, verifying digital logic at RTL level using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or ASICs. - Experience in verification and debug of IP/subsystem/SoCs in the Networking domain such as packet processing, bandwidth management, congestion control desired. - Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems). **About the Company:** The ML, Systems, and Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.,