506 Systemverilog Jobs

Category Engineering Hire Type Employee Job ID 12393 Remote Eligible No Date Posted 29/07/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned engineer with a passion for pushing the boundaries of technology. With 3 -7 years of experience, you bring a wealth of knowledge in software architecture. You excel in C/C++ software development, digital simulation, compiler optimizations and your strong background in design patterns, data structures, and algorithms sets you apart. Your expertise in Verilog, SystemVerilog, coupled with your experience in Unix/Linux platforms, makes you a valuable asset. You are well-versed in developer tools like gdb and Valgrind. Your analytical and problem-solving skills are top-notch, and you are always eager to learn and explore new technologies. As a highly enthusiastic and energetic team player, you are ready to go the extra mile to achieve success. What You’ll Be Doing: - Designing, developing, and troubleshooting core algorithms for compiler. - Collaborating with local and global teams to enhance runtime performance for verilog compiler. - Engaging in pure technical roles focused on software development and architecture. - Utilizing your knowledge of digital simulation flows and EDA tools to drive innovation. - Leveraging your expertise in Verilog, SystemVerilog, and VHDL to develop cutting-edge solutions. The Impact You Will Have: - Driving technological innovation in chip design and verification. - Enhancing the performance and quality of simulation tools used globally. - Solving complex compiler optimizations problems to improve simulation performance. - Collaborating with cross-functional teams to achieve project milestones. - Pioneering new software architectures that set industry standards. What You’ll Need: - Strong hands-on experience in C/C++ based software development. - Deep understanding of design patterns, data structures, algorithms, and programming concepts. - Knowledge of ASIC design flow and EDA tools and methodologies. - Proficiency in Verilog, SystemVerilog, and VHDL HDL. Who You Are: - Highly enthusiastic and energetic team player with excellent communication skills. - Strong desire to learn and explore new technologies. - Effective problem-solver with a keen analytical mind. - Experienced in working on Unix/Linux platforms. - Adept at using developer tools such as gdb and Valgrind. The Team You’ll Be A Part Of: You will be part of the performance team in Digital Simulation. You will work closely with both local and global teams to drive technological advancements and achieve project goals. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: General Summary: Join Qualcomm’s cutting-edge hardware engineering team to drive the design verification of next-generation SoCs, with a focus on wireless technologies including WLAN (IEEE 802.11). You will work on IP and subsystem-level verification, collaborating with cross-functional teams to deliver high-performance, low-power silicon solutions. A strong understanding of on-chip buses and bridges is essential to ensure seamless integration and performance across subsystems. Key Responsibilities: Develop and execute verification plans for complex SoC designs and IP blocks. Architect and implement testbenches using SystemVerilog and UVM/OVM methodologies. Perform RTL verification, simulation, and debugging. Collaborate with design, architecture, and software teams to ensure functional correctness. Contribute to IP design reviews and sign-off processes. Support post-silicon validation and bring-up activities. Analyze and verify interconnects, buses (e.g., AMBA AXI/AHB/APB), and bridges for performance and protocol compliance. Conduct CPU subsystem verification including coherency, cache behavior, and interrupt handling. Perform power-aware verification using UPF/CPF and validate low-power design intent. Execute performance verification to ensure bandwidth, latency, and throughput targets are met. Preferred Skills & Experience: 2–15 years of experience in digital design and verification. Deep understanding of bus protocols and bridge logic, including hands-on experience with AXI, AHB, and APB. Experience with CPU subsystem verification and performance modeling. Familiarity with wireless protocols (IEEE 802.11 a/b/g/n/ac/ax/be) is a plus. Proficiency in SystemVerilog, UVM/OVM, Verilog, and scripting languages (Perl, Tcl, Python). Experience with power-aware verification methodologies and tools (e.g., UPF, CPF). Familiarity with performance verification techniques and metrics. Exposure to tools like Clearcase/Perforce and simulation/debug environments. Strong analytical, debugging, and communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications: Bachelor’s or Master’s degree in Electrical/Electronics Engineering, Computer Science, or related field. Relevant experience in hardware design and verification. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

We are seeking a highly experienced Hardware Verification Engineer with extensive hands-on experience in block-level, IP-level, and SoC-level verification. You will leverage your proficiency in Verilog, SystemVerilog, and UVM-based testbenches, along with knowledge of industry-standard EDA tools, to ensure the robustness and functionality of complex hardware designs. This role requires strong problem-solving and communication skills, and an in-depth understanding of ARM AMBA protocols. Hardware Verification Engineer Roles & Responsibilities: Develop and execute comprehensive verification test plans for block-level, IP-level, and SoC-level designs. Create and maintain efficient UVM-based testbenches . Utilize Verilog and SystemVerilog for testbench development and assertion-based verification. Employ industry-standard EDA tools for simulation and debug to identify and resolve hardware design issues. Verify the functionality and performance of IPs for caches, cache coherency, memory subsystems, interconnects, and NoCs (Networks-on-Chip). Collaborate closely with design teams to understand architectural specifications and ensure verification coverage. Debug complex hardware and software interactions, contributing to root cause analysis. Potentially explore and apply formal verification techniques and emulation platforms . Ensure the quality and reliability of hardware designs prior to tape-out. Qualifications and Preferred Skills: Strong hands-on experience in block-level/IP-level/SOC-level verification . Proficiency in Verilog, SystemVerilog . Familiarity with industry-standard EDA tools for simulation and debug . Deep experience with UVM-based testbenches . Experience with modern programming languages like Python . Knowledge of ARM AMBA protocols such as AXI, APB, and AHB. Understanding of ARM CHI protocol is a plus. Experience on working with IPs for caches, cache coherency, memory subsystems, interconnects and NOCs. Experience with formal verification techniques, emulation platforms is a plus. Excellent problem-solving skills and attention to detail. Strong communication and collaboration skills. QUALIFICATION: BS, MS in Electrical Engineering, Computer Engineering or Computer Science.

You should have experience working with USRP N310/X310 (N3xx/X3x0) and possess a deep understanding of FPGA Architecture. Additionally, you must be proficient in writing your own RTL custom HDL or integrating IP components, including VHDL, Verilog, System Verilog, Vivado HLS, Xilinx IP, and Vivado Block Diagram. It is essential that you have developed RFNoC Blocks and have a good grasp of the USRP Hardware Driver (UHD). Your responsibilities will include creating custom FPGA logic in RFNoC Blocks, utilizing existing RFNoC Blocks library, and understanding the GNU Radio interface to RFNoC Block. Furthermore, you will be involved in FPGA debugging, hardware/software integration, and implementing appropriate coding styles for FPGAs while considering density and speed trade-offs. A thorough knowledge of XILINX ZYNQ 71xx/PL-KINTEX-7 based RFNoC architecture is crucial for this role. You will also be required to comprehend customer requirements, define architecture, and develop detailed designs. Strong communication skills and familiarity with Agile methodology are necessary for effective interaction with customers. In addition to the technical skills, the ideal candidate should hold a Bachelor's degree in Engineering or Technology (B.E./B.Tech.). Please note that we are accommodating a notice period of up to 30 days for this position.,

The job opportunity is based in Bangalore, Karnataka, India, where a new Silicon R&D center is being established. The center aims to pioneer the IPs that will power the digital ASICs for the future mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks, including the Ericsson Radio System - RAN Compute, Radio, and Transport. The goal is to enable communication service providers to exceed the expectations of their end-customers. The design centers aim to lead innovation in the telecommunications sector by leveraging cutting-edge tools and methodologies. As a team member, you will play a crucial role in shaping the future of global connectivity and contributing to the advancement of 5G and 6G technologies. You will have the opportunity to collaborate with talented teams globally, fostering a collaborative and innovative work environment that encourages creativity and teamwork. The work environment prioritizes work-life balance, professional growth, and continuous learning opportunities. The culture values diversity, innovation, and inclusivity. Key Responsibilities: - Participate in the verification of designs at the block or subsystem level. - Define and implement UVM-based test environments. - Contribute to the development and execution of Verification Strategies and Plans. - Develop, run, and debug test cases to ensure design quality. - Optimize verification methodologies and generate documentation. - Collaborate with verifiers, designers, and architects. - Build competence in the technical domain and engage in cross-team collaboration. Required Qualifications: - Bachelor's degree in electrical or computer engineering. - 5+ years of industry experience in verification using SystemVerilog and UVM. - Strong experience in developing verification test plans and test cases, formal verification, and implementing scoreboards and checkers. - Proficiency in SystemVerilog Assertions. Additional Requirements: - Experience with Cadence or Synopsys verification suites. - Team-oriented with strong communication skills. - Attention to detail, commitment to quality, and focus on meeting project deadlines. Preferred Skills: - Understanding of radio access systems and low-power design verification. - Knowledge of continuous integration systems, simulation environments, and issue-tracking tools. - Experience in verification of hardware domains such as AMBA-based designs, ARM-based systems, and digital signal processing systems. Join Ericsson for an outstanding opportunity to push the boundaries of technological possibilities, collaborate with diverse innovators, and craft solutions for the future.,

Eviden, part of the Atos Group, with an annual revenue of circa 5 billion is a global leader in data-driven, trusted, and sustainable digital transformation. As a next-generation digital business with worldwide leading positions in digital, cloud, data, advanced computing, and security, it brings deep expertise for all industries in more than 47 countries. By uniting unique high-end technologies across the full digital continuum with 47,000 world-class talents, Eviden expands the possibilities of data and technology, now and for generations to come. Role: ASIC Verification Engineer Location: Bangalore (Whitefield) Experience: 3+ years Education: Bachelor's Degree (BE / BTech) or Master's Degree (ME / MTech) Verification Engineer integrating ASIC functional verification team. ASIC developed includes network controller, router, and cache coherence controller targeting Bull high-end servers and Bull high-performance ("big data" and "exascale" servers). Using Constraint-Random, Coverage Driven functional verification methodologies underlying UVM verification framework to ensure full and effective verification of complex ASIC. Main Responsibilities Acquire knowledge microarchitecture an ASIC unit by studying the specification and interacting with the logical design team. Write and perform the test plan in close cooperation with the logical design team. Develop coverage models and verification environments using UVM-SystemVerilog / C++. Write, maintain, and publish the verification specification. Monitor, analyze, and debug simulation errors. Monitor and analyze simulation coverage results to improve tests accordingly thereby achieving coverage targets on time. Produce a maintainable and reusable code across projects. Skills And Capacities Curious, demanding, and rigorous. Mastering object-oriented programming. Knowledge of UVM verification methodology (or equivalent) and SystemVerilog / SystemC hardware verification languages. Knowledge of Constraint-Random / Coverage-Driven verification environments development in SystemVerilog / C ++ (drivers / monitors, constraint random tests, checkers, and self-checking models and coverage models written in SystemVerilog-Covergroup / SVA). Knowledge of simulation tools and coverage database visualization tools. Effective in problems solving by rapidly identifying their root cause and developing patches or workarounds under tight timing constraints. #Eviden Let's grow together.,

As a Design Manager at Texas Instruments, you will have the opportunity to lead a team of RTL front end, Digital Back end & Design verification engineers. Your primary responsibilities will include directing and guiding the activities of a research or technical design function, overseeing the design, development, modification, and evaluation of digital electronic parts, components, or integrated circuitry for electronic equipment and hardware systems. You will evaluate the final results of research and development projects to ensure the accomplishment of technical objectives. Additionally, you will be involved in preparing and presenting reports outlining the outcomes of technical projects and making recommendations for actions necessary to achieve desired results. In this role, you will play a key part in selecting, developing, and evaluating personnel to ensure the efficient operation of the function. Joining Texas Instruments as a Design Manager (RTL, P&R, Design Verification) will allow you to work with a team of enthusiastic engineers focused on developing highly complex and industry-leading devices for audio applications. You will be involved in developing new Audio converters catering to PE, Automotive, and Industrial market segments, with the digital content including a DSP for digital filters and audio signal processing blocks among various other IPs. Collaboration with various engineering teams within the product line, including analog design, layout, firmware, verification, validation, test, systems, applications, and marketing, will be a part of your role to successfully execute new products from concept to volume production and subsequent support. As a core member of the design team, you will drive flawless execution by finding innovative design architecture and solutions through out-of-the-box thinking to deliver highly differentiated products. This is an exceptional opportunity to be part of a team that is continuously seeking growth opportunities, working with leading customers globally, and developing cutting-edge solutions in consumer electronics, industrial, and automotive markets. To qualify for this position, you must hold a minimum bachelor's degree in electrical engineering and have at least 7 years of experience. Strong aptitude, hands-on experience in RTL frontend design, excellent command of RTL design concepts, and the ability to work with dynamically evolving requirements are some of the key qualifications needed for this role. You should also possess a result-driven attitude, the ability to mentor team members, and familiarity with digital backend flow and design verification flow. Preferred qualifications for this role include establishing strong relationships with key stakeholders, strong verbal and written communication skills, hands-on experience with Digital Back end tools, and the ability to quickly ramp up on new systems and processes. Demonstrated interpersonal, analytical, and problem-solving skills, ability to collaborate effectively with cross-functional teams, and strong time management skills are also desirable qualities for this position. As a Design Manager at Texas Instruments, you will be responsible for leading a team of 7+ engineers and multiple contractors, driving results while striving for excellence in the complete Digital (Front and Backend) & Design verification team. Your role will also involve overseeing the career growth of your team members. If you are passionate about engineering and shaping the future of electronics, Texas Instruments offers a collaborative environment where employees are empowered to own their career and development. Join us to work with some of the smartest people in the industry and contribute to creating a better world through affordable semiconductor technology. Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company dedicated to designing, manufacturing, and selling analog and embedded processing chips for various markets. Our core passion is to make electronics more affordable through innovative semiconductor solutions. We value diversity and inclusion in our work environment and strive to empower our employees to drive innovation forward. At Texas Instruments, we believe in creating a diverse, inclusive work environment and are an equal opportunity employer. If you are interested in this position, please apply to this requisition.,

The ideal candidate for this role will be an RTL engineer with over 8 years of practical design and verification experience using SystemVerilog UVM and ASIC verification. You should have hands-on experience with Synopsys and/or Cadence simulation tools, as well as proficiency in RTL and possibly Gate level debug. Desirable skills for this position include experience with Synopsys and/or Cadence Synthesis, STA, DFT, Formal Equivalence tools, and familiarity with JIRA. It would be beneficial to have knowledge of scripting languages such as Python or equivalent, understanding of PLLs, and experience with mixed-signal design modelling and debugging. Keywords: UVM, RTL, SystemVerilog, Synthesis, Analog.,

As a Verification Engineer at CoreIC Technologies, located in Bengaluru, you will contribute your expertise in Embedded Display Port (EDP) and DDR protocols to our dynamic team. With a minimum of 6 years of experience, you will play a crucial role in SoC-level verification using C/C++. Your responsibilities will include developing and executing verification plans for EDP and DDR, building and maintaining testbenches and simulation environments, performing functional and regression testing, as well as debugging issues in close collaboration with design and software teams. To excel in this role, you should possess a minimum of 4 years of experience in Design Verification, a deep understanding of EDP & DDR protocols, and proficiency in C/C++ for SoC verification. Exposure to SystemVerilog/UVM is considered an advantage. Strong problem-solving skills and effective communication abilities are essential traits for success in this position. As a qualified candidate, you should hold a B.E./M.E. degree in Electronics or a related field. If you are excited about the opportunity to join our team and contribute to cutting-edge technology developments, please send your resume to Kriti.tripathi@coreictech.com or directly message us. Join us in shaping the future of technology at CoreIC Technologies. #Hiring #VerificationEngineer #DisplayPort #DDR #SoC #VLSIJobs #BangaloreJobs #CoreICTechnologies,

You are an experienced AMS Verification Engineer with over 8 years of expertise in AMS IC verification, possessing hands-on experience in VerilogAMS, SystemVerilog, and UVM. Your strong skills lie in VerilogAMS and Real Number Modeling, and you have a solid understanding of Cadence tools, VManager, and Tcl/Perl. Any knowledge or experience in Analog/RF would be considered a valuable advantage. The location for this position is in Bengaluru. If you believe you are a suitable candidate for this role, we encourage you to reach out by either sending a direct message or sharing your CV to aayushi.sharma@saracasolutions.com. Join us in shaping the future of semiconductors!,

As an experienced professional in ASIC development with a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, you will be leading a team of engineers in Bengaluru to deliver AI/ML compute intensive IPs and subsystems. With 8 years of experience in Verilog/SystemVerilog, VHDL, or Chisel, and 4 years of people management expertise, you will collaborate with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications. Your responsibilities will include taking ownership of complex IPs or subsystems, implementing RTL, and driving design methodology, libraries, debug, and code review in coordination with other IPs Design Verification (DV) teams and physical design teams. Additionally, you will be tasked with identifying and driving power, performance, and area improvements for the domains owned. Your role will involve working on cutting-edge SoCs used to accelerate machine learning computation in data centers. You will be solving technical issues with innovative micro-architecture and practical logic solutions, and evaluating design options with complexity, performance, power, and area in mind. Furthermore, you will contribute to the innovation behind products loved by millions worldwide, leveraging your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. The future of AI/ML hardware acceleration awaits you in this role, where you will have the opportunity to shape cutting-edge TPU technology that powers Google's most demanding AI/ML applications. You will be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. Your contributions will play a crucial role in delivering high-quality designs for next-generation data center accelerators, collaborating with various teams such as architecture, verification, power and performance, and physical design. The Technical Infrastructure team at Google is responsible for the architecture that keeps everything running smoothly online. From data centers to the next generation of Google platforms, this team ensures Google's product portfolio remains at the forefront of innovation. By joining this team, you will play a key role in maintaining networks, ensuring users have the best and fastest experience possible.,

We are seeking an experienced RTL Design Engineer to be a part of our advanced ASIC/SoC development team in Bengaluru. As an RTL Design Engineer, you will be responsible for developing high-quality, synthesizable RTL code using Verilog/SystemVerilog and integrating complex IPs and subsystems into high-performance SoCs. Collaboration with system architects, contribution to micro-architecture, and ensuring design quality through checks like Lint, CDC, and Synthesis will be key aspects of this role. Your responsibilities will include leading SoC-level integration activities, providing technical guidance in design reviews, and interfacing with cross-functional teams for smooth bring-up and signoff processes. The ideal candidate should possess a Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering, along with at least 7 years of experience in RTL design and SoC integration. Strong skills in Verilog/SystemVerilog, knowledge of SoC architecture and bus protocols, and proficiency in industry tools like Design Compiler, Spyglass, and VCS are essential for this role. If you have a deep understanding of clock/reset strategies, hierarchical design practices, timing closure, synthesis flows, and constraints development, along with strong analytical and debugging skills to resolve complex RTL and integration issues, we would like to hear from you. Join us and contribute to the design, integration, and verification of cutting-edge IPs and subsystems within high-performance SoCs.,

As an Electrical Engineer or Computer Science professional with a Bachelor's degree and 3 years of experience in design, multi-power domains with clocking, and SoCs with silicon, you will have the opportunity to contribute to the innovation behind Google's direct-to-consumer products. Your expertise will be crucial in shaping the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Your responsibilities will include defining the microarchitecture of IPs, Subsystems, or SOCs, working with cross-functional teams to ensure quality, schedule compliance, and PPA optimized design. You will collaborate with Verification, Design for Test, Physical Design, and Software teams to make design decisions and represent project status throughout the development process. Additionally, you will define block-level design documents such as interface protocols, block diagrams, transaction flows, and pipelines. You will be responsible for RTL coding for SS/SOC integration, function/performance simulation debug, and Lint/CDC/FV/UPF checks. Working with key design collaterals such as SDC and UPF, you will negotiate the right collateral quality and identify solutions in collaboration with stakeholders. Preferred qualifications include a Master's degree or PhD in Electrical Engineering or equivalent practical experience, experience with chip design flow and cross-domain involving DV, DFT, Physical Design, and software. Experience in STA closure, DV test-plan review, and coverage analysis of the sub-system and chip-level verification will be advantageous. Knowledge in areas such as Processor Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, and Pin-muxing is also beneficial. Join a team that pushes boundaries and works towards developing custom silicon solutions that power the future of Google's products, loved by millions worldwide. Contribute your skills and expertise to create radically helpful experiences by combining the best of Google AI, Software, and Hardware. Be a part of a team that aims to make people's lives better through technology.,

You are a highly experienced ASIC RTL Design Architect responsible for leading the design and verification of cutting-edge SoCs and high-speed digital IPs. With over 10 years of experience in ASIC/FPGA design, your expertise lies in RTL using Verilog/SystemVerilog, Lint, CDC, and Spyglass-based design verification methodologies. Your main responsibilities include leading RTL design and micro-architecture for high-performance ASIC SoCs, ensuring compliance with Lint, CDC, and SDC constraints using Spyglass or equivalent tools, driving design optimization and timing closure, as well as collaborating with cross-functional teams such as Design Verification, DFT, Physical Design, and Software teams. You will also be involved in developing and reviewing architecture specifications, coding guidelines, and best practices, as well as performing synthesis, timing analysis, and static verification using tools like STA, LEC, and Formal Verification. Key requirements for this role include a minimum of 10 years of experience in ASIC RTL design and architecture, expertise in Verilog/SystemVerilog for RTL design, strong knowledge of Spyglass Lint/CDC and static verification methodologies, experience in SoC micro-architecture, high-speed interfaces, and power optimization. Additionally, you should have a solid understanding of synthesis, STA, timing closure, backend constraints, experience with EDA tools like Synopsys, Cadence, Mentor Graphics, and familiarity with UVM-based verification and scripting languages such as TCL, Python, or Perl. Preferred qualifications include an M.Tech/MS/PhD in Electrical Engineering, Computer Engineering, or related field, experience in chip tape-out and production silicon, and an understanding of hardware security, reliability, and safety standards. If you are looking to be part of a team that is shaping the future of high-performance computing, apply now and join us in building innovative solutions together.,

As an ASIC RTL Engineer at Google, you will be part of a team that is dedicated to developing custom silicon solutions to power Google's direct-to-consumer products. Your role will involve contributing to the innovation that drives the creation of products loved by millions worldwide, shaping the next generation of hardware experiences for unparalleled performance, efficiency, and integration. Your responsibilities will include: - Contributing as an ASIC RTL engineer to sub-system and chip-level integration activities. This will involve task planning, conducting code and design reviews, and contributing to sub-system/chip-level integration. - Working closely with the architecture team to develop implementation strategies that meet quality, schedule, and power performance area requirements for sub-system/chip-level integration. - Collaborating with the subsystem team to plan SOC milestones, quality checks, and guide subsystem teams with SOC level requirements such as IPXACT, CSR, Lint, CDC, SDC, UPF, etc. - Engaging with a cross-functional team of verification, design for test, physical design, emulation, and software teams to make design decisions and provide project status updates throughout the development process. To be successful in this role, you should have a Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. You should also have at least 3 years of experience in RTL coding using Verilog or SystemVerilog language, with experience in high-performance design, multi-power domains with clocking. Preferred qualifications include experience with multiple SoCs with silicon success, knowledge of ASIC design methodologies for front quality checks, and domain expertise in areas such as Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, PinMux. Additionally, an understanding of cross-domain activities involving domain validation, design for testing, physical design, and software will be beneficial. Join us at Google and be part of a team that combines the best of Google AI, Software, and Hardware to create radically helpful experiences. Help us research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful, ultimately aiming to make people's lives better through technology.,

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Science or equivalent practical experience. 5 years of experience in coding, developing test methodologies, writing test plans, creating test cases, and debugging. Experience verifying digital logic at RTL level either using SystemVerilog, C, C++. Preferred qualifications: Master's degree in Electrical Engineering or Computer Science or equivalent practical experience. Experience with Interconnect Protocols such as AHB, AXI, ACE, CHI, CCIX, CXL. Experience with performance verification of SOC, Pre-Silicon analysis and post-Silicon correlation. About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Plan and execute the verification of the next generation configurable Infrastructure Intellectual Property (IPs), interconnects and memory subsystems. Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM). Develop cross language tools and verification methodologies. Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct blocks and subsystems. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SILICON DESIGN ENGINEER 2 THE ROLE: As a Silicon Design Engineer, you will work with formal experts and designers to verify formal properties and drive convergence. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Drive formal verification for the block and write formal properties and assertions to verify the design Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the design Write tests, sequences, and testbench components in SystemVerilog and UVM along with formal to achieve verification of the design Responsible for verification quality metrics like pass rates, code coverage and functional coverage PREFERRED EXPERIENCE: Project level experience with design concepts and RTL implementation for same Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics Good understanding of computer organization/architecture ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SG Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Increasing digitalization and flexibility of production processes presents outstanding potential. In Digital Industries, we enable our customers to unlock their full potential and drive digital transformation with a unique portfolio of automation and digitalization technologies. From hardware to software to services, we’ve got quite a lot to offer. How about you? We blur the boundaries between industry domains by integrating the virtual and physical, hardware and software, design and manufacturing worlds. With the rapid pace of innovation, digitalization is no longer tomorrow’s idea. We take what the future promises tomorrow and make it real for our customers today. Join us - where your career meets tomorrow. Looking for Siemens EDA ambassadors We are passionate about innovations that mean real progress, and we are curious about technologies that still need to be developed. Do you want to use curiosity, passion, and creativity to make the lives of millions of people easier and better? Join us – whichever path you take, we’re looking forward to seeing your point of view! Veloce Transactors (Accelerated Verification IPs) Veloce Transactor Group is part of Mentor Emulation Division R&D located in Noida. Group develops transactors (RTL based IPs/VIPs) for various protocol solutions in Networking, Display, Storage, Mobile, Automobile etc. At present Veloce Transactor Library supports more than 25 protocol solution and growing further. This is your Role Individual will be responsible for developing transactor (xVIP) solutions for CCIX or PCIe based interconnect technology. Primary responsibilities include understanding standard specifications, develop architecture and micro-arch for the design and writing a synthesized design using Verilog/System Verilog. Required Experience: We seek a graduate with at 5-8 years of relevant working experience with (BE/BTech/ME/MTech/MS) from a reputed engineering college. We value your experience on the protocol e.g. PCIe, USB, Ethernet, AMBA in Design or Verification. Good understanding of IP Verification Methodologies, Verification procedures and practices are plus! Experience in one or more verification techniques such as simulation, emulation, acceleration, formal, etc We value expertise in Verilog, SystemVerilog, and SystemC, as well as experience in developing RTL for FPGAs, ASICs, and IPs, as this will greatly contribute to the quality of our products. We expect candidates to be able to build verification test plans and environments, develop test cases, utilize VIPs, and efficiently debug defects identified during verification processes. We consider exposure to object-oriented programming languages like C++ an advantage, and experience in scripting languages such as Perl will also be valuable in automating tasks and improving efficiency. You need to engage with customers for Deployment and R&D assistance. We've got quite to offer, how about you? We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. #LI-EDA

Description The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior Design Verification Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge. Work hard. Have fun. Make history. In this role, you will be responsible for defining the verification methodology and implementing the corresponding test plan for sub-systems and the full chip. You will participate in the design verification and bring-up of the chip and subsystems by writing relevant assertions, debugging code, test benches, test harnesses, and otherwise interacting with the extended team. You will participate in the lab bring-up of these blocks either in FPGA, emulation, or silicon by potentially writing test scripts, analyzing lab data, proposing experiments, etc. Role You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware Engineering, and Software Engineering, to architect and implement complex functional block that enable development of world-class hardware devices. In this role, you will: Design world class hardware and software Communicate and work with team members across multiple disciplines Deliver detailed test plans for verification of the full chip or sub-system by working with design engineers and architects Create and enhance constrained-random verification environments using SystemVerilog and UVM Write tests in C to run out of the CPU Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and to show progress towards tape-out. Participate in test plan and coverage reviews The ideal candidate should have experience with RTL development environments, fluency in modern hardware description languages and verification methodologies. They should have experience verifying complex IP blocks from scratch that have successfully been integrated in SOCs or other such silicon that have been productized in consumer devices. We are looking for a self-driven individual who can work with architects, HW and SW developers and can quickly resolve blocking issues. Key job responsibilities Design Verification of Subsystems such as CPU, NPU, and SOC. Drive Verification Methodology using System Verilog / C++ based test benches. Basic Qualifications Bachelor’s degree or higher in EE, CE, or CS 10+ years or more of practical semiconductor design verification experience including System Verilog, UVM, assertions and coverage driven verification. Experience using multiple verification platforms: UVM test bench, FPGA, emulator, software environments and system testing Experience defining verification methodologies Experience with test plan development, building the necessary test bench infrastructure, developing tests and verifying the design Experience with writing directed tests Experience identifying bugs in architecture, algorithms, functionality and performance with strong overall debug skills Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing Experience with industry standard tools and scripting languages (Python or Perl) for automation Understanding and knowledge of object oriented programming concepts Preferred Qualifications PhD in Computer Science, Electrical Engineering, or related field Experience with ARM and various DSP ISA Experience with CPU block level testing Experience debug Company - Amazon.com Services LLC Job ID: A3016320

Cradlepoint is establishing a new Silicon R&D center in Bangalore, and we are looking for a Senior Verifier - ASIC IP to join our pioneering team. You will be instrumental in ensuring the quality and reliability of the IPs that power the digital ASICs for tomorrow's mobile standards, contributing directly to the advancement of 5G and 6G technologies. This role offers the opportunity to work with cutting-edge verification technologies within a collaborative and innovative global R&D environment. What We Offer: Creative Freedom: Immerse yourself in an an environment that champions innovation and critical thinking. You'll have the opportunity to explore advanced verification technologies alongside skilled experts. Global Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. An international work environment with opportunities for professional growth and development. A collaborative and inclusive culture that values diversity and innovation. A competitive compensation and benefits package . What You Will Do: Key Responsibilities Take part in the verification of designs , whether at the block or subsystem level. Participate in defining and implementing UVM-based test environments . Support the creation of Verification Strategies and contribute to the development and execution of Verification Plans . Develop, run, and debug test cases to ensure design quality under supervision. Contribute to the improvement and optimization of verification methodologies . Generate documentation throughout the verification lifecycle. Collaborate closely with other verifiers, designers, and architects . Build competence in the technical domain. Engage in cross-team collaboration to ensure successful project delivery. Required Qualifications: Education: Bachelor's degree in electrical or computer engineering. Experience: 5+ years of industry experience in verification using SystemVerilog and UVM . Additional experience will allow placement at higher job levels. Strong Experience in/with: Development of verification test plans and creation of directed/randomized test cases . Formal verification . Implementing scoreboards, checkers, and bus functional models in an existing testbench environment. SystemVerilog Assertions . Additional Requirements: Experience with Cadence or Synopsys verification suites . Team-oriented , prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality . Strong focus on meeting project deadlines and deliverables . Proficient in English , with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Experience in low-power design verification . Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), and issue-tracking (e.g., Jira). Experience in verification in one or more of the following hardware domains: AMBA-based designs , especially AXI and CHI. ARM-based real-time microcontroller systems , including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces . Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.).

Cradlepoint is establishing a new Silicon R&D center in Bangalore, and we are looking for a Senior Designer - ASIC IP to join our pioneering team. You will be instrumental in developing the IPs that power the digital ASICs for tomorrow's mobile standards, contributing directly to the advancement of 5G and 6G technologies. This role offers the opportunity to work with cutting-edge tools and methodologies within a collaborative and innovative global R&D environment. What We Offer: Creative Freedom: Immerse yourself in an environment that champions innovation and critical thinking. You'll have the opportunity to explore advanced design technologies alongside skilled experts. Global Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. What You Will Do: Key Responsibilities Develop ASIC IP blocks and subsystems , contributing to the advancement of 5G and 6G communication technology. Take full ownership of a design , whether at the block or subsystem level. Generate comprehensive documentation throughout the design lifecycle. Perform digital design and conduct all RTL sign-off checks . Continuously enhance and optimize design methodologies and processes . Collaborate with IP Architects to break down requirements and create detailed IP architecture and design specifications. Work closely with verification engineers to review and refine verification plans. Build competence in the technical domain. Engage in cross-team collaboration to ensure successful project delivery. Required Qualifications: Education: Bachelor's degree in electrical or computer engineering. Industry Experience: Proven industry experience in ASIC design. Strong Experience in/with: Understanding of ASIC technology, design environments, and methodologies . SystemVerilog . RTL static sign-off tools such as SpyGlass. Scripting languages like TCL, Python, or similar. SystemVerilog Assertions . The Skills You Bring: Additional Requirements Experience with Cadence and Synopsys front-end and middle-end design suites . Team-oriented , prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality . Strong focus on meeting project deadlines and deliverables . Proficient in English , with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Expertise in low-power design , including specifying power intent using UPF or similar standards. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), and issue-tracking (e.g., Jira). Experience designing one or more of the following hardware domains: AMBA-based designs especially AXI and CHI. ARM-based real-time microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols . Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.).

As a Lead Verification Engineer with over 7 years of experience, you will be an integral part of a geographically distributed verification team working on next-generation ASIC and FPGAs. Your responsibilities will include developing testplans, implementing testbenches, creating testcases, and ensuring functional coverage closure. Additionally, you will handle regression testing, contribute to verification infrastructure development, and develop both directed and random verification tests. In this role, you will be expected to debug test failures, identify root causes, and collaborate with RTL and firmware engineers to resolve design defects and test issues. You will also review functional and code coverage metrics, modify or add tests, and constrain random tests to meet coverage requirements. Furthermore, you will collaborate closely with design, software, and architecture teams to verify the design under test. The preferred experience for this role includes proficiency in IP-level FPGA and ASIC verification, knowledge of protocols such as PCIe, CXL, or other IO protocols, and proficiency in Verilog/SystemVerilog and scripting languages like Perl or Python. Hands-on experience with SystemVerilog and UVM is mandatory, along with experience in developing UVM-based verification testbenches, processes, and flows. A solid understanding of design flow, verification methodology, and general computational logic design and verification is also essential. About the Company: ACL Digital, a leader in digital engineering and transformation and part of the ALTEN Group, empowers organizations to thrive in an AI-first world. With expertise spanning the entire technology stack and seamlessly integrating AI and data-driven solutions from Chip to cloud, ACL Digital offers a strategic advantage in navigating the complexities of digital transformation. Join us at ACL Digital and be a part of shaping the future as our trusted partner.,

The Core Switch Group (CSG) at Broadcom, the industry leader in cutting-edge networking ASICs, is known for developing advanced protocols and delivering unmatched port density and bandwidth performance. Our team has contributed to iconic switching solutions like the Trident and Tomahawk series, setting benchmarks in the networking world. Broadcom, a global innovator in fabless communications semiconductors, software, and systems, is proud to be recognized as one of Fortune magazine's "Most Admired Companies." We foster a culture that embraces change, values risk-taking, and thrives on tackling the impossible. At Broadcom, we reward innovation and initiative with competitive salaries, industry-leading benefits, and opportunities for growth in an open, collaborative work environment. If you're a passionate engineer eager to shape the future of networking, Broadcom is where you can outdo, outsmart, and outperform. Join us and make an impact! Key Responsibilities: - Conduct detailed studies of chip architecture and micro-architecture to define, develop, and execute comprehensive test plans that thoroughly validate switch features in both emulation phase and post-silicon. - Develop system-level tests using Tcl, ITcl, Python, C/C++ to verify networking switch chips and systems. - Build and Synthesize Verilog based models for emulation platforms such as Zebu or Palladium. - Debugging Expertise: Perform chip/system-level debugging and root cause analysis for hardware and software issues, effectively addressing Pre/Post Silicon issues and challenges. - Automation and Methodology: Develop and optimize automation scripts and emulation methodologies to enhance efficiency, reusability, and value. - Reusable Components: Create reusable synthesizable design blocks, libraries, and verification components to streamline emulation processes. - Silicon Bring-up: Plan, organize, and execute silicon bring-up and test plans. - Environment Management: Create and maintain robust emulation and post-silicon validation environments, supporting a global user community. - Cross-functional Collaboration: Collaborate with Architecture, Micro-Architecture, Design, DV, Software, and other teams to achieve thorough emulation coverage and smooth project execution. What You Bring: - Bachelors with 12+ years in emulation or post-silicon validation of networking ASICs. - Expertise in Verilog/SystemVerilog, C/C++, Tcl, Python, and scripting for automation. - Hands-on experience with emulation platforms (Zebu, Palladium), traffic generators (IXIA, Spirent), and interface protocols (PCIe) is desirable. - Strong debugging skills and familiarity with DPI transactors, assertions, and coverage-driven verification. - Excellent communicator who thrives in a collaborative, fast-paced environment.,

As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. This will involve working on a variety of components including yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to bring cutting-edge products to the market. Collaboration with cross-functional teams is a key aspect of this role to ensure that solutions meet performance requirements. The ideal candidate should have a minimum of 4 to 6 years of work experience in ASIC RTL Design. Experience in Logic design, micro-architecture, and RTL coding is essential. Hands-on experience with the design and integration of complex multi clock domain blocks is a must. Proficiency in Verilog/System-Verilog and knowledge of AMBA protocols such as AXI, AHB, APB, clocking/reset/debug architecture are also required. Candidates should have experience in Multi Clock designs and Asynchronous interface. Familiarity with ASIC development tools like Lint, CDC, Design compiler, and Primetime is necessary. An understanding of Automotive System Designs, Functional Safety, Memory controller designs, and microprocessors would be advantageous. The role involves close collaboration with Design verification and validation teams for pre/post Silicon debug. Prior experience in Low power design is preferred. Additionally, expertise in Synthesis and a solid grasp of timing concepts for ASIC are must-haves for this position.,

Softnautics is seeking a skilled Verification Engineer to join our VLSI group function. As a Verification Engineer at Softnautics, you will play a crucial role in the architecture development, implementation, and documentation of verification IPs. You will be responsible for various tasks including SV/VUM coding, test-plan development, assertion and functional coverage coding, simulations, and more. Additionally, you will have the opportunity to lead a small team and contribute to the overall success of our projects. Responsibilities: - Understanding the standards and specifications relevant to the project - Developing and documenting architecture details - Hands-on involvement in all aspects of the verification cycle - Ensuring compliance with the latest methodologies - Creating Verification IPs - Defining Functional Coverage matrix and Comprehensive Test plan - Managing regression and achieving functional coverage closure - Integrating and verifying Design Under Test (DUT) for IP delivery sign-off - Leading a small team of engineers Required Skills: - Hands-on experience in complete verification cycle with a strong understanding of verification concepts - Proficiency in Verilog, SystemVerilog, and UVM - Experience in UVM based Verification IP development - Familiarity with AMBA AXI/AHB/APB System buses - Hands-on experience with protocols such as PCIe, Ethernet, USB, DDR, etc. - Knowledge of System Verilog Assertions - Proficiency in scripting for automation, release processes, simulations, and regressions - Excellent written and oral communication skills Desired Skills: - Experience in leading Verification IP development with junior engineers - Exposure to the full verification cycle If you are a confident, self-motivated individual with strong fundamentals in verification engineering, we encourage you to apply for this exciting opportunity at Softnautics. Join our team and be a part of a collaborative environment focused on delivering high-quality results.,