850 Systemverilog Jobs - Page 2

**Job Description** **Role Overview:** In this role, you will work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. **Key Responsibilities:** - Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios. - Identify and write all types of coverage measures for stimulus and corner-cases. - Debug tests with design engineers to deliver functionally correct design blocks. - Measure to identify verification holes and to show progress towards tape-out. - Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM). **Qualifications Required:** - Bachelor's degree in Electrical Engineering or equivalent practical experience. - 4 years of experience in Verification, verifying digital logic at RTL level using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or ASICs. - Experience in verification and debug of IP/subsystem/SoCs in the Networking domain such as packet processing, bandwidth management, congestion control desired. - Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems). **About the Company:** The ML, Systems, and Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.,

As a member of the team at Cadence, your role will involve: - Designing and implementing DFT IP with Verilog/SystemVerilog and/or VHDL - Designing and implementing RTL for DFT IP including POST, IST - Developing synthesis automation for DFT IP, which includes synthesis and timing constraints, RTL insertion, and verification - Owning and maintaining, extending, and enhancing existing DFT IP like LBIST At Cadence, you will be part of a team that is focused on doing work that matters and solving challenges that others may find difficult. Join us in making an impact on the world of technology.,

The role This position is a unique opportunity to exercise your hardware verification skills on cutting edge designs within the prestigious PowerVR Hardware Graphics group. Here you will exercise your skills on key components that meet latest demands and improvements for graphics IP. You will: Put in dedicated effort to understand graphics concepts and enhance your verification expertise. Collaborate effectively within a team, demonstrating a willingness to learn and contribute. Take ownership of your tasks by planning, estimating, and tracking your progress. Assist in developing tests, sequences, checkers, scoreboards, and other components in UVM. About You Committed to making your customers, stakeholders and colleagues successful, you’re an excellent communicator, listener and collaborator who builds trusted partnerships by delivering what you say, when you say. You’re curious, solutions orientated and a world-class problem solver who constantly seeks opportunities to innovate and achieve the best possible outcome to the highest imaginable standard. You'll have: Strong expertise in Digital Circuits and Verilog. Proficient in SystemVerilog and UVM, with a strong desire to further enhance skills in these areas. You might also have: Knowledge of Graphics, GPU, CPU, or SoC architectures. Experience with broader verification technologies, including formal property-based verification (FPV). Proficiency in coding and scripting using Python, TCL, Perl, SystemC, or C++. Who We Are Imagination is a UK-based company that creates silicon and software IP designed to give its customers an edge in competitive global technology markets. Its GPU and AI technologies enable outstanding power, performance, and area (PPA), fast time-to-market, and lower total cost of ownership. Products based on Imagination IP are used by billions of people across the globe in their smartphones, cars, homes, and workplaces. We need your skills to help us continue to deliver technology that will impress the industry and our customers alike, ensuring that people everywhere can enjoy smarter and faster tech than ever before. So come join us if you're wanting that something more Bring your talent, curiosity and expertise and we’ll help you do the rest. You’ll be part of one of the world’s most exciting companies who are one of the leaders in semiconductor IP solutions. As a part of our team, you can help us transform, innovate, and inspire the lives of millions through our technology. Additional Information If you encounter accessibility barriers in the application process or if you have access needs and require support or adjustments to participate equitably in the recruitment process, please email recruitment@imgtec.com.

Position : FPGA Verification Engineer Location : Vadodara, Gujarat Experience : 4-6 years Job Summary: We are seeking a skilled and motivated FPGA Verification Engineer with around 5 years of experience in verifying complex FPGA-based designs. The ideal candidate should have a solid foundation in Verilog/SystemVerilog, UVM methodology, and FPGA simulation tools. Experience with Altera, Lattice FPGAs or an interest in contributing to FPGA design tasks is a plus. You will work closely with design, hardware, and software teams to ensure robust and reliable verification of cutting-edge embedded FPGA systems. Key Responsibilities: ● Develop and execute comprehensive verification plans for FPGA designs using Verilog/SystemVerilog. ● Write testbenches and verification environments, including UVM-based testbenches if applicable. ● Perform functional simulation, code coverage, and assertion-based verification. ● Identify, isolate, and debug design and verification issues. ● Collaborate closely with design engineers to validate functional correctness and performance. ● Maintain and improve reusable verification IP and methodologies. ● Document verification results, progress, and issues in a clear and structured manner. ● Stay current with FPGA verification best practices, tools, and methodologies. Requirements: ● Bachelor’s degree in Electrical, Electronics, or Computer Engineering. ● 4–6 years of experience in FPGA verification. ● Strong proficiency in Verilog/SystemVerilog for simulation and testbench development. ● Familiarity with verification tools such as ModelSim, QuestaSim, or Vivado Simulator. ● Experience with Xilinx and/or Intel (Altera) FPGA development environments. ● Solid understanding of digital design fundamentals. ● Proficiency with scripting languages like TCL, Python, or Perl. ● Strong debugging and analytical skills. Preferred Qualifications: ● Experience with UVM (Universal Verification Methodology). ● Exposure to communication protocols like AXI, SPI, I2C, PCIe, Ethernet, etc. ● Experience with Lattice FPGA devices and toolchains (e.g., Lattice Diamond, Radiant).● Willingness and ability to take on FPGA design tasks when required, in case of having experience. ● Familiarity with version control systems (e.g., Git). ● Understanding of embedded systems and co-verification techniques. If you're excited about building next-gen FPGA-based solutions and want to grow in both verification and design, we invite you to join our engineering team. You’ll have the opportunity to work on real-world challenges, contribute across the FPGA development lifecycle, and make a tangible impact.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 1 year of experience with creating/using verification components and environments in UVM methodology at IP or Subsystem level. Experience developing and maintaining design verification (DV) testbenches, test cases, and test environments. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience with image processing, computer vision or machine learning IPs. Experience with AMBA(APB/AXI/ACE) or other standard protocols. Familiarity with CPU, GPU or other computer architectures. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Responsibilities Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation is easy to use. Plan the verification of digital design blocks by understanding design specifications and collaborating with design engineers to identify key verification scenarios. Create and improve constrained-random verification environments using SystemVerilog and UVM. Optionally use SVA and formal tools for formal verification. Perform power-aware simulations and formal verification to validate power management features like clock gating, power gating, and DVFS. Develop and implement power-aware test cases, including stress and corner-case scenarios, for power integrity. Develop and execute coverage-driven verification plans to ensure comprehensive coverage of ASIC designs. Collaborate with design engineers to resolve coverage issues and improve design quality. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

Job Overview Experience: 3 – 15 years Responsibilities Verification engineer with a knowledge of IP verification or SoC integration verification Experience in SoC scenario verification, SoC performance verification, CHI/DDRx/LPDDRx integration verification in SoC RTL. Experience in architecting and implementing SV/UVM testbenches, create and maintain reusable verification components Experience in formal verification strategy for complex IP blocks—defining properties, driving proofs and coverage closure Your key responsibilities will include writing test plans, defining test methodologies, SystemVerilog/Verilog testbench development, developing UVM or C based software tests, and debugging of test failures and issues. Working with project management and leads on planning tasks, schedules, and reporting progress Collaborate with engineers from other teams including architecture, design, implementation, modelling, performance analysis, silicon validation, FPGA and board development Required Skills And Experience Proven understanding of digital hardware verification language Verilog/Systemverilog HDL Experience in SoC verification using Embedded Low-level programming including C/C++ tests and assembly language(preferably ARM) Experienced in one or more of various verification methodologies – UVM/OVM, Formal(jasper), power aware verification, emulation Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case development, documentation, and support Good Problem Solving and Debugging skills. Knowledge of IP or SoC Verification Flow and strategy. Experience with ARM-based designs and/or ARM System Architectures. Porting peripheral driver software Clock Domain Crossing verification Experienced in GLS, DFT/DFD, Experienced in UPF Power Aware verification Experience in embedded operating systems, device drivers, microprocessor and embedded system hardware architectures. Automation experience with shell programming/scripting (g. Tcl, Perl, Python etc.) Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Hybrid Working at Arm Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS SILICON DESIGN ENGINEER (ASIC - SoC Design Verification Lead) The Role The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s custom silicon/ASIC designs, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Key Responsibilities Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 10+ years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills Continuously drive methodology improvements to improve efficiency Mentor junior engineers to build a high performing team PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Work on creating verification plan for RISC-V based application specific IP Build Standalone IP test bench using System Verilog Develop test cases, coverage model and assertions needed to ensure functional correctness of the Design Under Test (i.e., IP/SOC) Use the IP/SOC RTL in system verilog based logic verification environment complete the functional verification Generate functional and code coverage metrics, collaborate with IP developers on the correctness completeness of IP functionality. Deliver the functional test vectors needed to be used for post-silicon validation. Be the single point contact for the concerned IP Verification and enable the Tapeout for all control ASICs of Enphase Who you are and what you bring Proficient in UVM, Verilog, SystemVerilog, C, Python. Working on the HW/SW interface. Strong understanding and experience of logic verification environment (UVM System Verilog) Strong understanding of RISC-V architecture functional verification Experience with processor toolchains (compiler, assembler, simulator). Experience with processor verification. Directed tests and random program generated tests. Experience with functional processor simulators. Experience with verification of secure processor boot code. Experience with Floating point instructions implementation verification in micro controller based ASIC designs Ability to quickly adapt to other categories of C-based/System Verilog based IP verification Experience and ability to bring complex SOCs into the physical world and into production. Excellent problem solving skills, written verbal communication skills Logic Verification #Embedded C Verification #ARM #Boot. Prior hands on work experience of at least 8 years in Logic IP Verification based on System Verilog.

Senior Verification Engineer Bangalore, Karnataka, India Date posted Sep 12, 2025 Job number 1876587 Work site 3 days / week in-office Travel 0-25 % Role type Individual Contributor Profession Hardware Engineering Discipline Silicon Engineering Employment type Full-Time Overview Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft’s Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality. We are looking for a Sr D esign V erification E ngineers to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. The candidate must be a highly motivated self-starter who will thrive in this cutting-edge technical environment. Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond #SCHIEINDIA Qualifications 8 or more years of experience in design verification with a proven track record of delivering complex CPU or SoC IP’s In depth knowledge of verification principles, testbenches, stimulus generation, and UVM or C++ based test environments. Solid understanding of computer architecture Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments Scripting language such as Python or Perl Desirable: Hands on experience in Formal property verification knowledge in high-speed protocols like DDR, PCIe, Ethernet Processor based testbenches and emulation Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Responsibilities The AISoC silicon team is seeking a passionate, driven, and intellectually curious computer/electrical engineer to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge, custom IP and SoC designs that can perform complex and high-performance functions in an extremely efficient manner. Plan the verification of complex design IP/SoC interacting with the architecture and design engineers to identify verification test scenarios. Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools Develop tests using UVM or C/C++ Analyse and debug test failures with designers to deliver functionally correct design. Identify and write functional coverage for stimulus and corner cases. Close coverage to plug verification holes and meet tape out requirements. Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.  Industry leading healthcare  Educational resources  Discounts on products and services  Savings and investments  Maternity and paternity leave  Generous time away  Giving programs  Opportunities to network and connect Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

As a Portable Stimulus (PSS) Verification Lead at Vayavya Labs, you will play a crucial role in understanding customer requirements on system-level verification scenarios and developing test scenarios in PSS language and C or SystemVerilog/UVM. Your responsibilities will include executing test scenarios in pre-silicon and post-silicon environments, as well as debugging the test scenarios. Key Responsibilities: - Understand customer requirements on system-level verification scenarios - Develop test scenarios in PSS language and in C or SystemVerilog/UVM - Execute test scenarios in pre-silicon (simulation, emulation) and post-silicon environments - Debug test scenarios Qualifications Required: - Hands-on experience in C programming for embedded systems - Expertise in pre-silicon validation of system-level scenarios - Experience with verification of controllers for protocols like PCIe, Ethernet, MIPI CSI/DSI - Familiarity with verification on emulator environments Vayavya Labs has been actively contributing to the development and adoption of the PSS standard, making it a leader in the industry. By joining our team, you will have the opportunity to work on Portable Stimulus technologies and develop scenarios for various SoC sub-systems. Additionally, you will receive training on PSS as part of the ramp-up phase. You will also be involved in project planning, effort estimation, technical leadership, and mentoring other team members on PSS. It is essential to have strong analytical and problem-solving skills, excellent communication skills, and a self-managed approach to work. This position offers a great learning opportunity for engineers with experience in system-level verification scenarios and a keen interest in SoC verification technologies. Vayavya Labs is at the forefront of the industry, driving discussions and advancements in Portable Stimulus technologies. If you are eager to take on new challenges and work with cutting-edge verification methodologies, this role is perfect for you.,

In this role at Ambit, you will be responsible for IP / sub-system level micro-architecture development and RTL coding. Your key responsibilities will include: - Prepare block/sub-system level timing constraints - Integrate IP/sub-system - Perform basic verification either in IP Verification environment or FPGA - Deep knowledge of mixed signal concepts - Deep knowledge of RTL design fundamentals - Deep knowledge of Verilog and System-Verilog - Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Power intent, Static Timing Analysis (STA) - Write design specifications for different functional blocks on a chip - Create micro-architecture diagrams of functional blocks - Design functional blocks using System Verilog RTL code - Conduct Synthesis and place and route to meet timing / area goals - Contribute to Design Verification, Synthesis, Power Reduction, Timing Convergence & Floorplan efforts - Code Verilog RTL for high performance designs - Specify, design, and synthesize RTL blocks - Optimize and floorplan them Qualifications required for this position at Ambit include: - B.Tech / M.Tech or equivalent from a reputed University - 5-7 years of relevant experience Join Ambit today for a fulfilling career in semiconductor design services.,

Required Skills & Experience 3 to 5 years of experience in IP/Subsystem/SoC design verification. Strong knowledge in SystemVerilog, UVM , and functional coverage. Understanding of digital design concepts (FSMs, pipelines, FIFOs, memory, clock/reset domains). Experience with protocols like AMBA (AXI/AHB/APB) or similar. Familiarity with assertion-based verification (SVA) . Hands-on with EDA tools (Cadence Xcelium, Synopsys VCS, Mentor Questa, or equivalent). Proficiency in debug tools (Verdi, SimVision, DVE). Strong problem-solving and debugging skills. Scripting skills in Python/Perl/TCL/Makefile for automation. Good to Have (Optional) Exposure to DFT/DFX verification, UPF/power-aware flows, or GLS . Experience with high-speed interfaces (PCIe, USB, DDR, UCIe, etc.) . Familiarity with C/C++/embedded software-driven verification . Role & responsibilities Location: Bangalore Looking for immediate joiners.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS SILICON DESIGN ENGINEER The Role The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience. Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

🚀 We at Scaledge Technology Hiring: VLSI Verification Engineer (PCIe & CXL Expertise) 🚀 Are you a passionate verification engineer with deep expertise in PCIe and CXL protocols? Ready to work on cutting-edge semiconductor technologies? We’re looking for a VLSI Verification Engineer with 5+ years of experience to join our high-impact team! 🔧 Role Responsibilities: *) Develop and execute verification plans for high-speed interface IPs (PCIe/CXL) *) Work with SystemVerilog, UVM, and industry-standard simulation tools Collaborate with architecture and design teams to ensure functional correctness *) Debug and resolve complex issues in simulation and emulation environments 🎯 What You Bring: *) Strong hands-on experience in protocol-level verification of PCIe and/or CXL *) Proficiency in SystemVerilog, UVM, and scripting languages *) Familiarity with assertion-based verification, coverage analysis, and debug tools *) Excellent problem-solving and communication skills 📍 Location: Pune 📧 Apply Now: nupur.dodake@scaledge.io

As an Electrical Engineer with 4 years of experience in Verification, you will play a crucial role in shaping the future of AI/ML hardware acceleration. Your responsibilities will include driving cutting-edge TPU (Tensor Processing Unit) technology for Google's demanding AI/ML applications. You will be part of a dynamic team that focuses on developing custom silicon solutions to power Google's TPU, contributing to innovative products loved by millions worldwide. Your key responsibilities will involve: - Planning the verification of digital design blocks and collaborating with design engineers to identify critical verification scenarios. - Identifying and implementing various coverage measures for stimulus and corner-cases to ensure thorough verification. - Debugging tests with design engineers to ensure the delivery of functionally correct design blocks. - Creating a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM). Preferred qualifications for this role include a Master's degree in Electrical Engineering or a related field, experience with industry-standard simulators and regression systems, as well as familiarity with AI/ML Accelerators or vector processing units. Excellent problem-solving and communication skills will be essential for success in this role. About the company: The ML, Systems, and Cloud AI (MSCA) organization at Google focuses on designing, implementing, and managing hardware, software, machine learning, and systems infrastructure for all Google services and Google Cloud. With a commitment to security, efficiency, and reliability, the organization drives innovation in hyperscale computing, including Google Cloud's Vertex AI platform. In this role, you will have the opportunity to own the full verification life-cycle, from planning and test execution to coverage closure, with a specific emphasis on meeting stringent AI/ML performance and accuracy goals. By collaborating closely with design and verification engineers, you will contribute to verifying complex digital designs, particularly focusing on TPU architecture integration within AI/ML-driven systems.,

Minimum qualifications: Bachelor's degree in Electrical Engineering or equivalent practical experience. 1 year of experience with verification methodology such as Universal verification methodology (UVM). 1 year of experience in the verification of IP designs such as IP, SoC, vector CPUs, etc. Experience with SystemVerilog, SVA, and functional coverage. Preferred qualifications: Master's degree in Electrical Engineering or a related technical field. Experience with industry-standard simulators, revision control systems, and regression systems. Experience with the full verification life-cycle. Experience in Artificial Intelligence/Machine Learning (AI/ML) Accelerators or vector processing units. Excellent problem-solving and communication skills. About The Job In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will own the full verification life-cycle from verification planning and test execution to coverage closure, with an emphasis on meeting stringent AI/ML performance and accuracy goals, build constrained-random verification environments capable of exposing corner-case bugs and ensuring the reliability of Artificial Intelligence/Machine Learning (AI/ML) workloads on Tensor Processing Unit (TPU) hardware. You will collaborate closely with design and verification engineers in active projects and perform verification. The ML, Systems, and Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Responsibilities Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios. Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct design blocks. Measure to identify verification holes and to show progress towards tape-out. Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM). Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

Agnisys is looking for freshers to join our team to work on high tech products for the Semiconductor industry. Agnisys is a leader in automating SoC development. It’s products are considered to be the most comprehensive and best in class. We offer a progressive, innovations-driven, learning environment. Don’t get pigeon-holed into one specific area when you can learn the intricacies of Design, Verification, Firmware and overall chip design all at one company! Not only that, you will be exposed to Product Validation, Customer Support and an Agile development environment. Agnisys focuses on research and development by participating in Accellera Systems Initiative, presenting in worldwide conferences, encouraging creative thinking and initiative. So if you value innovation and creativity and want to create a strong foundation for your career, join Agnisys today. Basic Requirements: Candidates should be B.Tech.CS & MCA freshers/graduate Basic Knowledge in Verilog, VHDL, SystemVerilog & C FPGA, EDA Tools, Linux, Perl, Python, Tcl, Bash scripting Should have excellent communication skills Ability to work independently with little supervision as well as ability to work within a team Excellent multi-tasking skills Self-motivated with strong team spirit Job Type: Full-time Pay: ₹22,000.00 - ₹22,001.00 per month Benefits: Health insurance Internet reimbursement Work Location: In person

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SILICON DESIGN ENGINEER 1 The Role As a Silicon Design Engineer, you will work with formal experts and designers to verify formal properties and drive convergence. The Person You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Key Responsibilities Drive formal verification for the block and write formal properties and assertions to verify the design Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the design Write tests, sequences, and testbench components in SystemVerilog and UVM along with formal to achieve verification of the design Responsible for verification quality metrics like pass rates, code coverage and functional coverage Preferred Experience Project level experience with design concepts and RTL implementation for same Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics Good understanding of computer organization/architecture Academic Credentials Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Enphase Energy is a global energy technology company and a leading provider of solar, battery, and electric vehicle charging products. Since its establishment in 2006, Enphase has been at the forefront of innovation in solar power, enhancing its safety, reliability, and scalability. With the Enphase Energy System, individuals can generate, utilize, store, and even sell their own power. The company has a remarkable global presence, having shipped over 80 million products to 160 countries. In this role at Enphase, you will be part of a dynamic team focused on designing and developing next-generation energy technologies to contribute towards a sustainable future. The position requires your presence onsite for 3 days a week initially, with a plan to transition back to a full 5-day in-office schedule gradually. As an experienced SoC Verification engineer, you will join the Enphase team in Bangalore, India, contributing to the development of the next generation Control ASIC in 22nm technology. This ASIC incorporates the ARM CM4 core, necessitating expertise in this core. The SOC integrates safety and security features, demanding a comprehensive understanding of these SoC challenges. The Control ASIC includes various components such as the CPU, Analog Front End (AFE), Power Line Communications Modem (PLC), proprietary Power Production control block, and other peripherals. Reporting to the Senior Director of ASIC Engineering in Bangalore, you will collaborate with internal/contract verification resources, IP designers, and Full Chip RTL engineers to verify the new SOC design. Your responsibilities will involve defining the verification methodology and verifying the RTL developed by Enphase engineers and 3rd party IP. The ideal candidate for this role possesses: - Deep understanding and experience in SoC architecture and verification - Specific experience in verifying the ARM CM4 and associated IP like AHB, AXI, RAM and ROM controllers, and DMA controllers - Hands-on experience with RISC-V verification (preferred) - Proficiency in UVM using SystemVerilog, Coverage driven verification methods, and formal verification methods for IP/SoC functional verification - Knowledge of RTL verification methods, Gate-level verifications, and mixed-signal methodologies - Experience in bringing complex SOCs into production To be considered for this position, you should have a proven track record with at least 15+ years of experience in the field. Join Enphase Energy in shaping the future of energy technology and playing a significant role in building a sustainable future.,

You are an experienced ASIC Verification Engineer with more than 12 years of experience, seeking a challenging opportunity to utilize your expertise in PCIe interface protocols. You will be responsible for delivering high-quality RTL and simulation models, developing verification plans, and test environments at IP and/or SoC level. Your proactive problem-solving mindset will be crucial in tackling complex design and verification challenges. Additionally, you will lead verification teams, mentor junior engineers, and engage with customers to ensure smooth execution. The ideal candidate for this role possesses strong hands-on expertise in PCIe verification at the IP or SoC level, along with proven experience in working with UVM-based test benches and complex verification environments. Your ability to work collaboratively in fast-paced environments, while maintaining a focus on quality, innovation, and technical leadership, will be highly valued in this position.,

You are seeking a Manager Digital Design with a robust background in RTL design and Design Verification (DV). As an ideal candidate, you will be a techno-functional manager actively involved in design/verification tasks, overseeing a mid-to-large engineering team of approximately 30 members. This role entails close coordination across various projects to ensure delivery excellence and promote technical best practices. The position is based in Hyderabad (Preferred) or Bangalore (Optional). Key Responsibilities - Managing and guiding a digital design & DV team of over 30 members across multiple projects. - Supervising RTL design, micro-architecture, verification planning, and execution. - Offering hands-on technical guidance to address design/verification challenges. - Driving project planning, execution, and monitoring to meet delivery timelines. - Collaborating with cross-functional teams including Physical Design, Analog/Mixed Signal, Architecture, and Software. - Ensuring compliance with Performance, Power, Area (PPA), and quality objectives. - Enhancing the team's capabilities by mentoring engineers. - Supporting customer reviews, project audits, and internal reporting. Required Skills & Experience - 12+ years of experience in Digital Design (RTL/DV). - Proficiency in SystemVerilog, UVM, and verification methodologies. - Hands-on expertise in RTL design, coding, and functional verification. - Demonstrated ability to lead teams of over 30 engineers in complex ASIC/SoC projects. - Sound knowledge of design flows, low-power design, and verification techniques. - Strong project management skills enabling tracking and delivery of multiple engagements. - Excellent communication skills for effective cross-team and customer interaction.,

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SoC Verification ENGINEER THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP/Sub-System/SOC level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Processor Micro-Architecture concepts – Reset/Boot-flow/Cache Coherency/Interrupt flows knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience. Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR5 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

💻 Work From Remote – Design Verification Experts 🔹 Role: Design Verification Engineers 🔹 Experience: 8 to 16 years 🔹 Availability: 0–30 days notice 🔹 Mode: Remote ✨ Job Description: Strong knowledge of verification flows Excellent debugging skills and problem-solving attitude Experience with complex test-benches/models in Verilog, SystemVerilog, or SystemC Hands-on with Functional Verification, SoC Verification, Emulation Proficiency in SystemVerilog, PLI/DPI, C/C++, PERL/Shell scripting, assembly Knowledge of OVM/UVM Methodology Strong communication & teamwork skills Preferably with x86 or ARM SoC verification experience Background in SoC/IP performance verification is a plus 📩 Share resumes: swarnamanjari@mirafra.com 👥 Referrals are highly appreciated!

Join our ambitious team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our mission is to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You will have the opportunity to work on groundbreaking products and collaborate with talented hardware and software engineers to create disruptive infrastructure solutions that excite our customers. We are seeking talented engineers experienced in physically implementing large-scale networking and computing semiconductor products. You will be part of a dynamic startup environment and contribute to the full lifecycle of complex chip development, from CAD tool flow setup to physical verification and tapeout. This role is based in India, with options for hybrid/remote work. Candidates capable of in-office participation in Hyderabad or Bangalore are preferred. Responsibilities: - Develop and maintain the CAD tool flow for physical implementation in a cloud-first environment. - Collaborate with architects on chip-level floorplan and block partitioning, considering tradeoffs in functional partitioning and interface complexity. - Design major physical structures like clock architecture, power delivery network, and interconnect topologies. - Execute physical implementation at block, cluster, and top levels, including synthesis, floorplan, timing closure, and tapeout. - Liaise with foundry and library partners on 3rd party IP integration and process technology issues. Skills/Qualifications: - Proven track record in physical implementation of high-performance network switching/routing fabrics, NICs, CPUs, or GPUs in the latest silicon process nodes. - Proficiency in CAD tools like Cadence Genus, Synopsys ICC2, and analysis tools such as Redhawk. - Experience with scripting languages like Perl, Python, and SystemVerilog. - Minimum BSEE/CE + 10 years or MSEE/CE + 5 years experience with products shipped in high volume. Company Background: We are a well-funded startup based in Mountain View, CA, founded by industry veterans and backed by top-tier investors. Our diverse team excels in co-designing hardware/software solutions and has a proven track record in processing global data center traffic. Note: The above job description is based on the mentioned details in the provided job description.,

You will be responsible for managing and guiding a 30+ member digital design & DV team across multiple projects. Your role will involve overseeing RTL design, micro-architecture, verification planning, and execution. You are expected to provide hands-on technical guidance to resolve design/verification challenges and drive project planning, execution, and tracking to meet delivery schedules. Collaboration with cross-functional teams such as Physical Design, Analog/Mixed Signal, Architecture, and Software is essential. Ensuring adherence to PPA (Performance, Power, Area) and quality targets, as well as building and strengthening the team's capability through mentoring engineers will be part of your key responsibilities. Additionally, you will support customer reviews, project audits, and internal reporting. The ideal candidate for this position should have at least 12 years of experience in Digital Design (RTL/DV) and possess a strong expertise in SystemVerilog, UVM, and verification methodologies. Hands-on experience in RTL design, coding, and functional verification is required. A proven ability to manage teams of 30+ engineers in complex ASIC/SoC projects, along with a solid understanding of design flows, low-power design, and verification techniques, is crucial. Strong project management skills, including the ability to track and deliver multiple engagements, are necessary. Excellent communication skills are also essential for effective cross-team and customer interaction. This position is located in Hyderabad (Preferred) or Bangalore (Optional).,