Enfabrica

Enfabrica is at the forefront of building cutting edge networking silicon and system software to drive the revolution in AI and accelerated computing infrastructure at scale. We are seeking a hands-on Team Lead to drive the development of tools, automation, and infrastructure critical to validating high-performance networking ASICs. This role combines technical ownership of validation infrastructure with a functional leadership of our silicon validation team in the India region. You will architect scalable test environments and automation frameworks while guiding and coordinating validation engineers across projects. This position is ideal for a senior engineer who leads by example, mentors others, and drives execution excellence across both technology and people. Key Responsibilities Design and implement automation frameworks, test benches, and validation infrastructure using Python, C++, and industry-standard tools Build and maintain CI/CD pipelines and regression systems to support scalable and repeatable validation workflows Act as the technical lead for validation tools and infrastructure, enabling cross-site alignment and tool reuse Provide functional leadership for the silicon validation team in the India geo, including task planning, progress tracking, and performance feedback Remain deeply hands-on: develop test content, debug complex system issues, and lead root-cause analysis efforts Collaborate with design, DV, firmware, and software teams to ensure comprehensive test coverage and effective debug strategies Develop and apply debug methodologies using logs, protocol traces, and signal analysis tools Promote a culture of engineering excellence, technical documentation, and continuous improvement Qualifications Education & Experience BSc, MSc, or PhD in Electrical or Computer Engineering 7+ years of experience in post-silicon validation in microprocessors, networking, or high-speed interconnect products, with demonstrated ownership of test infrastructure and automation systems 2+ years in a technical leadership or geo/site lead role, combining engineering execution with team coordination Required Technical Strengths Proficient in Python and C++ Proven experience in designing and scaling validation frameworks and automation platforms Solid understanding of one or more of the following protocols: PCIe (Gen5/Gen6), CXL, Ethernet (MAC/PHY), RDMA/RoCE Preferred Technical Strengths Skilled in lab equipment: oscilloscopes, logic analyzers, protocol analyzers, BER testers Leadership & Mentorship Strong mentoring skills with the ability to grow junior engineers while delivering on team goals Experienced in managing and aligning geographically distributed engineering efforts Effective communicator across cross-functional teams including architecture, design, and firmware Self-driven, accountable, and thrives in fast-paced, high-impact environments Success Metrics Innovate and establish scalable, quality-driven, and cost-effective test infrastructure—measured by a leading low ratio of validation workforce to front-end design (Architecture, Design, and Design Verification) Continuously improve validation efficiency, coverage, and issue resolutions Deliver validation milestones consistently and on time, with minimal bugs surfacing post-hardware qualification Build a technically strong, self-directed validation team with clear ownership and disciplined execution About Us: Enfabrica is on a mission to revolutionize AI compute systems and infrastructure at scale through the development of superior-scaling networking silicon and software which we call the Accelerated Compute Fabric. Founded and led by an executive team assembled from first-class semiconductor and distributed systems/software companies throughout the industry, Enfabrica sets themselves apart from other startups with a very strong engineering pedigree, a proven track record of delivering, deploying and scaling products in data center production environments, and significant investor support for our ambitious journey! Together, with their differentiated approach to solving the I/O bottlenecks in distributed AI and accelerated compute clusters, Enfabrica is unleashing the revolution in next-gen computing fabrics. Powered by JazzHR SPUPSyk5w4 Show more Show less

Enfabrica is at the forefront of building cutting-edge networking silicon and system software to drive the revolution in AI and accelerated computing infrastructure at scale. As we transition into the post-silicon phase, we are seeking dynamic Technical Experts and Leaders who thrive in multidisciplinary environments, balancing hands-on development, testing, debugging, mentoring, and project leadership. Our mission is to establish a modern, scalable, high-quality silicon validation methodology and operation that ensures efficiency and reliability across diverse AI workloads and customer use cases. As a Silicon Validation Engineer, you will be responsible for post-silicon validation of high-performance networking ASICs involving Ethernet, RDMA/RoCE, InfiniBand (IB), PCIe, CXL, and Network-on-Chip (NoC) architectures. You will work closely with design, firmware, software, and architecture teams to ensure the silicon meets performance, reliability, and compliance requirements before production deployment. Qualifications: We recognize that not all candidates will possess every skill listed, but these represent the key capabilities we seek: Education & Experience: - BSc/MSc/PHd in Electrical or Computer Engineering, preferably with 5+ years of post-silicon validation experience - Strong expertise in high-speed networking (Ethernet, RDMA/RoCE, IB) and interconnects (PCIe Gen5/Gen6, CXL) Technical Expertise: - Silicon Debug & Validation: Bring-up, functional testing, stress/margin testing, and performance validation - High-Speed Protocols: PCIe, CXL, RDMA, Ethernet MAC/PHY, congestion control algorithms - Debug Tools: Protocol analyzers, oscilloscopes, logic analyzers, BER testers - Scripting & Automation: Proficiency in Python for test automation, data analysis, and validation frameworks - CI/CD & Test Infrastructure: Experience with automating validation pipelines and regression testing Soft Skills: - Strong problem-solving and debugging skills - Ability to collaborate across De, DV, firmware, and system teams - Proactive, action-driven executor with a results-oriented mindset Success Metrics: - Seamless silicon bring-up & debugging - Optimized Validation of networking & interconnect protocols - Rapid identification and resolution of silicon and system-level issues - Minimal post-production silicon bugs - Bottom-line impact: Delivering a robust, high-quality product that meets customer expectations and performs flawlessly in real-world deployments About Us: Enfabrica is on a mission to revolutionize AI compute systems and infrastructure at scale through the development of superior-scaling networking silicon and software which we call the Accelerated Compute Fabric. Founded and led by an executive team assembled from first-class semiconductor and distributed systems/software companies throughout the industry, Enfabrica sets themselves apart from other startups with a very strong engineering pedigree, a proven track record of delivering, deploying, and scaling products in data center production environments, and significant investor support for our ambitious journey! Together, with their differentiated approach to solving the I/O bottlenecks in distributed AI and accelerated compute clusters, Enfabrica is unleashing the revolution in next-gen computing fabrics.,

You are an experienced Rust Software Engineer with a background in low-level firmware development, Linux systems, and board support, joining our team. Your responsibilities include designing, developing, and maintaining firmware for in-house PCBs, collaborating with hardware engineers, and ensuring seamless integration and performance. You will design, implement, and maintain low-level firmware for custom PCBs using Rust. Additionally, you will develop and optimize drivers for various hardware components, collaborate with hardware engineers, work with Linux systems, develop kernel drivers, debug and troubleshoot hardware and software issues, write comprehensive documentation, participate in code reviews, and contribute to firmware development best practices. Qualifications: - Bachelor's degree in Computer Science, Electrical Engineering, or related field. - Proven experience in Rust programming for low-level systems or embedded development. - Strong understanding of Linux systems and their interaction with firmware. - Experience in developing and optimizing drivers for hardware components. - Proficiency in debugging tools and techniques. - Strong problem-solving skills, attention to detail, and communication skills. Preferred Qualifications: - Experience with other systems programming languages. - Familiarity with embedded systems and microcontroller architectures. - Experience with embedded or real-time operating systems. - Knowledge of version control systems. - Experience with Bazel build tooling is a plus. Join us at Enfabrica, where we are revolutionizing AI compute systems and infrastructure with our Accelerated Compute Fabric. With a strong engineering pedigree and a proven track record, we are unleashing the revolution in next-gen computing fabrics.,

Design and implement automation frameworks, test benches, and validation infrastructure using Python, C++, and industry-standard tools. Build and maintain CI/CD pipelines and regression systems to support scalable and repeatable validation workflows. Act as the technical lead for validation tools and infrastructure, enabling cross-site alignment and tool reuse. Provide functional leadership for the silicon validation team in the India geo, including task planning, progress tracking, and performance feedback. Remain deeply hands-on: develop test content, debug complex system issues, and lead root-cause analysis efforts. Collaborate with design, DV, firmware, and software teams to ensure comprehensive test coverage and effective debug strategies. Develop and apply debug methodologies using logs, protocol traces, and signal analysis tools. Promote a culture of engineering excellence, technical documentation, and continuous improvement. Qualifications Education Experience BE/B.Tech in Electrical or Computer Engineering. 7+ years of experience in post-silicon validation in microprocessors, networking, or high-speed interconnect products, with demonstrated ownership of test infrastructure and automation systems. 2+ years in a technical leadership or geo/site lead role, combining engineering execution with team coordination. Required Technical Strengths Proficient in Python and C++. Proven experience in designing and scaling validation frameworks and automation platforms. Solid understanding of one or more of the following protocols: PCIe (Gen5/Gen6), CXL, Ethernet (MAC/PHY), RDMA/RoCE. Preferred Technical Strengths Skilled in lab equipment: oscilloscopes, logic analyzers, protocol analyzers, BER testers. Leadership Mentorship Strong mentoring skills with the ability to grow junior engineers while delivering on team goals. Experienced in managing and aligning geographically distributed engineering efforts. Effective communicator across cross-functional teams including architecture, design, and firmware. Self-driven, accountable, and thrives in fast-paced, high-impact environments.

Please review our open positions and apply to the positions that match your qualifications. Enfabrica is at the forefront of building cutting edge networking silicon and system software to drive the revolution in AI and accelerated computing infrastructure at scale. As we transition into the post-silicon phase, we are seeking dynamic Technical Experts and Leaders who thrive in multidisciplinary environments, balancing hands-on development, testing, debugging, mentoring, and project leadership. Our mission is to establish a modern, scalable, high-quality silicon validation methodology and operation that ensures efficiency and reliability across diverse AI workloads and customer use cases. As a Silicon Validation Engineer, you will be responsible for post-silicon validation of high-performance networking ASICs involving Ethernet, RDMA/RoCE, InfiniBand (IB), PCIe, CXL, and Network-on-Chip (NoC) architectures. You will work closely with design, firmware, software, and architecture teams to ensure the silicon meets performance, reliability, and compliance requirements before production deployment. Qualifications We recognize that not all candidates will possess every skill listed, but these represent the key capabilities we seek: BSc/MSc/PHd in Electrical or Computer Engineering, preferably with 5+ years of post-silicon validation experience. Strong expertise in high-speed networking (Ethernet, RDMA/RoCE, IB) and interconnects (PCIe Gen5/Gen6, CXL).

Lead Engineer Silicon Validation Tools & Infrastructure (India) - Enfabrica - Career Page Thanks for visiting our Career Page. We develop groundbreaking hardware, software, and system technologies that solve the critical bottlenecks in next-generation computing workloads - at any scale - across hyperscale cloud, edge, enterprise, 5G/6G, and automotive infrastructure. Please review our open positions and apply to the positions that match your qualifications. is at the forefront of building cutting edge networking silicon and system software to drive the revolution in AI and accelerated computing infrastructure at scale. We are seeking a hands-on Team Lead to drive the development of tools, automation, and infrastructure critical to validating high-performance networking ASICs. This role combines technical ownership of validation infrastructure with a functional leadership of our silicon validation team in the India region. You will architect scalable test environments and automation frameworks while guiding and coordinating validation engineers across projects. This position is ideal for a senior engineer who leads by example, mentors others, and drives execution excellence across both technology and people. Key Responsibilities Design and implement automation frameworks, test benches, and validation infrastructure using Python, C++, and industry-standard tools. Build and maintain CI/CD pipelines and regression systems to support scalable and repeatable validation workflows. Act as the technical lead for validation tools and infrastructure, enabling cross-site alignment and tool reuse. Provide functional leadership for the silicon validation team in the India geo, including task planning, progress tracking, and performance feedback. Remain deeply hands-on: develop test content, debug complex system issues, and lead root-cause analysis efforts. Collaborate with design, DV, firmware, and software teams to ensure comprehensive test coverage and effective debug strategies. Develop and apply debug methodologies using logs, protocol traces, and signal analysis tools. Promote a culture of engineering excellence, technical documentation, and continuous improvement. Qualifications BE/B.Tech in Electrical or Computer Engineering. 7+ years of experience in post-silicon validation in microprocessors, networking, or high-speed interconnect products, with demonstrated ownership of test infrastructure and automation systems. 2+ years in a technical leadership or geo/site lead role, combining engineering execution with team coordination. Required Technical Strengths Proficient in Python and C++. Proven experience in designing and scaling validation frameworks and automation platforms. Solid understanding of one or more of the following protocols: PCIe (Gen5/Gen6), CXL, Ethernet (MAC/PHY), RDMA/RoCE. Preferred Technical Strengths Skilled in lab equipment: oscilloscopes, logic analyzers, protocol analyzers, BER testers. Strong mentoring skills with the ability to grow junior engineers while delivering on team goals. Experienced in managing and aligning geographically distributed engineering efforts. Effective communicator across cross-functional teams including architecture, design, and firmware. Self-driven, accountable, and thrives in fast-paced, high-impact environments. Innovate and establish scalable, quality-driven, and cost-effective test infrastructure measured by a leading low ratio of validation workforce to front-end design (Architecture, Design, and Design Verification). Continuously improve validation efficiency, coverage, and issue resolutions. Deliver validation milestones consistently and on time, with minimal bugs surfacing post-hardware qualification. Build a technically strong, self-directed validation team with clear ownership and disciplined execution. is on a mission to revolutionize AI compute systems and infrastructure at scale through the development of superior-scaling networking silicon and software which we call the Accelerated Compute Fabric. Founded and led by an executive team assembled from first-class semiconductor and distributed systems/software companies throughout the industry, Enfabrica sets themselves apart from other startups with a very strong engineering pedigree, a proven track record of delivering, deploying and scaling products in data center production environments, and significant investor support for our ambitious journey! Together, with their differentiated approach to solving the I/O bottlenecks in distributed AI and accelerated compute clusters, Enfabrica is unleashing the revolution in next-gen computing fabrics.

Our mission is to establish a modern, scalable, high-quality silicon validation methodology and operation that ensures efficiency and reliability across diverse AI workloads and customer use cases As a Silicon Validation Engineer, you will be responsible for post-silicon validation of high-performance networking ASICs involving Ethernet, RDMA/RoCE, InfiniBand (IB), PCIe, CXL, and Network-on-Chip (NoC) architectures You will work closely with design, firmware, software, and architecture teams to ensure the silicon meets performance, reliability, and compliance requirements before production deployment Qualifications We recognize that not all candidates will possess every skill listed, but these represent the key capabilities we seek: BSc/MSc/PHd in Electrical or Computer Engineering, preferably with 5+ years of post-silicon validation experience Strong expertise in high-speed networking (Ethernet, RDMA/RoCE, IB) and interconnects (PCIe Gen5/Gen6, CXL) Technical Expertise Silicon Debug & Validation: Bring-up, functional testing, stress/margin testing, and performance validation High-Speed Protocols: PCIe, CXL, RDMA, Ethernet MAC/PHY, congestion control algorithms Protocol analyzers, oscilloscopes, logic analyzers, BER testers Proficiency in Python for test automation, data analysis, and validation frameworks CI/CD & Test Infrastructure: Experience with automating validation pipelines and regression testin

Join our ambitious team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our mission is to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You will have the opportunity to work on groundbreaking products and collaborate with talented hardware and software engineers to create disruptive infrastructure solutions that excite our customers. We are seeking talented engineers experienced in physically implementing large-scale networking and computing semiconductor products. You will be part of a dynamic startup environment and contribute to the full lifecycle of complex chip development, from CAD tool flow setup to physical verification and tapeout. This role is based in India, with options for hybrid/remote work. Candidates capable of in-office participation in Hyderabad or Bangalore are preferred. Responsibilities: - Develop and maintain the CAD tool flow for physical implementation in a cloud-first environment. - Collaborate with architects on chip-level floorplan and block partitioning, considering tradeoffs in functional partitioning and interface complexity. - Design major physical structures like clock architecture, power delivery network, and interconnect topologies. - Execute physical implementation at block, cluster, and top levels, including synthesis, floorplan, timing closure, and tapeout. - Liaise with foundry and library partners on 3rd party IP integration and process technology issues. Skills/Qualifications: - Proven track record in physical implementation of high-performance network switching/routing fabrics, NICs, CPUs, or GPUs in the latest silicon process nodes. - Proficiency in CAD tools like Cadence Genus, Synopsys ICC2, and analysis tools such as Redhawk. - Experience with scripting languages like Perl, Python, and SystemVerilog. - Minimum BSEE/CE + 10 years or MSEE/CE + 5 years experience with products shipped in high volume. Company Background: We are a well-funded startup based in Mountain View, CA, founded by industry veterans and backed by top-tier investors. Our diverse team excels in co-designing hardware/software solutions and has a proven track record in processing global data center traffic. Note: The above job description is based on the mentioned details in the provided job description.,