Thanks for visiting our Career Page. We develop groundbreaking hardware, software, and system technologies that solve the critical bottlenecks in next-generation computing workloads - at any scale - across hyperscale cloud, edge, enterprise, 5G/6G, and automotive infrastructure. Please review our open positions and apply to the positions that match your qualifications. Rust Firmware Engineer (India) Hyderabad, India Full Time Experienced SUMMARY We are looking for an experienced Rust Software Engineer with a strong background in low-level firmware development, Linux systems, and board support to join our team. In this role, you will be responsible for designing, developing, and maintaining firmware for in-house developed PCBs, working closely with our hardware engineers to ensure seamless integration and performance. Key Responsibilities Design, implement, and maintain low-level firmware for custom PCBs using Rust. Develop and optimize drivers for various hardware components including CPLDs, Ethernet OSFPs, PCIe CEM by means of I2C and SPI interfaces. Collaborate with hardware engineers to understand board specifications and requirements. Work with Linux systems, and develop kernel drivers, to ensure proper integration and support for firmware components. Debug and troubleshoot hardware and software issues, providing effective solutions. Write and maintain comprehensive documentation for firmware and board support. Participate in code reviews and contribute to best practices in firmware development. Qualifications Bachelor s degree in Computer Science, Electrical Engineering, or a related field (or equivalent experience). Proven experience with Rust programming, particularly in low-level systems or embedded development. Strong understanding of Linux operating systems and their interaction with firmware. Experience developing and optimizing drivers for hardware components such as CPLDs, Ethernet OSFPs, PCIe CEM. Proficiency in debugging tools and techniques for both software and hardware issues. Excellent problem-solving skills and attention to detail. Strong communication skills and ability to work collaboratively in a team environment. Preferred Qualifications Experience with other systems programming languages (e.g., C, C++). Familiarity with embedded systems and microcontroller architectures. Experience with embedded or real-time operating systems (RTOS). Experience with Hubris is a plus, but not required. Experience with other embedded or similar systems is valued. Knowledge of version control systems (e.g., Git). Experience with Bazel build tooling is a plus. ABOUT US Enfabrica is on a mission to revolutionize AI compute systems and infrastructure at scale through the development of superior-scaling networking silicon and software which we call the Accelerated Compute Fabric. Founded and led by an executive team assembled from first-class semiconductor and distributed systems/software companies throughout the industry, Enfabrica sets themselves apart from other startups with a very strong engineering pedigree, a proven track record of delivering, deploying and scaling products in data center production environments, and significant investor support for our ambitious journey! Together, with their differentiated approach to solving the I/O bottlenecks in distributed AI and accelerated compute clusters, Enfabrica is unleashing the revolution in next-gen computing fabrics. Share Apply for this position Required * Apply with First Name * Last Name * Email Address * Phone * Address Resume * Weve received your resume. Click to update it. or Attach resume as .pdf, .doc, .docx, .odt, .txt, or .rtf (limit 5MB) or Paste your resume here or Please indicate which of the following skills and experiences you are proficient with * Writing and optimizing drivers for hardware components (e.g., CPLDs, I2C, SPI). Writing low-level firmware in Rust for embedded systems. Using Rust s ownership model and lifetime annotations effectively. Implementing and working with Rust s async/await for asynchronous programming. Using Rusts trait system and generics for efficient and reusable code. Writing unit tests and integration tests using Rust s built-in testing framework. Utilizing Rust s concurrency features, such as threads and async tasks. Debugging and troubleshooting Rust code in embedded environments. Using Bazel for build automation and dependency management in Rust projects. Managing Rust dependencies and builds using crates_universe. Writing and maintaining Rust code for real-time operating systems (RTOS). Interfacing Rust code with C/C++ through FFI (Foreign Function Interface). Employing debugging tools like GDB and openocd for embedded systems. Creating and managing build scripts for embedded projects. Writing and optimizing low-level code for performance and memory constraints. Using Rust s memory safety features to prevent common vulnerabilities and bugs. Documenting firmware and board support using Rust s documentation tools (e.g., rustdoc). Working with version control systems, particularly Git. Level of experience with rust *

Thanks for visiting our Career Page. We develop groundbreaking hardware, software, and system technologies that solve the critical bottlenecks in next generation computing workloads at any scale across hyperscale cloud, edge, enterprise, 5G/6G, and automotive infrastructure. Please review our open positions and apply to the positions that match your qualifications. IC Physical Design Engineer (India) Hyderabad or Bangalore, India Full Time Mid Level Physical Design Engineer Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industrys most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, from CAD tool flow setup, early floorplan exploration in conjunction with microarchitecture development, through block partitioning, power planning, clock network design and construction, through P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout. This role is based in India in either Hyderabad or Bangalore. Hybrid/remote is supported but preference will be for candidates who are capable of regular in office participation in either of the above locations. Roles and Responsibilities Build and support the CAD tool flow for physical implementation in a cloud first development environment. Work with architects and microarchitects on the chip level floorplan and block partitioning. Evaluate tradeoffs in functional partitioning, block size, and interface complexity with other stakeholders. Define and construct the major physical structures, including the clock and reset architecture, the power delivery network, and interconnect topologies. Execute on block level, cluster level, and top level physical implementation, from synthesis, floorplan and power plan, through P+R, through timing closure, physical verification, and tapeout. Interface with foundry and library partners on 3rd party IP and process technology issues, including updates to device models, IP integration requirements, and pre tapeout signoff. Skills/Qualifications : Proven industry experience and successful track record in the physical implementation of large, high performance network switching/routing fabrics (Ethernet, Infiniband, HPC), Network Interface Controllers, Smart NICs, CPUs, or GPUs in the latest silicon process nodes. Deep experience with the latest CAD tools through the entire physical design workflow, e.g., Cadence Genus and Innovus, Synopsys ICC2/FusionCompiler, Tempus, PrimeTime SI, PrimeTime PX, StarRC, ICV, Calibre. Strong familiarity with various analysis tools such as Redhawk, Voltus. Experience with circuit analysis using HSPICE is a plus. Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages. Minimum BSEE/CE + 10 years or MSEE/CE + 5 years experience. Proven track record of execution on products which have shipped in high volume. Company Background We are a well funded, stealth mode startup based in Mountain View, CA, founded by senior technical and business executives hailing from category leaders in infrastructure semiconductors and hyperscale cloud services, and backed by top tier investors with an immensely successful formula track record on early stage investments. We are a diverse team of expert chip/software/systems architects and developers who excel in hardware/software solution co design. Our team has built, and delivered into production, technologies that process over half of the worlds global data center traffic. Share Apply for this position Required * Apply with First Name * Last Name * Email Address * Phone * Address Resume * Weve received your resume. Click to update it. or Attach resume as .pdf, .doc, .docx, .odt, .txt, or .rtf (limit 5MB) or Paste your resume here or What was the process node for your most recent tapeout * How many placeable instances were in the largest block that you have worked on *

Enfabrica is at the forefront of building cutting edge networking silicon and system software to drive the revolution in AI and accelerated computing infrastructure at scale. We are seeking a hands-on Team Lead to drive the development of tools, automation, and infrastructure critical to validating high-performance networking ASICs. This role combines technical ownership of validation infrastructure with a functional leadership of our silicon validation team in the India region. You will architect scalable test environments and automation frameworks while guiding and coordinating validation engineers across projects. This position is ideal for a senior engineer who leads by example, mentors others, and drives execution excellence across both technology and people. Key Responsibilities Design and implement automation frameworks, test benches, and validation infrastructure using Python, C++, and industry-standard tools Build and maintain CI/CD pipelines and regression systems to support scalable and repeatable validation workflows Act as the technical lead for validation tools and infrastructure, enabling cross-site alignment and tool reuse Provide functional leadership for the silicon validation team in the India geo, including task planning, progress tracking, and performance feedback Remain deeply hands-on: develop test content, debug complex system issues, and lead root-cause analysis efforts Collaborate with design, DV, firmware, and software teams to ensure comprehensive test coverage and effective debug strategies Develop and apply debug methodologies using logs, protocol traces, and signal analysis tools Promote a culture of engineering excellence, technical documentation, and continuous improvement Qualifications Education & Experience BSc, MSc, or PhD in Electrical or Computer Engineering 7+ years of experience in post-silicon validation in microprocessors, networking, or high-speed interconnect products, with demonstrated ownership of test infrastructure and automation systems 2+ years in a technical leadership or geo/site lead role, combining engineering execution with team coordination Required Technical Strengths Proficient in Python and C++ Proven experience in designing and scaling validation frameworks and automation platforms Solid understanding of one or more of the following protocols: PCIe (Gen5/Gen6), CXL, Ethernet (MAC/PHY), RDMA/RoCE Preferred Technical Strengths Skilled in lab equipment: oscilloscopes, logic analyzers, protocol analyzers, BER testers Leadership & Mentorship Strong mentoring skills with the ability to grow junior engineers while delivering on team goals Experienced in managing and aligning geographically distributed engineering efforts Effective communicator across cross-functional teams including architecture, design, and firmware Self-driven, accountable, and thrives in fast-paced, high-impact environments Success Metrics Innovate and establish scalable, quality-driven, and cost-effective test infrastructure—measured by a leading low ratio of validation workforce to front-end design (Architecture, Design, and Design Verification) Continuously improve validation efficiency, coverage, and issue resolutions Deliver validation milestones consistently and on time, with minimal bugs surfacing post-hardware qualification Build a technically strong, self-directed validation team with clear ownership and disciplined execution About Us: Enfabrica is on a mission to revolutionize AI compute systems and infrastructure at scale through the development of superior-scaling networking silicon and software which we call the Accelerated Compute Fabric. Founded and led by an executive team assembled from first-class semiconductor and distributed systems/software companies throughout the industry, Enfabrica sets themselves apart from other startups with a very strong engineering pedigree, a proven track record of delivering, deploying and scaling products in data center production environments, and significant investor support for our ambitious journey! Together, with their differentiated approach to solving the I/O bottlenecks in distributed AI and accelerated compute clusters, Enfabrica is unleashing the revolution in next-gen computing fabrics. Powered by JazzHR SPUPSyk5w4 Show more Show less