850 Systemverilog Jobs - Page 3

You will collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Your responsibility will include owning end-to-end SOC RTL delivery while analyzing and optimizing design for power, performance, and area (PPA) targets. You will influence SoC definition, features, and adopt physical design friendly partitioning. Leading RTL design and integration of multi-subsystem SoCs, supporting complex architectures with multi-core, multi-power, and multi-reset domains will be a key aspect of your role. Demonstrating strong proficiency with front-end flows, including Lint, CDC, low-power (UPF) checks, synthesis, DFT, and Static Timing Analysis (STA) is essential. You will drive the development of robust Safety, Security, and Debug architectures for advanced SoCs with multiple interconnects. Designing and integrating standard interface protocols such as AHB, AXI, CHI, and memory interfaces including ROM, RAM, Flash, LPDDR/DDR3/4 will also be part of your responsibilities. Engaging cross-functionally with DFT, physical design, verification, emulation, and validation teams to ensure first-time-right silicon and on-time project delivery is crucial. Supporting post-silicon debug, bring-up, and validation, working closely with lab and silicon validation teams, will be part of your regular tasks. Continuously evaluating and adopting new design methodologies and best practices to improve productivity and shift-left the design cycle is expected from you. Mentoring junior engineers, reviewing their work, and providing technical leadership and guidance across multiple design projects will be an important aspect of your role. You will also provide overall leadership and tracking of the team's goals. Contributing to the innovation quotient of the team via Design Patents, Industry Standard Publications, AI-enabled design methodologies, etc., will be an integral part of your responsibilities. To qualify for this position, you should have an M.Tech/ B.Tech in Electrical Engineering or Computer Science with 12+ years of RTL design experience. Proven expertise in Verilog/SystemVerilog RTL design, integration, and microarchitecture is essential. A strong understanding of SoC architecture, AMBA protocols (AXI, AHB, APB), clock/power domains, and memory subsystems is required. Experience with EDA tools for synthesis, lint, CDC, RDC, and timing analysis is necessary. Familiarity with UPF/low-power design, formal verification techniques, and static/dynamic checks is also important. Excellent leadership, communication, and project management skills are desired, along with experience working with global cross-functional teams.,

As a FPGA Development Team Lead at Optiver, you will play a key role in establishing and leading the Mumbai FPGA & low latency development team. Your primary focus will be on ensuring best-in-market trade execution on Indian exchanges such as NSE, BSE, and MCX. You will collaborate closely with existing FPGA & low latency development teams in Sydney and Shanghai, gaining exposure to execution challenges in Optiver's global businesses. In this leadership position, you will work closely with internal stakeholders including trading, risk, compliance, and research teams based in the Mumbai office. Your responsibilities will involve shaping the future of the execution platform, leading a team of FPGA developers and low latency software developers, and influencing teams in the Asia Pacific region. Additionally, you will be involved in building and growing your team, while also having the opportunity to remain hands-on with VHDL and C++. Your team will be responsible for identifying business problems, designing innovative solutions, and overseeing the entire development lifecycle from design to deployment and monitoring. You will lead the effort to build a high-performance mixed FPGA development & low latency software development team, define the architecture of the trading stack, and contribute to Optiver's Asia Pacific execution capability. To excel in this role, you should have at least 5 years of experience in FPGA development within financial services/capital markets, along with experience in team leadership and project management. Proficiency in VHDL, Verilog, SystemVerilog, as well as basic skills in C++ and Python are essential. An understanding of computer networks and protocols will also be beneficial. Joining Optiver means becoming part of a collaborative and excellence-driven culture, where you will work alongside talented colleagues to solve complex problems in the financial markets. You can look forward to competitive remuneration, attractive bonus structures, personal development opportunities, and a supportive work environment that values diversity and inclusion. If you are a driven and experienced FPGA developer looking to lead a dynamic team and make a significant impact in the financial markets, this role at Optiver offers a rewarding and challenging opportunity to grow your skills and contribute to the success of a global market maker.,

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SoC Verification Engineer The Role The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Key Responsibilities Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requirements Preferred Experience Proficient in IP/Sub-System/SOC level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Processor Micro-Architecture concepts - Reset/Boot-flow/Cache Coherency/Interrupt flows knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience. Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SoC Verification ENGINEER The Role The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design. The Person You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Key Responsibilities Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requirements Preferred Experience Proficient in IP/Sub-System/SOC level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Processor Micro-Architecture concepts - Reset/Boot-flow/Cache Coherency/Interrupt flows knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience. Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Primary Title: ASIC/SoC Verification Engineer About The Opportunity A deeptech company operating at the intersection of Quantum Computing hardware and semiconductor systems, building custom ASIC/SoC solutions that enable next-generation quantum platforms. Our multi-disciplinary hardware team designs, verifies, and brings up complex mixed-signal/digital IPs and SoCs used in low-noise, high-fidelity quantum control systems. Location: Bangalore, Karnataka, India | Employment Type: Full-time Role & Responsibilities Define verification plans and acceptance criteria for ASIC/IP blocks and SoC-level features, translating specifications into measurable verification goals. Develop and maintain SystemVerilog/UVM testbenches, directed and constrained-random tests, functional coverage models, and assertions to achieve coverage closure. Run and manage simulation regressions using tools such as Synopsys VCS and debug failures with waveform/trace analysis and Verdi. Integrate verification environments with automation pipelines (TCL/Python/Shell), create CI-driven regressions, and maintain test artifacts and metrics dashboards. Work with RTL designers, architecture, and firmware teams to debug complex functional issues, support silicon bring-up, and iterate on corner-case fixes. Introduce and apply formal verification, emulation/FPGA-prototyping, and SoC-level integration strategies where applicable to accelerate verification and reduce risk. Skills & Qualifications Must-Have Bachelor’s degree in Electrical/Computer Engineering or equivalent; 3+ years of hands-on ASIC/SoC/IP verification experience. Strong SystemVerilog expertise and practical UVM experience building reusable verification components and test suites. Proven experience with simulation/debug tools (Synopsys VCS,Verdi or equivalent) and coverage-driven verification. Solid RTL comprehension, assertion-based verification (SVA), and ability to close functional coverage gaps. Scripting proficiency (Python, TCL, Shell) for test automation and regression orchestration. Preferred Experience with formal tools, emulation/FPGAs for prototyping, and SoC bring-up in lab/silicon validation. Familiarity with mixed-signal verification flows, quantum-control relevant timing constraints, or low-noise analog-digital interfaces. Advanced degree (MS/PhD) or prior work on complex SoC IP stacks and cross-team integration projects. Benefits & Culture Highlights Work on cutting-edge quantum hardware in a fast-paced deeptech environment with high ownership and visibility. Collaborative, cross-functional teams, mentorship opportunities, and a strong focus on engineering excellence and continuous learning. Competitive compensation, flexible work practices, and access to state-of-the-art lab and prototyping facilities. We are seeking proactive verification engineers who enjoy building robust verification strategies, automating workflows, and collaborating across hardware, firmware, and system teams to deliver silicon-quality results. Apply to join a team pushing the boundaries of quantum hardware and semiconductor design. Skills: vcs,quantum verification,hardware verification,verification tools,verification languages,verdi

About The Role We are seeking a skilled and motivated Hardware Design Engineer to join our Hardware team. Together, we will build the next generation of life-changing custom hardware for Quantum Computers ! If you are motivated, understand how complex SoCs and IPs are built, have a strong grasp of client requirements, and are familiar with various development cycles, this is the place for you. What You Will Be Doing Participate in micro-architecture development and document specifications Implement in RTL and collaborate with the verification team to ensure design functionality Apply logic design skills to optimize and meet performance and power goals Deliver a synthesis/timing-clean design while partnering with the physical design team to ensure a routable and physically implementable solution What We Need To See Bachelor’s degree in Electrical Engineering or Computer Engineering 3+ years of relevant experience in chip design development of complex designs Strong proficiency in logic design, Verilog, and/or SystemVerilog, with a deep understanding of physical design and VLSI Experience with design reuse, including RTL, constraints, and waivers Experience with timing constraints and timing exceptions Familiarity with standard quality checks such as LINT and CDC Strong interpersonal skills and a proven team player Skills: quality control,micro-architecture development,chip design development,architecture development,logic design,design,rtl design,teamwork,timing,physical design,vlsi fundamentals

Responsibilities Understand the standards/specifications Architecture development and documenting implementation level details Hands on work for every aspect of verification cycle Responsible for the compliance with the latest Methodologies. Developing Verification IPs Define Functional Coverage matrix and Comprehensive Test plan Regression management and functional coverage closure DUT integration and verification for IP delivery sign-off Leading small team Person Specification Required Skills Hands-on experience of complete verification cycle with strong verification concepts Strong knowledge of Verilog, SystemVerilog and UVM Experience in UVM based Verification IP development Experience in AMBA AXI/AHB/APB System buses Hands on work experience on any of PCIe/Eth/USB/DDR etc. Hands on experience with System Verilog Assertions Scripting for automation, release process, simulations, regressions Good command over written and oral communication Desirable Skills Lead the Verification IP development with 2 or more junior engineers Exposure to full verification cycle Desired Skills And Experience DV Engineer, Design Verification, Verification Engineer

Minimum qualifications: Bachelor's degree in Electrical Engineering or equivalent practical experience. 4 years of experience in Verification, verifying digital logic at RTL level using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or ASICs. Experience in verification and debug of IP/subsystem/SoCs in the Networking domain such as packet processing, bandwidth management, congestion control desired. Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems). Preferred qualifications: Master's degree in Electrical Engineering or a related field. Experience with industry-standard simulators, revision control systems, and regression systems. Experience in Artificial Intelligence/Machine Learning (AI/ML) Accelerators or vector processing units. Experience with the full verification life cycle. Excellent problem-solving and communication skills. About the job In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will own the full verification life-cycle from verification planning and test execution to coverage closure, with an emphasis on meeting stringent AI/ML performance and accuracy goals, build constrained-random verification environments capable of exposing corner-case bugs and ensuring the reliability of Artificial Intelligence/Machine Learning (AI/ML) workloads on Tensor Processing Unit (TPU) hardware. You will collaborate closely with design and verification engineers in active projects and perform verification. The ML, Systems, and Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Responsibilities Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios. Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct design blocks. Measure to identify verification holes and to show progress towards tape-out. Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM). Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

JD: This role requires expertise in PCIe, CPU, Ethernet, CXL, DDR, and RISC-V technologies. Key Responsibilities: Develop and execute verification plans for hardware designs incorporating PCIe, Ethernet, CXL, DDR, and RISC-V technologies. Design and implement verification environments using SystemVerilog and UVM methodologies. Develop test cases to validate functional correctness, performance, and compliance with industry standards. Collaborate with the design team to debug and resolve issues identified during verification. Perform coverage analysis to ensure thorough verification of the design. Required Skills: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. Experience in ASIC/FPGA verification with a focus on PCIe, Ethernet, CXL, DDR, and RISC-V protocols. Proficiency in SystemVerilog and familiarity with UVM methodology. Strong problem-solving and debugging skills. Excellent communication and teamwork abilities. Preferred Skills: Familiarity with high-speed serial interfaces such as PCIe Gen4/Gen5, Ethernet 400G/800G, or CXL. Experience with verification tools such as VCS, Questa, or ModelSim. Knowledge of scripting languages such as Perl or Python. Understanding of computer architecture and digital logic design principles.

Company Description: MosChip® Technologies is a publicly traded company specializing in Silicon and Product Engineering solutions, with over 1300 engineers located in Silicon Valley-USA and India. The company offers comprehensive engineering solutions in silicon design, verification, systems, software, device engineering, AI/ML design, and test automation. MosChip® is known for developing and shipping millions of connectivity ICs and has an outstanding track record of first-time right silicon across 200+ SoC tape-outs. Role Description: This is a full-time on-site role for a Senior ASIC/SOC/IP Design Verification Engineer at MosChip®, located in Hyderabad. The role involves performing day-to-day tasks such as formal verification, RTL design, functional verification, and debugging. The engineer will work closely with cross-functional teams to ensure the quality and efficiency of silicon design and verification processes. Experience required: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Developing UVM based verification frameworks and testbenches, processes and flows Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Ruby, Makefile, shell preferred. Good understanding of object-oriented programming concepts Prior experience with protocols such as AXI, APB, AHB etc Excellent communication skills. Good problem-solving skills and analytical ability. Required: 4-10 years of professional experience in the industry with a proven track record of successfully building and delivering complex SOC computing devices.

Phinity is helping the labs building AGI automate hardware engineering by building environments to train agents on hardware design and verification tasks. Our customers include one of the largest frontier labs. We're seeking hardware engineers to collaborate with frontier lab researchers to create high-quality RTL design, verification, and debugging challenges that mirror real-world semiconductor development. It is a remote/hybrid position with flexible hours, with pay up to $90/hour based on experience. What you’ll do: Develop realistic RTL design and verification problems that reflect industry complexity and best practices Build and optimize containerized environments for agent training tasks in hardware design workflows Work directly with frontier lab AI researchers to understand agent capabilities and training requirements Required Experience: 2+ years in RTL design using Verilog/SystemVerilog or VHDL Strong background in verification methodologies (UVM, SystemVerilog, testbench development) Experience with synthesis, timing analysis, and debugging tools Familiarity with industry-standard EDA tools (Synopsys, Cadence, Mentor Graphics) Skills: Strong problem-solving and analytical thinking Excellent communication skills for cross-functional collaboration for researchers who are not hardware experts Curiosity about AI/ML applications in hardware design Self-motivated and able to work independently in a remote environment

Job Title: IP Design Technical Lead/ Staff ASIC RTL Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and forward-thinking digital design expert with a strong foundation in ASIC RTL design and a proven track record of delivering complex, high-performance IP cores. With a Bachelors or Masters degree in EE, EC, or VLSI and over four years of relevant industry experience, you thrive in dynamic, multi-site environments and excel at translating functional specifications into robust, scalable architectures. Youre adept at working with advanced protocols such as Ethernet, DDR, PCIe, and USB, and have hands-on experience in data path and control path design, including Reed Solomon FEC, BCH codes, and MAC SEC engines. Your expertise extends to synthesizable Verilog/SystemVerilog coding, timing closure, CDC analysis, and P&R-aware synthesis, complemented by a keen understanding of design trade-offs in area, latency, and throughput. You are comfortable leveraging version control systems like Perforce and scripting languages such as Perl or Shell to automate and streamline workflows. As a natural leader, you are ready to mentor and technically guide a team of designers, fostering a collaborative and inclusive culture. Communication comes easily to you, and youre known for your proactive problem-solving skills, attention to detail, and unwavering commitment to design quality. Youre seeking an opportunity to take ownership of challenging projects, contribute to cutting-edge innovation, and grow alongside a team of world-class engineering professionals. What Youll Be Doing: Architecting and implementing state-of-the-art RTL designs for the DesignWare IP family, targeting commercial, enterprise, and automotive applications. Translating standard and functional specifications into detailed micro-architectures and comprehensive design documentation for medium to high complexity features. Leading and contributing hands-on to RTL coding, synthesis, CDC analysis, debug, and test development tasks. Collaborating with global teams and engaging directly with customers to understand and refine specification requirements. Driving technical excellence in design processes, including linting, static timing analysis, formal checking, and P&R-aware synthesis using tools such as Fusion Compiler. Mentoring and technically leading a team of designers, providing guidance on best practices and innovative design methodologies. Utilizing version control systems and scripting to manage design flows and automate repetitive tasks for improved efficiency. The Impact You Will Have: Enable Synopsys to deliver industry-leading, high-performance IP cores that power next-generation technologies. Contribute to the successful execution of complex, global projects that set new standards in chip design and verification. Accelerate time-to-market for customers in commercial, enterprise, and automotive sectors by delivering robust, reliable IP solutions. Elevate the technical capabilities of your team through mentorship and leadership, cultivating a culture of continuous learning and innovation. Drive improvements in design quality, efficiency, and scalability through process optimization and automation. Directly influence product architecture and feature enhancements, ensuring alignment with customer needs and emerging industry trends. What Youll Need: Bachelors or Masters degree in Electrical Engineering, Electronics, VLSI, or related field. 4+ years of hands-on industry experience in ASIC RTL design, with a strong portfolio of completed projects. Deep expertise in data path and control path design, including experience with Reed Solomon FEC, BCH codes, CRC architectures, and MAC SEC engines. Proficiency in synthesizable Verilog/SystemVerilog, simulation tools, and design flows including lint, CDC, synthesis, and static timing analysis. Familiarity with high-speed design (>600MHz), P&R-aware synthesis, and EDA tools such as Fusion Compiler. Experience with version control systems (e.g., Perforce) and scripting languages (Perl, Shell) for design automation. Knowledge of industry protocols: Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA (AMBA2, AXI). Exposure to quality processes in IP design and verification is an advantage. Prior experience as a technical lead or mentor is highly desirable. Who You Are: Innovative thinker with a solutions-oriented mindset and a passion for technology. Excellent communicator who thrives in collaborative, multicultural, and multi-site environments. Natural leader with mentoring abilities, fostering inclusion and diversity within the team. Detail-oriented professional with strong analytical and problem-solving skills. Self-motivated, adaptable, and eager to drive technical excellence and process improvements. Committed to continuous learning and staying ahead of industry trends. The Team Youll Be A Part Of: You will join the R&D Solutions Group at our Bangalore Design Center, as part of the DesignWare IP Design team. This diverse and innovative group is dedicated to architecting, developing, and delivering cutting-edge IP cores that enable Synopsys global customers to achieve their design goals. The team thrives on collaboration, technical excellence, and shared success, working in a supportive environment that values creativity, knowledge sharing, and continuous growth. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SE NIOR SILICON DESIGN ENGINEER THE ROLE : We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Develop/Maintain tests for functional verification and performance verification at the core level Build testbench components to support the next generation IP Maintain or improve current test libraries to support IP level testing Create hardware emulation build to verify the IP functional performance Maintain and improve current hardware emulation environment to speed up the runtime performance and improve the debug facility Provide technical support to other teams PREFERRED EXPERIENCE: Good at C/C++ Familiarity with SystemVerilog and modern verification libraries like UVM Experience/Background on Computing/Graphics is a benefit Experience with OpenGL/OpenCL/D3D programming is a benefit ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Principal / Staff Design Verification Engineer Bangalore Our client can be described as "Developing Foundational Technologies for Chiplet Based Semiconductor Design". They are an early-stage startup, pioneering technologies for the emerging multi-chiplet system-on-package paradigm. Their mission is to enable the next wave of growth in the semiconductor space, and they're looking for passionate individuals to join a seasoned and dynamic team. Positions Available in Bengaluru, India/fully onsite Principal Design Verification engineer Responsibilities: Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards Collaborate with software teams to define and implement configurable test benches Work with design teams test plans, failure debug, coverage, etc. Qualifications and Preferred Skills BS, MS in Electrical Engineering, Computer Engineering or Computer Science 6-12 years and current hands-on experience in block-level/IP-level/SoC-level verification Proficiency in Verilog, SystemVerilog Familiarity with industry-standard EDA tools for simulation and debug Deep experience with UVM-based test benches Experience with modern programming languages like Python Knowledge of Arm AMBA protocols such as AXI, APB, and AHB Understanding of Arm CHI protocol is a plus Experience on working with IPs for caches, cache coherency, memory subsystems, interconnects and NoCs Experience with formal verification techniques, emulation platforms is a plus Excellent problem-solving skills and attention to detail Strong communication and collaboration skills Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com

Principal IP/RTL Design Engineer for Ethernet Switch Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. IP/RTL Design Engineer for Ethernet Switch Position Overview We are seeking an experienced IP/RTL Design Engineer with over 10 years of experience to join our team in designing and developing intellectual property (IP) and RTL for Ethernet switches tailored for AI datacenter backend networks. The ideal candidate will have a strong background in digital design, ASIC/FPGA development, Ethernet protocols, and experience with high-performance interconnect protocols such as InfiniBand, NVLink, Infinity Fabric, with a focus on delivering high-performance, low-latency solutions for large-scale AI workloads. Key Responsibilities Design and optimize IP blocks (MAC, PCS, packet processors) for Ethernet switches. Develop synthesizable RTL (Verilog/SystemVerilog) meeting performance and timing goals. Optimize designs for low latency, high throughput, and power efficiency. Implement Ethernet protocols (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control. Apply knowledge of InfiniBand, NVLink, or similar protocols for feature implementation. Use P4 or related languages for programmable packet processing. Collaborate with teams for synthesis, timing closure, and IP integration. Document designs and stay updated on AI networking trends. Required Qualifications Education: BS/MS/PhD in Electrical or Computer Engineering. Technical Skills: Proficient in Verilog/SystemVerilog for design. Knowledge of Ethernet (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control. Experience with InfiniBand, NVLink, or similar protocols. Proficiency in P4 or programmable data plane languages. Knowledge of UALink, Ultra Ethernet, or RDMA/RoCE. Familiarity with power optimization or SDN. Familiarity with synthesis (e.g., Synopsys Design Compiler) and timing tools. Soft Skills: Strong problem-solving, communication, and teamwork skills. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Job Title: IP Design Technical Lead/ Staff ASIC RTL Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and forward-thinking digital design expert with a strong foundation in ASIC RTL design and a proven track record of delivering complex, high-performance IP cores. With a Bachelor’s or Master’s degree in EE, EC, or VLSI and over four years of relevant industry experience, you thrive in dynamic, multi-site environments and excel at translating functional specifications into robust, scalable architectures. You’re adept at working with advanced protocols such as Ethernet, DDR, PCIe, and USB, and have hands-on experience in data path and control path design, including Reed Solomon FEC, BCH codes, and MAC SEC engines. Your expertise extends to synthesizable Verilog/SystemVerilog coding, timing closure, CDC analysis, and P&R-aware synthesis, complemented by a keen understanding of design trade-offs in area, latency, and throughput. You are comfortable leveraging version control systems like Perforce and scripting languages such as Perl or Shell to automate and streamline workflows. As a natural leader, you are ready to mentor and technically guide a team of designers, fostering a collaborative and inclusive culture. Communication comes easily to you, and you’re known for your proactive problem-solving skills, attention to detail, and unwavering commitment to design quality. You’re seeking an opportunity to take ownership of challenging projects, contribute to cutting-edge innovation, and grow alongside a team of world-class engineering professionals. What You’ll Be Doing: Architecting and implementing state-of-the-art RTL designs for the DesignWare IP family, targeting commercial, enterprise, and automotive applications. Translating standard and functional specifications into detailed micro-architectures and comprehensive design documentation for medium to high complexity features. Leading and contributing hands-on to RTL coding, synthesis, CDC analysis, debug, and test development tasks. Collaborating with global teams and engaging directly with customers to understand and refine specification requirements. Driving technical excellence in design processes, including linting, static timing analysis, formal checking, and P&R-aware synthesis using tools such as Fusion Compiler. Mentoring and technically leading a team of designers, providing guidance on best practices and innovative design methodologies. Utilizing version control systems and scripting to manage design flows and automate repetitive tasks for improved efficiency. The Impact You Will Have: Enable Synopsys to deliver industry-leading, high-performance IP cores that power next-generation technologies. Contribute to the successful execution of complex, global projects that set new standards in chip design and verification. Accelerate time-to-market for customers in commercial, enterprise, and automotive sectors by delivering robust, reliable IP solutions. Elevate the technical capabilities of your team through mentorship and leadership, cultivating a culture of continuous learning and innovation. Drive improvements in design quality, efficiency, and scalability through process optimization and automation. Directly influence product architecture and feature enhancements, ensuring alignment with customer needs and emerging industry trends. What You’ll Need: Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related field. 4+ years of hands-on industry experience in ASIC RTL design, with a strong portfolio of completed projects. Deep expertise in data path and control path design, including experience with Reed Solomon FEC, BCH codes, CRC architectures, and MAC SEC engines. Proficiency in synthesizable Verilog/SystemVerilog, simulation tools, and design flows including lint, CDC, synthesis, and static timing analysis. Familiarity with high-speed design (>600MHz), P&R-aware synthesis, and EDA tools such as Fusion Compiler. Experience with version control systems (e.g., Perforce) and scripting languages (Perl, Shell) for design automation. Knowledge of industry protocols: Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA (AMBA2, AXI). Exposure to quality processes in IP design and verification is an advantage. Prior experience as a technical lead or mentor is highly desirable. Who You Are: Innovative thinker with a solutions-oriented mindset and a passion for technology. Excellent communicator who thrives in collaborative, multicultural, and multi-site environments. Natural leader with mentoring abilities, fostering inclusion and diversity within the team. Detail-oriented professional with strong analytical and problem-solving skills. Self-motivated, adaptable, and eager to drive technical excellence and process improvements. Committed to continuous learning and staying ahead of industry trends. The Team You’ll Be A Part Of: You will join the R&D Solutions Group at our Bangalore Design Center, as part of the DesignWare IP Design team. This diverse and innovative group is dedicated to architecting, developing, and delivering cutting-edge IP cores that enable Synopsys’ global customers to achieve their design goals. The team thrives on collaboration, technical excellence, and shared success, working in a supportive environment that values creativity, knowledge sharing, and continuous growth. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day. Job Summary We are looking for a candidate with excellent communication skills and ability to ramp up on new technologies quickly and independently. This position requires the technical expertise in Emulation domain. This an excellent opportunity to work in a supportive and friendly work environment, where we are vested in each other’s success, and are passionate about technology and innovation. Position Description Product validation engineer to work on key Palladium technologies including UPF. Position is based in Noida/Bangalore. Role involves verification of various upcoming features in Palladium. Work also involves managing current set of regressions. Participate in technical discussions, including Functional Specification reviews, Testplan reviews etc Review and guide team members on technical deliverables from the team Person will be fully responsible and accountable for quality of releases and features for Palladium emulation technology. Mentor juniors in the team Contribute towards the improvement of existing emulation validation/verification flows Position Requirements The person should be an Electrical, Electronics or Computer Science Engineer with very good understanding of HDLs (Verilog and/ or VHDL). Prior experience in Emulation/UPF will be big plus. He/ she should have a good working knowledge of EDA tools (Cadence/ Others) specially Palladium with focus towards debugging design/ verification problems. Experience in process automation with scripting. Experience with SystemVerilog, C++, UVM. Experience with Functional Verification of complex digital systems, e.g. SoC Verification, with a Hardware Verification Language (HVL) like SystemVerilog. Behavioral Skills Required Must possess strong written, verbal and presentation skills. Good communication and interpersonal skills, demonstrate teamwork and collaboration skills. Ability to establish a close working relationship with both customer peers and management. Explore what’s possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity We’re doing work that matters. Help us solve what others can’t.

Cloudious LLC is one of the fastest emerging IT Solutions and Services company headquartered in San Jose, CA with their global offices in Canada, EMEA & APAC. We are currently hiring a seasoned Design Verification Engineer (NoC, SoC) who comes with a strong consulting mindset Design Verification Engineer (NoC, SoC) Hyderabad (Onsite) Full Time Skills: NoC - Network on Chip SoC - System-on-Chip Experience: 5 to 10 Years Strong experience in SystemVerilog, UVM methodologies. Hands-on experience in SoC, NoC design verification. Good knowledge of bus protocols (AMBA, AXI, etc.). Familiarity with scripting languages (Perl/Python/TCL) is a plus. Strong problem-solving and debugging skills. Experience from product-based companies

This position offers a unique opportunity to utilize your hardware verification skills in the PowerVR Hardware Graphics group by working on cutting-edge designs. You will be responsible for overseeing all verification activities for a GPU component or subsystem, from initial planning to final sign-off. Your role will involve developing verification plans, building and maintaining UVM testbench components, monitoring and reporting verification metrics, and providing feedback during design specification discussions. Additionally, you will implement UVM testbenches, including writing tests, sequences, functional coverage, assertions, and verification plans. Taking ownership of task definition, effort estimation, and progress tracking will be crucial in this role. You will also contribute to enhancing GPU verification methodologies, lead and mentor team members, and engage in design and verification reviews. The ideal candidate is committed to ensuring the success of customers, stakeholders, and colleagues. You should possess excellent communication skills, be a good listener, and collaborate effectively to build trusted partnerships. A strong problem-solving ability and a focus on innovation are essential qualities for this role. You should have demonstrated experience in developing verification environments for complex RTL designs, a deep understanding of verification methodologies, and expertise in SystemVerilog and UVM. Proficiency in planning, estimating, and tracking personal tasks is required, along with the capability to manage multiple projects simultaneously. Experience in ASIC design methodologies, familiarity with broader verification technologies, and knowledge of functional safety standards would be advantageous. Imagination, a UK-based company, specializes in creating silicon and software IP to give its customers a competitive edge in global technology markets. The company's GPU and AI technologies enable exceptional power, performance, and area efficiency, fast time-to-market, and reduced total cost of ownership. Imagination's products are used by billions of people worldwide in smartphones, cars, homes, and workplaces. Joining the team at Imagination means contributing to the development of cutting-edge technology that will impress the industry and customers, ensuring that people everywhere can benefit from smarter and faster tech innovations. If you are seeking a challenging opportunity to bring your talent, curiosity, and expertise to a dynamic organization, and be part of a leading semiconductor IP solutions company, then Imagination is the place for you. Join us in transforming, innovating, and inspiring millions of lives through our technology.,

Principal / Staff IP/RTL Design Engineer (AI Accelerator) – Multiple positions - Hyderabad Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. Well-funded product startup is looking for RTL Design Engineers to contribute to the development of novel high performance AI accelerators from scratch. In this role you will collaborate with cross-functional teams, including architect, software, verification, physical design, systems engineers, to define and implement next generation AI architectures. We are seeking highly experienced individuals who have a passion for innovation and are excited about the opportunity to create world class products from India. The key responsibilities for this role include, but are not limited to: Key Responsibilities Design and implement high-performance TPUs/MPUs and other related AI blocks using RTL. Own IP/block-level RTL from spec to GDS, including design, synthesis, and timing closure. Optimize design for power, performance, and area (PPA). Interface with physical design and DFT (Design for Test) engineers for seamless integration. Drive design reviews, write design documentation, and support post silicon bring-up/debug. Minimum Qualifications B.S./M.S./Ph.D. in ECE/CS from top engineering college with 5-15 years of related experience. Previous experience in either high performance processor design or AI accelerator design is plus. Clear understanding of floating-point arithmetic, vector processing, SIMD, MIMD, VLIW, EPIC concepts. Strong grasp of digital design fundamentals, computer architecture, virtual memory and high-speed data-path design. Proficiency in Verilog/SystemVerilog and simulation tools. Experience with EDA tools (e.g., Synopsys, Cadence) for synthesis, lint, CDC, and timing analysis. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

We are seeking a skilled Embedded SystemC Architect with over 10 years of experience to take charge of designing and developing high-performance virtual platforms and system-level models in Bangalore. As an Embedded SystemC Architect, you will play a crucial role in creating SystemC/TLM 2.0 models for various SoC components and virtual platforms, along with developing and enhancing embedded software and firmware elements in C/C++. Your expertise in SystemC modeling, SoC architecture, and solving intricate hardware-software interaction issues will be pivotal in this position. Your responsibilities will include designing and implementing SystemC/TLM 2.0 models for SoC components and virtual platforms, creating and managing embedded software and firmware components in C/C++, optimizing models for CPU, memory subsystems, hardware accelerators, and bus protocols, modeling peripherals such as Timers, DMA Controllers, and I/O devices, collaborating with hardware and software teams for co-simulation and integration, as well as mentoring junior engineers and leading technical discussions related to modeling and simulation. Key Requirements: - Proficiency in SystemC and TLM 2.0. - Strong command over C/C++ programming with a profound knowledge of Object-Oriented Programming (OOPS). - Hands-on experience in embedded software/firmware development. - Extensive understanding of SoC architecture, including CPU pipelines, GPUs, memory controllers and subsystems, hardware accelerators, and bus protocols (AXI, PCIe, USB). - Experience in modeling embedded peripherals. - Exposure to PSoc programming. Desired Skills: - Previous experience in developing Virtual Platforms (VPs) for semiconductor or embedded products. - Familiarity with simulators like QEMU, Synopsys Virtualizer, or equivalents. - Knowledge of hardware/software co-simulation methods. - Understanding of Verilog/SystemVerilog for hardware design analysis. If you are passionate about embedded systems, SystemC modeling, and SoC architecture, and possess a strong technical background in the mentioned areas, we encourage you to apply for this challenging and rewarding role as an Embedded SystemC Architect.,

What you have: B.Tech/B.E in Computer Engineering (or allied discipline e.g. Electrical, Electronics) 13+ years of experience in the design, verification, and validation of advanced ARM-based SOCs 5+ years in building, managing, and mentoring large verification team span across multiple geographies Deep understanding of ARM-based SOC Verification using SystemVerilog/UVM methodology. Writing assembly and C firmware for embedded ARM processors and debugging in a simulation environment Hands-on experience in advanced verification techniques using constrained random verification methodology, building reference models, scoreboard, and self-checking TBs Working experience in DSP (Digital Signal Processing) is highly desirable Working experience and knowledge in AMBA protocols, CoreSight Debugger, LPDDR, Ethernet, MIPI, and high-speed serdes Experience in building teams including hiring, mentoring, scheduling/budgeting, and providing focal reviews and feedbacks Ability to collaborate deeply with design, verification, architecture, and management teams Ability to deliver results in a very fast-moving environment Desire to learn & implement groundbreaking new processes and methodology for continuous verification improvement

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell Data Centre Engineering (DCE) - Compute & Storage (CCS) BU has been at the forefront of developing and delivering leading-edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast?growing product lines, Marvell technology is powering the next?generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Automotive Compute market segments. The team focusses on the Custom ASIC business, Cloud AI solutions & Enterprise/Career solutions including the CXL product line. What You Can Expect Develop and maintain testbenches for IP, subsystem, and SoC-level verification Design and implement UVM-based verification environments Write and execute directed and random test cases Perform functional coverage analysis and debug failures Collaborate with design, architecture, and validation teams to ensure verification completeness Participate in code reviews, quality improvement, and problem-solving initiatives What We're Looking For - Bachelor's degree in CS/EE with 8-12 years of relevant experience, or Master's degree in CS/EE with 8-10 years of relevant experience - Strong background in IP, Subsystem and SoC verification, including methodology and testbench development - Proficient in hardware verification languages such as Verilog, SystemVerilog, UVM, and C/C++ - Solid understanding of verification methodologies: object-oriented programming, white-box/black-box testing, directed/random testing, coverage analysis, and gate-level simulations - Experience in Unix/Linux environments scripting skills in Shell, Perl, or Python are a plus - Strong analytical and problem-solving skills - Ability to manage multiple tasks in a fast-paced environment - Excellent communication, interpersonal, and teamwork skills - Capable of interfacing effectively at all levels within and outside the organization - Proactive in participating in problem-solving and quality improvement initiatives Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it's like to work at Marvell, visit our page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1

Job Position : Design Verification Experience : 5 – 10 Years Location : Hyderabad Notice Period : Immediate or those who are in serving notice only • Strong experience in ARM based SOC and ARM based SS level Design verification . • Must have worked on ARM based SOC viz Cortex A or M series based SOC • Experence in Multi processor based ARM cpu is plus • Coresight Debug knowledge – coresight is plus : ARM SoC based debug infrastructure including CoreSight infrastructure (implementation and/or validation). • Strong debug skills with AXI/AHB/APB, memory, and NoC components. • Strong work experience in AMBA – AXI/AHB protocol based NOC , Understanding/ experience in CHI/ACE is plus • Strong skills/Proficiency in SystemVerilog, UVM • Strong work experience(Advanced skills ) in SV-UVM and/or C based verification. Working knowledge in TB/Checker/SB development is plus. Must posses strong SV/UVM debugging • Proficiency in C/C++ modeling. • GLS experience is a plus; • Should have worked on handling regressions – RTL /GLS simulations and should possess excellent debugging skills • Must be proactive, independent, and capable of strong simulation debug. • Work Expereince or Strong knowledge in Memory SS verification - LPDDR5/LPDDR4/DDR protocols or HBM is plus • Work experience in PCIe/CXL and other similar complex protocol like Ethernet is plus • Scripting knowledge – python, perl if worked is plus and should posses working knowledge in updating/fixing flow/pre or post processing scripts

Job Description Collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Own end-to-end SOC RTL delivery while analysing and optimizing design for power, performance, and area (PPA) targets. Influence SoC definition, features, and adopt physical design friendly partitioning. Lead RTL design and integration of multi-subsystem SoCs , supporting complex architectures with multi-core, multi-power, and multi-reset domains . Demonstrate strong proficiency with front-end flows , including Lint, CDC, low-power (UPF) checks, synthesis, DFT , and Static Timing Analysis (STA) . Drive the development of robust Safety, Security, and Debug architectures for advanced SoCs with multiple interconnects. Design and integrate standard interface protocols such as AHB, AXI, CHI , and memory interfaces including ROM, RAM, Flash, LPDDR/DDR3/4 . Engage cross-functionally with DFT, physical design, verification, emulation, and validation teams to ensure first-time-right silicon and on-time project delivery. Support post-silicon debug, bring-up, and validation , working closely with lab and silicon validation teams. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Mentor junior engineers, review their work, and provide technical leadership and guidance across multiple design projects. Provide overall leadership and tracking of the team’s goals. Contribute to the innovation quotient of the team via Desing Patents, Industry Standard Publications, AI-enabled design methodologies etc. Qualifications M.Tech/ B.Tech in Electrical Engineering or Computer Science with 12+ years of RTL design experience. Proven expertise in Verilog/SystemVerilog RTL design, integration, and microarchitecture. Strong understanding of SoC architecture, AMBA protocols (AXI, AHB, APB), clock/power domains, and memory subsystems. Experience with EDA tools for synthesis, lint, CDC, RDC, and timing analysis. Familiarity with UPF/low-power design, formal verification techniques, and static/dynamic checks. Excellent leadership, communication, and project management skills. Experience working with global cross-functional teams. Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement . Job title Principal Engineer, RTL Design Department Engineering Location Noida Remote No Requisition ID 20019554_2025-03-12