267 Systemverilog Jobs - Page 4

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The person should be an Electrical, Electronics or Computer Science Engineer with very good understanding of HDLs (Verilog and/ or VHDL). Prior experience in simulation/emulation using these languages. He/ she should have a good working knowledge of EDA tools (Cadence/ Others) with focus towards debugging design/ verification problems using these tools. Experience in process automation with scripting. Experience with SystemVerilog, C++, UVM. Experience with Functional Verification of complex digital systems, e.g. SoC Verification, with a Hardware Verification Language (HVL) like SystemVerilog. Experience designing and implementing complex functional verification environments is required. Knowledge of protocols like PCIe, USB3/4, DP an added advantage. We’re doing work that matters. Help us solve what others can’t. Show more Show less

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: PMTS SILICON DESIGN ENGINEER As a SerDes Verification Architect , you will be responsible for the verification and validation of high-speed SerDes interfaces, including testing data integrity, performance, and protocol compliance. You will work closely with hardware and design teams to ensure that SerDes designs meet the required specifications, operating parameters, and quality standards. Key Responsibilities: Verification of SerDes Designs: Develop and execute verification plans and testbenches for SerDes IPs (Intellectual Property) and subsystems to ensure they meet functional and performance requirements. Testbench Development: Design and implement verification testbenches using industry-standard verification methodologies (e.g., UVM, SystemVerilog, VHDL). Simulation and Debugging: Perform simulations, analyze results, and debug issues related to timing, protocol errors, and other design anomalies in SerDes blocks. Performance Evaluation: Evaluate and validate performance characteristics of SerDes systems including jitter, bit error rates (BER), signal integrity, eye diagrams, and other key metrics. Protocol Compliance Testing: Verify adherence to relevant SerDes protocols such as UCIe , PCIe, Ethernet, USB, DDR, DisplayPort, or custom protocols. Automated Testing: Develop automated regression tests to ensure the robustness and stability of the SerDes design over multiple versions and iterations. Collaboration: Work closely with the design, hardware, and software teams to troubleshoot issues, implement fixes, and verify design changes. Documentation: Create detailed reports and documentation on verification results, test scenarios, and issues found during testing. Verification methodology: Provide feedback for design and verification process improvements and contribute to innovation in verification strategies and methodologies. Experience: 16+ years of experience in SerDes verification or high-speed communication verification. Strong hands-on experience with verification methodologies such as UVM, SystemVerilog, or other simulation-based verification tools. Knowledge of high-speed serial protocols such as UCIe , PCIe, Ethernet, USB, DDR, or custom protocols. Experience in analyzing and interpreting signal integrity issues, jitter, BER, and eye diagrams. Skills: Solid understanding of SerDes architectures, link training, and equalization. Strong debugging skills, with the ability to work across multiple domains (timing, protocol, performance). Familiarity with hardware description languages (HDL) like VHDL or Verilog. Strong analytical, problem-solving, and communication skills. Experience with DDR protocol (e.g., DDR3, DDR4, DDR5) for memory interface verification. Understanding of UCIe protocol and its role in chiplet-to-chiplet communication. Preferred Skills: Experience with Python, Perl, or similar scripting languages for automation. Exposure to high-speed memory interface design and verification, including DDR controller IP verification. Functional coverage, assertions knowledge in SV/UVM. Ability to work in a fast-paced environment and manage multiple verification tasks. Strong team player with good interpersonal and communication skills. #LI-PS1 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Staff GPU Verification Engineer Bangalore India, Hyderabad India Experienced Professional Posted 4 Jun 2025 502669 The role This position is a unique opportunity to exercise your hardware verification skills on cutting edge designs within the prestigious PowerVR Hardware Graphics group. Here you will exercise your skills on key components that meet latest demands and improvements for graphics, AI or connectivity processor and related IP. You will: Be responsible for the delivery of all verification activities related to a GPU component or sub-system from early stages of verification planning to sign-off Create verification plans, develop and maintain UVM testbench components Track and report verification metrics and closure Participate in all stages of design specification definition providing feedback from the verification perspective Develop testbenches in UVM, write tests, sequences, functional coverage, assertions & verification plans. Be responsible for the definition, effort estimation and tracking of your own work Be able to influence and advance our GPU verification methodology Have the opportunity to lead, coach and mentor other members of the team Participate in design and verification reviews and recommend improvements About you Committed to making your customers, stakeholders and colleagues successful, you’re an excellent communicator, listener and collaborator who builds trusted partnerships by delivering what you say, when you say. You’re curious, solutions orientated and a world-class problem solver who constantly seeks opportunities to innovate and achieve the best possible outcome to the highest imaginable standard. You'll have: Have a proven track record of developing verification environments for complex RTL designs Have excellent understanding of constrained-random verification methodology and challenges of verification closure Be confident in defining verification requirements, and work out the implementation approach and details of a testbench Be able to do root-cause analysis of complex issues and resolve them in a timely manner Have excellent knowledge of SystemVerilog and UVM Be able to develop new verification flows Have working knowledge of ASIC design methodologies, flows and tools Be able to plan, estimate and track your own work Experience working on multiple projects at one time The skill to be able to communicate technical issues both in written form and verbally You might also have: Experience leading teams Graphics/GPU/CPU/SoC knowledge Experience in wider verification technologies, such formal property based verification and code mutation Skill scripting in Python, TCL, Perl, SystemC, C++ experience Understanding of functional safety standards such as ISO26262 Who we are Imagination is a UK-based company that creates silicon and software IP designed to give its customers an edge in competitive global technology markets. Its GPU and AI technologies enable outstanding power, performance, and area (PPA), fast time-to-market, and lower total cost of ownership. Products based on Imagination IP are used by billions of people across the globe in their smartphones, cars, homes, and workplaces. We need your skills to help us continue to deliver technology that will impress the industry and our customers alike, ensuring that people everywhere can enjoy smarter and faster tech than ever before. So come join us if you're wanting that something more Bring your talent, curiosity and expertise and we’ll help you do the rest. You’ll be part of one of the world’s most exciting companies who are one of the leaders in semiconductor IP solutions. As a part of our team, you can help us transform, innovate, and inspire the lives of millions through our technology. Additional information If you encounter accessibility barriers in the application process or if you have access needs and require support or adjustments to participate equitably in the recruitment process, please email recruitment@imgtec.com.

Meta is hiring ASIC EDA Infrastructure Engineers within our Infrastructure ASIC organization. EDA Infrastructure Engineers are individuals with experience in EDA flow and methodology, CAD/automation and ASIC infrastructure to build efficient System on Chip (SoC) and IP for data center applications. ASIC Engineer, EDA Infrastructure Responsibilities: Front End implementation flow development and support Internal tools development and automation to help improve productivity across ASIC design cycles including but not limited to RTL generation tools, memory selection automation, register generation, filelist generation Manage the internal EDA license requests, installation and license forecast as well as EDA tool installation and maintenance Work with internal infrastructure team on compute grid, storage management and job scheduling architecture, efficiency and maintenance Work with internal infrastructure team on adapting Meta infrastructure to ASIC design solutions, including but not limited to Source Control Management, Continuous Integration, data management and reporting RTL2GDS flow development and support Physical Design implementation flow development and support Minimum Qualifications: Knowledge of front-end and back-end ASIC tools and flows Experience with RTL design using SystemVerilog or other HDL 8+ years of experience with EDA tools and scripting languages (Python, Tcl) used to build tools and flows for complex environments Experience with ASIC EDA infrastructure (compute, storage, job scheduling) management, maintenance and support Experience with developing and supporting solutions for ASIC design environment and infrastructure Experience with communicating across functional internal teams and with vendors Successful candidates must remain in role in the same team in India for a minimum period of 24 months before being eligible for transfer to another role, team or location Preferred Qualifications: Experience setting up EDA infrastructure from scratch User experience and customer oriented solutions About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Join Qualcomm's design verification team in verifying the Digital Low Power IPs for exciting products targeted for 5G, AI/ML, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle (including Functional, Low Power Verification, Gate Simulation, Formal Verification) from system-level concept to tape out and post-silicon support. Responsibilities: Define pre-silicon and post-silicon testplans based on design specs and using applicable standards working closely with design team. Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Low power verification, Formal verification and Gate level simulation to ensure high design quality. Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure. Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful IP level verification, integration into subsystem and SoC, and post-silicon validation. Minimum Qualifications: Master's/Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field. 8+ years ASIC design verification, or related work experience. Knowledge of a HVL methodology like SystemVerilog/UVM. Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others. Preferred Qualifications: Experience with Low power design verification, Formal verification and Gate level simulation. Knowledge of standard protocols such as Power Management Flows, PCIe, USB, MIPI, LPDDR, etc. will be a value add Experience in scripting languages (Python, or Perl). Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Minimum qualifications: Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or related field, or equivalent practical experience. 5 years of experience with ML/AI frameworks and libraries (e.g., TensorFlow, PyTorch, scikit-learn). Experience with hardware description languages (e.g., Verilog, SystemVerilog, VHDL). Experience with applying ML/AI techniques. Preferred qualifications: Experience with ML/AI applications in hardware design, verification and Low Power (e.g., formal verification with ML, coverage closure with ML). Experience with verification methodologies (UVM, OVM). Experience in data preprocessing and feature engineering, hardware architecture and microarchitecture. Experience with simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa). Excellent programming skills in Python or C++. About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Research, design, and implement ML/AI algorithms techniques for various verification tasks, including test case generation, coverage analysis, bug prediction, and performance optimization. Develop and maintain tools and scripts for data collection, preprocessing, model training, and evaluation. Analyze large datasets of simulation results, logs, and other verification data to identify patterns and trends. Build and train ML models for various verification applications, such as anomaly detection, pattern recognition, and prediction. Evaluate model performance and iterate to improve accuracy and efficiency. Participate in verification planning and develop test plans that incorporate ML/AI-driven techniques. Execute verification tests and analyze results to identify bugs and coverage gaps. Develop and maintain verification tools and scripts to automate verification tasks. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form . Show more Show less

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS SILICON DESIGN ENGINEER The Role The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience. Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned engineer with a passion for pushing the boundaries of technology. With 8-15 years of experience, you bring a wealth of knowledge in software architecture and leadership. You excel in C/C++ software development, and your strong background in design patterns, data structures, and algorithms sets you apart. You thrive in multi-threaded and distributed code environments, and your familiarity with ASIC design flow and EDA tools is second to none. Your expertise in Verilog, SystemVerilog, and VHDL HDL, coupled with your experience in Unix/Linux platforms, makes you a valuable asset. You are well-versed in developer tools like gdb and Valgrind, and you understand the importance of source code control tools such as Perforce. Your analytical and problem-solving skills are top-notch, and you are always eager to learn and explore new technologies. As a highly enthusiastic and energetic team player, you are ready to go the extra mile to achieve success. What You’ll Be Doing: Designing, developing, and troubleshooting core algorithms for word-level synthesis. - Collaborating with local and global teams to enhance synthesis QoR, performance, and logic interference. - Engaging in pure technical roles focused on software development and architecture. - Implementing multi-threaded and distributed code solutions. - Utilizing your knowledge of ASIC design flow and EDA tools to drive innovation. - Leveraging your expertise in Verilog, SystemVerilog, and VHDL HDL to develop cutting-edge solutions. The Impact You Will Have: Driving technological innovation in chip design and verification. - Enhancing the performance and quality of synthesis tools used globally. - Solving complex logic interference problems to improve design accuracy. - Contributing to the development of high-performance silicon chips and software content. - Collaborating with cross-functional teams to achieve project milestones. - Pioneering new software architectures that set industry standards. What You’ll Need: Strong hands-on experience in C/C++ based software development. - Deep understanding of design patterns, data structures, algorithms, and programming concepts. - Familiarity with multi-threaded and distributed code development. - Knowledge of ASIC design flow and EDA tools and methodologies. - Proficiency in Verilog, SystemVerilog, and VHDL HDL. Who You Are: Highly enthusiastic and energetic team player with excellent communication skills. - Strong desire to learn and explore new technologies. - Effective problem-solver with a keen analytical mind. - Experienced in working on Unix/Linux platforms. - Adept at using developer tools such as gdb and Valgrind. The Team You’ll Be A Part Of: You will be part of the word-level synthesis team, catering to multiple EDA products. This team focuses on developing innovative solutions to improve synthesis quality of results (QoR), performance, and logic interference. You will work closely with both local and global teams to drive technological advancements and achieve project goals. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned engineer with a passion for pushing the boundaries of technology. With 5 -8 years of experience, you bring a wealth of knowledge in software architecture and leadership. You excel in C/C++ software development, and your strong background in design patterns, data structures, and algorithms sets you apart. You thrive in multi-threaded and distributed code environments, and your familiarity with ASIC design flow and EDA tools is second to none. Your expertise in Verilog, SystemVerilog, and VHDL HDL, coupled with your experience in Unix/Linux platforms, makes you a valuable asset. You are well-versed in developer tools like gdb and Valgrind, and you understand the importance of source code control tools such as Perforce. Your analytical and problem-solving skills are top-notch, and you are always eager to learn and explore new technologies. As a highly enthusiastic and energetic team player, you are ready to go the extra mile to achieve success. What You’ll Be Doing: Designing, developing, and troubleshooting core algorithms for word-level synthesis. - Collaborating with local and global teams to enhance synthesis QoR, performance, and logic interference. - Engaging in pure technical roles focused on software development and architecture. - Implementing multi-threaded and distributed code solutions. - Utilizing your knowledge of ASIC design flow and EDA tools to drive innovation. - Leveraging your expertise in Verilog, SystemVerilog, and VHDL HDL to develop cutting-edge solutions. The Impact You Will Have: Driving technological innovation in chip design and verification. - Enhancing the performance and quality of synthesis tools used globally. - Solving complex logic interference problems to improve design accuracy. - Contributing to the development of high-performance silicon chips and software content. - Collaborating with cross-functional teams to achieve project milestones. - Pioneering new software architectures that set industry standards. What You’ll Need: Strong hands-on experience in C/C++ based software development. - Deep understanding of design patterns, data structures, algorithms, and programming concepts. - Familiarity with multi-threaded and distributed code development. - Knowledge of ASIC design flow and EDA tools and methodologies. - Proficiency in Verilog, SystemVerilog, and VHDL HDL. Who You Are: Highly enthusiastic and energetic team player with excellent communication skills. - Strong desire to learn and explore new technologies. - Effective problem-solver with a keen analytical mind. - Experienced in working on Unix/Linux platforms. - Adept at using developer tools such as gdb and Valgrind. The Team You’ll Be A Part Of: You will be part of the word-level synthesis team, catering to multiple EDA products. This team focuses on developing innovative solutions to improve synthesis quality of results (QoR), performance, and logic interference. You will work closely with both local and global teams to drive technological advancements and achieve project goals. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Join Qualcomm's design verification team in verifying the Digital Low Power IPs for exciting products targeted for 5G, AI/ML, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle (including Functional, Low Power Verification, Gate Simulation, Formal Verification) from system-level concept to tape out and post-silicon support. Responsibilities: Define pre-silicon and post-silicon testplans based on design specs and using applicable standards working closely with design team. Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Low power verification, Formal verification and Gate level simulation to ensure high design quality. Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure. Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful IP level verification, integration into subsystem and SoC, and post-silicon validation. Minimum Qualifications: Master's/Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field. 8+ years ASIC design verification, or related work experience. Knowledge of a HVL methodology like SystemVerilog/UVM. Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others. Preferred Qualifications: Experience with Low power design verification, Formal verification and Gate level simulation. Knowledge of standard protocols such as Power Management Flows, PCIe, USB, MIPI, LPDDR, etc. will be a value add Experience in scripting languages (Python, or Perl). Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3076699 Show more Show less

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell is empowering the global data economy. Whether at the network core or edge, our leadership technologies make it possible for the world’s data to be processed, moved, stored and secured faster and more reliably. With leading intellectual property and deep system‐level knowledge, Marvell's infrastructure semiconductor solutions are transforming the 5G, cloud computing, enterprise and automotive markets of tomorrow. Marvell Compute and Custom Solutions has been at the forefront of developing and delivering leading edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast-growing product lines, Marvell technology is powering the next-generation data processing and workload acceleration platforms for multiple market segments. What You Can Expect Lead DV efforts for blocks, subsystems, and top-level verification. Develop and maintain UVM-based verification environments. Define and review test plans with architecture and design teams. Verify designs using directed and constrained random techniques. Maintain regression, debug failures, and analyze coverage. Drive verification to meet coverage targets. Contribute to next-gen data processing and hardware accelerator verification. Focus on networking domain verification for future solutions. Ensure design closure using innovative and automated techniques. What We're Looking For Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or a related field with 8+ years of professional experience. Strong experience with Verilog, SystemVerilog, and UVM. Expertise in unit and subsystem verification, modern verification concepts. Proficiency in SystemVerilog, C, C++, and scripting (Perl, Tcl, Python preferred). Strong debugging skills and verification flow optimization. Collaborate with design teams on specs, test plans, and verification strategies. Develop and maintain UVM-based testbenches for ASIC SoCs. Execute verification, maintain regressions, and debug failures. Excellent verbal and written communication skills. Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Show more Show less

PMTS Silicon Design Engineer Hyderabad, India Engineering 65769 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ PMTS SILICON DESIGN ENGINEER As a SerDes Verification Architect , you will be responsible for the verification and validation of high-speed SerDes interfaces, including testing data integrity, performance, and protocol compliance. You will work closely with hardware and design teams to ensure that SerDes designs meet the required specifications, operating parameters, and quality standards. Key Responsibilities: Verification of SerDes Designs: Develop and execute verification plans and testbenches for SerDes IPs (Intellectual Property) and subsystems to ensure they meet functional and performance requirements. Testbench Development: Design and implement verification testbenches using industry-standard verification methodologies (e.g., UVM, SystemVerilog, VHDL). Simulation and Debugging: Perform simulations, analyze results, and debug issues related to timing, protocol errors, and other design anomalies in SerDes blocks. Performance Evaluation: Evaluate and validate performance characteristics of SerDes systems including jitter, bit error rates (BER), signal integrity, eye diagrams, and other key metrics. Protocol Compliance Testing: Verify adherence to relevant SerDes protocols such as UCIe , PCIe, Ethernet, USB, DDR, DisplayPort, or custom protocols. Automated Testing: Develop automated regression tests to ensure the robustness and stability of the SerDes design over multiple versions and iterations. Collaboration: Work closely with the design, hardware, and software teams to troubleshoot issues, implement fixes, and verify design changes. Documentation: Create detailed reports and documentation on verification results, test scenarios, and issues found during testing. Verification methodology: Provide feedback for design and verification process improvements and contribute to innovation in verification strategies and methodologies. Experience: 16+ years of experience in SerDes verification or high-speed communication verification. Strong hands-on experience with verification methodologies such as UVM, SystemVerilog, or other simulation-based verification tools. Knowledge of high-speed serial protocols such as UCIe , PCIe, Ethernet, USB, DDR, or custom protocols. Experience in analyzing and interpreting signal integrity issues, jitter, BER, and eye diagrams. Skills: Solid understanding of SerDes architectures, link training, and equalization. Strong debugging skills, with the ability to work across multiple domains (timing, protocol, performance). Familiarity with hardware description languages (HDL) like VHDL or Verilog. Strong analytical, problem-solving, and communication skills. Experience with DDR protocol (e.g., DDR3, DDR4, DDR5) for memory interface verification. Understanding of UCIe protocol and its role in chiplet-to-chiplet communication. Preferred Skills: Experience with Python, Perl, or similar scripting languages for automation. Exposure to high-speed memory interface design and verification, including DDR controller IP verification. Functional coverage, assertions knowledge in SV/UVM. Ability to work in a fast-paced environment and manage multiple verification tasks. Strong team player with good interpersonal and communication skills. #LI-PS1 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Questa Simulation Product It is a core R&D team working on multiple verticals of Simulation. A very energetic and enthusiastic team of motivated individuals. This role is based in Noida. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. We make real what matters! Key Responsibilities : We are looking for a highly motivated software engineer to work in the QuestaSim R&D team of the Siemens EDA Development responsibilities will include core algorithmic advances and software design/architecture. You will collaborate with a senior group of software engineers contributing to final production level quality of new components and algorithms and to build new engines and support existent code. Self-motivation, self-discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. Are you excited to know more about this Role ? Job Qualification: An ideal candidate should have skills below: B.Tech or M.Tech in Computer Science & Engineering (CSE), Electrical Engineering (EE), or Electronics & Communication Engineering (ECE) from a reputable engineering institution having 2-5 years of experience. Strong knowledge of C/C++, algorithms, and data structures. Candidate having worked in Design Verification domain who are well versed with System Verilog & UVM is a plus. Familiarity with compiler concepts and optimizations. Experience with UNIX and/or LINUX platforms is essential. Excellent problem-solving and analytical skills. Self-motivated with the ability to work independently and guide others towards successful project completion. We are not looking for superheroes, just super minds! Having the below skills will be an added advantage: Strong understanding of basic digital electronics concepts. Familiarity with machine learning (ML) and artificial intelligence (AI) algorithms, particularly their implementation in data-driven tasks. Proficiency in hardware description languages such as Verilog, SystemVerilog, and VHDL. Experience with parallel algorithms and job distribution techniques. Exposure to simulation or formal verification methodologies is a plus. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday #DVT Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and skilled R&D Engineer with a deep understanding of system verification. You are enthusiastic about developing cutting-edge verification solutions for high-performance computing, data centers, mobile/client devices, automotive systems, and IoT segments. Your experience in architecting and building SystemVerilog UVM-based verification components, coupled with your expertise in cache coherency protocols and functional verification, makes you an ideal candidate for this role. You are a team player with excellent problem-solving abilities, strong analytical skills, and a keen attention to detail. Your background in verification IP development and your programming prowess in languages like Perl, Python, and Shell scripting set you apart as a valuable asset to our team. What You’ll Be Doing: Responsible for functional verification involving coherent and non-coherent IP designs. Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. Developing verification plans and driving functional coverage-driven verification closure of real designs. Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You’ll Need: B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 5-8 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 4-8 years of relevant experience. Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. In-depth understanding of cache coherency protocols such as Protocol experience: Should have experience in any of the protocols, UCIe/PCIe/CXL/Unipro/USB/MIPI/HDMI/Ethernet/DDR/LPDDR/HBM memory protocol Experience in creating verification plans and achieving functional coverage-driven verification closure of real designs. Proficiency in writing scripts using Perl, Python, and Shell scripting. Who You Are: Excellent problem-solving, debugging, and analytical skills. Strong programming skills and familiarity with object-oriented programming concepts. Creative and innovative mindset. Excellent verbal and written communication skills. A collaborative team player with a passion for functional verification. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and skilled R&D Engineer with a deep understanding of system verification. You are enthusiastic about developing cutting-edge verification solutions for high-performance computing, data centers, mobile/client devices, automotive systems, and IoT segments. Your experience in architecting and building SystemVerilog UVM-based verification components, coupled with your expertise in cache coherency protocols and functional verification, makes you an ideal candidate for this role. You are a team player with excellent problem-solving abilities, strong analytical skills, and a keen attention to detail. Your background in verification IP development and your programming prowess in languages like Perl, Python, and Shell scripting set you apart as a valuable asset to our team. What You’ll Be Doing: Responsible for functional verification involving coherent and non-coherent IP designs. Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. Developing verification plans and driving functional coverage-driven verification closure of real designs. Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You’ll Need: B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 5-8 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 4-8 years of relevant experience. Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. In-depth understanding of cache coherency protocols such as Protocol experience: Should have experience in any of the protocols, UCIe/PCIe/CXL/Unipro/USB/MIPI/HDMI/Ethernet/DDR/LPDDR/HBM memory protocol Experience in creating verification plans and achieving functional coverage-driven verification closure of real designs. Proficiency in writing scripts using Perl, Python, and Shell scripting. Who You Are: Excellent problem-solving, debugging, and analytical skills. Strong programming skills and familiarity with object-oriented programming concepts. Creative and innovative mindset. Excellent verbal and written communication skills. A collaborative team player with a passion for functional verification. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and skilled R&D Engineer with a deep understanding of system verification. You are enthusiastic about developing cutting-edge verification solutions for high-performance computing, data centers, mobile/client devices, automotive systems, and IoT segments. Your experience in architecting and building SystemVerilog UVM-based verification components, coupled with your expertise in cache coherency protocols and functional verification, makes you an ideal candidate for this role. You are a team player with excellent problem-solving abilities, strong analytical skills, and a keen attention to detail. Your background in verification IP development and your programming prowess in languages like Perl, Python, and Shell scripting set you apart as a valuable asset to our team. What You’ll Be Doing: Responsible for functional verification involving coherent and non-coherent IP designs. Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. Developing verification plans and driving functional coverage-driven verification closure of real designs. Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You’ll Need: B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 5-8 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 4-8 years of relevant experience. Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. You will be responsible for functional verification involving coherent and non-coherent IP designs. Proficiency in writing scripts using Perl, Python, and Shell scripting. Who You Are: Excellent problem-solving, debugging, and analytical skills. Strong programming skills and familiarity with object-oriented programming concepts. Creative and innovative mindset. Excellent verbal and written communication skills. A collaborative team player with a passion for functional verification. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and skilled R&D Engineer with a deep understanding of system verification. You are enthusiastic about developing cutting-edge verification solutions for high-performance computing, data centers, mobile/client devices, automotive systems, and IoT segments. Your experience in architecting and building SystemVerilog UVM-based verification components, coupled with your expertise in cache coherency protocols and functional verification, makes you an ideal candidate for this role. You are a team player with excellent problem-solving abilities, strong analytical skills, and a keen attention to detail. Your background in verification IP development and your programming prowess in languages like Perl, Python, and Shell scripting set you apart as a valuable asset to our team. What You’ll Be Doing: Responsible for functional verification involving coherent and non-coherent IP designs. Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. Developing verification plans and driving functional coverage-driven verification closure of real designs. Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You’ll Need: B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 5-8 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 4-8 years of relevant experience. Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. In-depth understanding of cache coherency protocols such as Protocol experience: Should have experience in any of the protocols, UCIe/PCIe/CXL/Unipro/USB/MIPI/HDMI/Ethernet/DDR/LPDDR/HBM memory protocol Experience in creating verification plans and achieving functional coverage-driven verification closure of real designs. Proficiency in writing scripts using Perl, Python, and Shell scripting. Who You Are: Excellent problem-solving, debugging, and analytical skills. Strong programming skills and familiarity with object-oriented programming concepts. Creative and innovative mindset. Excellent verbal and written communication skills. A collaborative team player with a passion for functional verification. Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Lead Software Engineer Location: Noida Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success. Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests. You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day. Job Responsibilities & Skills Knowledge of at least one industry standard protocols preferably: Ethernet, Automotive Ethernet / Time Sensitive Networking (TSN), Automotive protocols like CAN, LIN, Flexray. Strong C and C++ development skills with a good understanding of object-oriented design. Hands on experience on HDLs like Verilog/SystemVerilog. Knowledge on transactor development and emulation flow is an added advantage. UVM SV knowledge is an added advantage. Passionate to learn and explore new technologies and demonstrates good analysis and problem-solving skills. Education And Experience B. Tech /BE/M.Tech / ME with 3 to 6 years of relevant experience. Behavioral Skills Required. Must possess strong written, verbal and presentation skills. Ability to establish a close working relationship with both customer peers and management. Explore what’s possible to get the job done, including creative use of unconventional solutions. Work effectively across functions and geographies. Push to raise the bar while always operating with integrity. We’re doing work that matters. Help us solve what others can’t. Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The person should be an Electrical, Electronics or Computer Science Engineer with very good understanding of HDLs (Verilog and/ or VHDL). Prior experience in simulation/emulation using these languages. He/ she should have a good working knowledge of EDA tools (Cadence/ Others) with focus towards debugging design/ verification problems using these tools. Experience in process automation with scripting. Experience with SystemVerilog, C++, UVM. Experience with Functional Verification of complex digital systems, e.g. SoC Verification, with a Hardware Verification Language (HVL) like SystemVerilog. Experience designing and implementing complex functional verification environments is required. Knowledge of protocols like PCIe, USB3/4, DP an added advantage. We’re doing work that matters. Help us solve what others can’t. Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position: Lead Hardware Engineer - DFT IP R&D Location: Noida Experience: 4-6 Years Job Description Cadence Design Systems is looking for a highly motivated software and hardware engineer to work as a member of the R&D staff on Cadence’s MODUS DFT software solution. MODUS is a complete product that encompasses Design for Test Solution for Achieving High Coverage, Reduced Test Time, and Superior PPA. The product breadth means we are looking for skilled and motivated candidates with backgrounds in RTL design, DFT architecture, computer architecture, verification, RTL compilation, placement, static timing analysis, power analysis, routing, extraction, and optimization. You will be part of a team responsible for creating the innovative technologies required for technology leadership in the DFT space. This position will encourage building of a solid foundation in logic circuits and gentle entry into larger DFT IP tool development. Development responsibilities include designing, developing, troubleshooting, debugging and supporting the MODUS software product. Job Responsibilities You will play a key role in developing cutting-edge design-for-testability (DFT) tools, contributing to improved usability and quality through feature enhancement and rigorous verification. The role’s day to day responsibilities cover: Designing and verifying Verilog/SystemVerilog/UVM RTL and test benches for DFT IP features, including new DFT IPs, full scan, compressed/uncompressed scan, memory BIST, JTAG, IEEE 1500, and boundary scan at block and SoC levels. Providing R&D support to application and product engineers, including problem analysis, debugging, and the development of new features to optimize synthesis results for timing, area, and power. There is a significant research element to the work that Cadence does that is truly innovative; we don’t know what the answers are when we start out! Mentoring and support will be provided to the successful candidate to both enable contribution to the large EDA problem domain and to develop their problem-solving skills into professional engineering skills. Job Qualifications Proficient in RTL design using Verilog and SystemVerilog. In-depth knowledge of front-end EDA tools (Verilog/SV simulators, linters, CDC checkers). Experience with SystemVerilog assertions, checkers, and advanced verification techniques. Knowledge of scripting languages, particularly Perl or Python is highly desirable. Knowledge of DFT methodologies is a plus. Strong foundational knowledge of data structures and algorithms. Familiarity with synthesis, static timing analysis (STA). Excellent written and verbal communication and presentation skills. Experience and understanding of EDA tool development concepts is a plus. Position Qualifications M.Tech, M.E, B.Tech, B.E. in EE/ECE/CS or Equivalent Good understanding of Digital Electronics. Prior knowledge of Verilog/System Verilog and EDA tools required. We’re doing work that matters. Help us solve what others can’t. Show more Show less

Are you ready to take the next step in your career and contribute to cutting-edge ASIC and IP/SoC development? We are looking for an experienced Design Engineer to join our team in Hyderabad. This is an exciting opportunity to work with a talented team on high-impact projects, pushing the boundaries of digital design in a collaborative and fast-paced environment. As a key technical contributor, you will work closely with ASIC engineering management to define and implement digital IP/SoC designs, and integrate these with third-party designs into customer ASICs and SoCs. You’ll be part of a multi-site development team, ensuring the delivery of high-quality designs that meet customer requirements and solving complex technical challenges. Key Responsibilities: Design & Implementation: Specify, micro-architect, implement, and perform design verification for complex RTL IP blocks, from basic SoC building blocks to advanced video processing and encoding/decoding logic. IP Development Cycle: Take part in the full lifecycle of IP development—from customer concept to backend layout and silicon validation. Collaboration: Work closely with SoC architects to ensure designs align with project requirements and integrate seamlessly with the rest of the SoC. Technical Guidance: Provide technical advice and solutions to design, verification, physical design, silicon validation, and production test teams. Customer & Team Engagement: Analyse customer requirements and implement functional digital designs and integration flows for complex SoCs. Provide support for customer-facing technical discussions. Tool & Script Development: Develop, maintain, and deploy proprietary scripts and tools for ASIC/SoC design and database management. Leverage industry-leading EDA tools for design quality assurance, power optimisation, and synthesis/timing analysis. Continuous Learning: Stay up-to-date with the latest advances in engineering technologies and methodologies to maintain our competitive edge. Mentorship: Coach junior engineers and support them in all aspects of design activities, including coding, synthesis, debug, DFT, and backend integration. Technical Publications: Contribute to technical white papers, and provide sales support as part of a collaborative team. Key Relationships: Internal: Collaborate with Engineers, Senior Engineers, Principal Engineers, Project Managers, Sales, Finance, and HR teams. External: Technical communication with customers (minimal), and liaising with EDA Tool Vendors, Foundries, and Assembly Houses. What We're Looking For: Qualifications: Essential: Degree/Masters or PhD in Electrical Engineering, Computer Science, or a related field. Typically, 5+ years of relevant experience in digital design and IP/SoC development. Desirable: A Masters or PhD in a related subject with practical experience of 5+ years. Skills & Experience: Essential: Expertise in IP design, implementation, and verification. Strong knowledge of RTL synthesis, performance, and power analysis. In-depth understanding of digital design concepts and problem-solving capabilities. Proficient in HDL coding (VHDL, Verilog, SystemVerilog). System design knowledge, including clock domain management, reset schemes, and power management. Experience with SoC level verification (HW/SW co-verification, multi-mode simulation, gate-level simulation). Experience with design checking tools (Lint, CDC, LEC). Strong communication skills and ability to provide technical guidance to junior engineers. Desirable: Familiarity with ARM processor subsystems, video processing, bus protocols (AXI/AHB/ACE). Experience with low power design methodology (UPF/CPF) and synthesis/timing analysis. Experience with Tcl, Perl, Python, SystemC, IPXACT, and database management. Familiarity with Linux software frameworks. Attributes: Self-motivated with the ability to work independently and as part of a team. Strong problem-solving skills and ability to adapt quickly to changing priorities. Excellent attention to detail and time management skills. A fast learner who thrives in a dynamic, collaborative environment. Show more Show less

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: General Summary: Join Qualcomm’s Wireless IP team to design and develop cutting-edge RTL for next-generation cellular and Wi-Fi modem IPs used in mobile, wearable, and IoT platforms. You will work on high-performance, low-power digital designs across the full VLSI development cycle—from architecture and micro-architecture to RTL implementation and SoC integration. This role offers the opportunity to collaborate with global teams and contribute to market-leading wireless solutions. Key Responsibilities: Design and implement RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog. Develop micro-architecture specifications and deliver high-quality, synthesizable RTL. Integrate complex subsystems into SoC environments and support design convergence. Collaborate with system architects, verification, SoC, software, DFT, and physical design teams. Apply low-power design techniques including clock gating, power gating, and multi-voltage domains. Analyze and optimize for performance, area, and power. Ensure protocol compliance and performance of interconnects, buses (AXI, AHB, APB), and bridges. Conduct CDC and lint checks using tools like Spyglass and resolve waivers. Participate in post-silicon debug and bring-up activities. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Preferred Skills & Experience: 2–15 years of experience in digital front-end ASIC/RTL design. Strong expertise in Verilog/SystemVerilog RTL coding and micro-architecture development. Familiarity with wireless protocols such as IEEE 802.11 (a/b/g/n/ac/ax/be), LTE, or 5G NR is highly desirable. Solid understanding of bus protocols (AXI, AHB, APB) and bridge logic. Experience with wireless modem IPs or similar high-performance digital blocks is a plus. Familiarity with low-power design methodologies and CDC handling. Hands-on experience with tools like Spyglass, 0-in, Design Compiler, PrimeTime, and simulation environments. Exposure to post-silicon debug and SoC integration challenges. Strong documentation and communication skills. Self-motivated with a collaborative mindset and ability to work with minimal supervision. Minimum Qualifications: Bachelor’s or Master’s degree in Electronics, VLSI, Communications, or related field. Proven experience in RTL design and SoC development. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3076712 Show more Show less

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: General Summary: Join Qualcomm’s cutting-edge hardware engineering team to drive the design verification of next-generation SoCs, with a focus on wireless technologies including WLAN (IEEE 802.11). You will work on IP and subsystem-level verification, collaborating with cross-functional teams to deliver high-performance, low-power silicon solutions. A strong understanding of on-chip buses and bridges is essential to ensure seamless integration and performance across subsystems. Key Responsibilities: Develop and execute verification plans for complex SoC designs and IP blocks. Architect and implement testbenches using SystemVerilog and UVM/OVM methodologies. Perform RTL verification, simulation, and debugging. Collaborate with design, architecture, and software teams to ensure functional correctness. Contribute to IP design reviews and sign-off processes. Support post-silicon validation and bring-up activities. Analyze and verify interconnects, buses (e.g., AMBA AXI/AHB/APB), and bridges for performance and protocol compliance. Conduct CPU subsystem verification including coherency, cache behavior, and interrupt handling. Perform power-aware verification using UPF/CPF and validate low-power design intent. Execute performance verification to ensure bandwidth, latency, and throughput targets are met. Preferred Skills & Experience: 2–15 years of experience in digital design and verification. Deep understanding of bus protocols and bridge logic, including hands-on experience with AXI, AHB, and APB. Experience with CPU subsystem verification and performance modeling. Familiarity with wireless protocols (IEEE 802.11 a/b/g/n/ac/ax/be) is a plus. Proficiency in SystemVerilog, UVM/OVM, Verilog, and scripting languages (Perl, Tcl, Python). Experience with power-aware verification methodologies and tools (e.g., UPF, CPF). Familiarity with performance verification techniques and metrics. Exposure to tools like Clearcase/Perforce and simulation/debug environments. Strong analytical, debugging, and communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications: Bachelor’s or Master’s degree in Electrical/Electronics Engineering, Computer Science, or related field. Relevant experience in hardware design and verification. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3076713 Show more Show less

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SILICON DESIGN ENGINEER 1 THE ROLE: As a Silicon Design Engineer, you will work with formal experts and designers to verify formal properties and drive convergence. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Drive formal verification for the block and write formal properties and assertions to verify the design Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the design Write tests, sequences, and testbench components in SystemVerilog and UVM along with formal to achieve verification of the design Responsible for verification quality metrics like pass rates, code coverage and functional coverage PREFERRED EXPERIENCE: Project level experience with design concepts and RTL implementation for same Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics Good understanding of computer organization/architecture ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 11861 Date posted 06/03/2025 Description Candidate will be part of TCM Front End team. Design, develop, troubleshoot the core algorithms used in TCM Front End tool Design and develop standard and customized features / checks in TCM FE for seamless consumption of VCS OM. Will be working with other local and global teams of TCM and VC SpyGlass Design and development of state-of-the-art EDA tools involving development of new and innovative algorithms. Create test cases to test the developed feature. Skills Required Strong knowledge of Front-end compilers and their flow Ability to develop new software architecture and good leadership skills. Fluent in C/C++ with extensive work experience in data-structures and algorithms. Good knowledge of Verilog, SystemVerilog & VHDL HDL. Excellent algorithm analysis skills and a good knowledge of data structures. Familiarity with ASIC design flow and the EDA tools and methodologies used therein. Familiarity with multi-threaded and distributed code development. Self-motivation, self- discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. Quality focus - one who believes in quality and wants to make a difference. Experience of production code development on Unix/Linux platforms. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.