526 Systemverilog Jobs - Page 4

As a VLSI Design Engineer at Kinara, you will be part of a dynamic team focused on edge AI technology, pushing the boundaries of what's achievable in machine learning and artificial intelligence. You will contribute to the development of state-of-the-art AI processors and high-speed interconnects, ensuring unmatched performance, power efficiency, and scalability to meet the demands of modern AI applications. Your role will involve working on cutting-edge semiconductor projects, requiring a blend of technical expertise, problem-solving skills, and collaborative teamwork. Your responsibilities will include defining micro-architecture and creating detailed design specifications, developing RTL code based on system-level requirements using Verilog, VHDL, or SystemVerilog, implementing complex digital functions and algorithms in RTL, and executing comprehensive test plans to verify RTL designs. You will optimize designs for power, performance, and area constraints, conduct simulation and debugging activities to ensure design accuracy, collaborate with verification engineers to develop test benches and validate RTL against specifications, and apply your strong understanding of digital design principles and concepts. To excel in this role, you should possess proficiency in writing and debugging RTL code, experience with synthesis, static timing analysis, and linting tools, familiarity with scripting languages like Python, Perl, or TCL for automation, and expertise in processor subsystem design, interconnect design, or high-speed IO interface design. A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, along with 5+ years of experience in RTL design and verification, is required. Proven experience in digital logic design using Verilog, VHDL, or SystemVerilog, familiarity with simulation tools such as VCS, QuestaSim, or similar, and hands-on experience with RTL design tools like Synopsys Design Compiler and Cadence Genus is preferred. At Kinara, we offer an innovative environment where technology experts and mentors collaborate to tackle exciting challenges. We believe in sharing responsibilities and valuing diverse viewpoints. If you are passionate about making a difference in the field of edge AI technology, we invite you to join our team and contribute to creating a smarter, safer, and more enjoyable world. Your application is eagerly awaited as we look forward to reviewing your qualifications and experiences. Make your mark with us at Kinara!,

As a VLSI Mentor / Guest Faculty specializing in Advanced Digital Systems & Low Power Design at Spandsons Horizon Engineering, you play a crucial role in guiding 5th, 6th, and 7th-semester B.E./B.Tech students in advanced VLSI concepts and practical applications. This contract role, based in Salem, offers a unique opportunity to directly influence the academic and career growth of 60 aspiring engineers. Your key responsibilities include delivering engaging sessions covering topics such as Advanced Digital System Design with Verilog HDL and Low Power VLSI Design. You will also provide hands-on guidance for lab assignments and projects using various tools like Xilinx Vivado, ModelSim, LTspice, and more. Facilitating interactive learning and ensuring alignment with the semester curriculum are essential aspects of this role. To qualify for this position, you need a minimum of 4-5 years of industry experience in VLSI design, proficiency in relevant EDA tools and hardware platforms, excellent communication skills, and a passion for teaching and mentoring. The program details include a total of approximately 60 students, with sessions scheduled on Thursdays and Fridays for 12 hours per week starting on July 24th & 25th. The program will run for Semesters 5, 6, and 7. In addition to a comprehensive program, benefits such as accommodation, food, and the opportunity to impact the next generation of VLSI engineers are provided. Join us at Spandsons Horizon Engineering and be part of a forward-thinking academic institution.,

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. As a new graduated Silicon Validation Engineer, you are a dedicated and innovative professional with a passion for advancing technology. You have a strong background in electronics engineering and a keen eye for detail. You thrive in collaborative environments, working seamlessly with R&D teams to drive the success of cutting-edge projects. Your problem-solving skills are exceptional, and you are adept at troubleshooting complex systems and equipment. With a commitment to continuous learning, you stay updated with the latest industry trends and technologies. You are proactive, self-motivated, and ready to take on new challenges in a dynamic and fast-paced environment. Developing test strategies for validation of silicon devices in conjunction with R&D engineering teams. Writing and implementing test programs for National Instruments LabVIEW-based equipment. Performing hands-on testing of devices using National Instruments LabVIEW-based equipment in the Plymouth lab facility. Designing and verifying SystemVerilog RTL targeting FPGA implementations. Creating schematics for test boards and fixtures. Recording and analyzing product test results and equipment logs. Ensuring the reliability and performance of Synopsys PVT Sensors across various applications. Contributing to the development of cutting-edge on-chip sensor products targeting the latest technology processes. Enhancing product quality through meticulous validation and testing procedures. Collaborating with a skilled team of engineers to drive innovation and technological advancements. Providing critical insights through data analysis to inform product improvements. Supporting the optimization of performance, power, and other requirements for a diverse range of applications. University degree/masters or similar, either in Electronics Engineering or related field. Some background of FPGA design using HDL would be beneficial, i.e. SystemVerilog. Basic understanding of the design of digital and analogue circuits for device validation and testing. Elementary understanding of component level device test methods. Some experience of PCB schematic capture using suitable CAD software. A familiarity with programming and scripting skills in one or more of VB script, python, tcl & bash. Ability to do basic statistical and data analysis for silicon devices and test results. You are an analytical thinker with excellent problem-solving abilities. You have strong communication skills and work effectively within a team. Your attention to detail ensures high-quality results, and you are driven by a commitment to continuous improvement. You are adaptable, proactive, and capable of managing multiple tasks efficiently. You will join a dynamic R&D team focused on the development of Synopsys PVT Sensors. This team is comprised of skilled engineers dedicated to pushing the boundaries of technology and delivering innovative solutions. Collaboration and knowledge sharing are key aspects of the teams success, fostering an environment where creativity and technical excellence thrive. We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.,

The company Eximietas Design is currently seeking an experienced and highly skilled RTL Micro Architect to join their team in Bangalore. As the RTL Micro Architect, you will be responsible for defining and implementing the microarchitecture of advanced semiconductor designs. Your role will involve working on challenging RTL design tasks, collaborating with various teams, and contributing to the development of high-performance and power-efficient solutions. Your key responsibilities will include defining microarchitecture specifications for complex SoC designs, leading RTL design and implementation using Verilog/SystemVerilog, collaborating with different teams to ensure project success, performing design trade-off analysis, developing design methodologies for efficiency improvement, mentoring junior engineers, participating in design reviews, and providing technical leadership. To qualify for this position, you should have at least 8 years of hands-on experience in RTL design and microarchitecture development, strong expertise in RTL design using Verilog/SystemVerilog and logic synthesis, proficiency in microarchitecture design for complex SoCs, experience with low-power design techniques, familiarity with advanced process nodes, strong scripting skills in Tcl, Python, or Perl, excellent problem-solving skills, and effective communication and leadership skills. In return, Eximietas Design offers you the opportunity to work on cutting-edge semiconductor designs and innovative technologies, a collaborative work environment, competitive compensation and benefits package, and professional growth and development opportunities. If you are interested in this position, please share your updated resume with maruthiprasad.e@eximietas.design.,

You are a FPGA design engineer with at least 5 years of experience, located in Vadodara, India. Your main responsibility is to implement control logic state machines and DSP algorithms in FPGA fabric for high throughput systems. You should possess excellent troubleshooting and debugging skills for both simulation and in-circuit scenarios. Your expertise should include: - Strong knowledge of digital design involving multiple clock domains - RTL design in Verilog and System-Verilog - Creating micro-architecture from high-level specifications - Functional simulation using ModelSIM or similar tools - FPGA design and synthesis, map and route flow, pin assignments, attribute assignments, resource fixing, and design partitioning - Targeting designs for Intel(Altera) or Xilinx FPGAs using Quartus Prime or Vivado - IP creation and parametrization using Vivado or Quartus - Debugging using ChipScope/SignalTap and lab bench oscilloscopes/protocol analyzers - Understanding of static timing analysis and timing closure using SDC - Collaborating with a cross-functional, global team of hardware designers, software engineers, verification and validation engineers - Leading teams to successful project completion within deadlines - Strong problem-solving skills It would be beneficial if you also have expertise in: - Knowledge of TCL scripting and Python - Transceivers and PHY - Power estimation and resource utilization estimation - Soft-processor cores like Microblaze or Nios-II - Understanding of Digital Signal Processing concepts - Proficiency in Matlab or Python for algorithm design - Familiarity with embedded systems/C/C++ About A&W Engineering Works: A&W Engineering Works is committed to developing and deploying innovative solutions to real-world problems. The company specializes in developing complete systems from front-end sensors to back-end applications, covering analog, digital signal processing, and algorithmic data and control paths. The team at A&W Engineering Works has a wide range of expertise in hardware, software, mechanical engineering, and systems development, aiming to solve complex problems efficiently with innovative development techniques and fast prototyping. To apply for this position, please send an email to [email protected] with your resume and cover letter attached, and remember to include the job title in the subject line.,

As a Senior Hardware Design Engineer at Agnisys, you will have the opportunity to work on high-tech semiconductor products by joining our R&D team. We provide a progressive and innovation-driven environment that promotes constant learning, which is crucial for personal and professional growth. Basic Requirements: - A B.Tech degree in Electronics and Communication Systems - Proficiency in Verilog, VHDL, SystemVerilog & C - Experience with FPGA, EDA Tools, Linux, Perl, and Tcl - Excellent communication skills - Ability to work independently with minimal supervision and collaboratively within a team - Strong multi-tasking skills - Self-motivated with a solid team spirit Job Responsibilities: - Design, plan, document, and develop new hardware products from initial requirements to production-ready prototypes - Maintain existing designs and create new variants to incorporate new features and manage component end-of-life issues - Collaborate with Hardware team members, Product Management, Software Engineering, and Manufacturing to deliver reliable and standards-compliant products About Agnisys: Agnisys Inc. is a prominent supplier of Electronic Design Automation (EDA) software aimed at addressing complex design and verification challenges in system development. Our products facilitate a unified specification-driven development flow, enabling users to describe registers and sequences for SoC and IP projects and automatically generate RTL design, UVM testbenches, C/C++ embedded code, and documentation. This approach accelerates design, verification, firmware, and validation processes. Leveraging patented technology and user-friendly interfaces, our specification automation tools enhance productivity, efficiency, and accuracy in system design and verification. Established in 2007, Agnisys is headquartered in Boston, Massachusetts, with R&D centers in Milpitas, CA, and Noida, India. Location: Noida Job Type: Full-time Schedule: Monday to Friday Work Location: In person,

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Data Centre Engineering Group develops Custom Silicon products tailored for the Data Centre market, focusing on cutting-edge Accelerated Infrastructure solutions for Networking, Switching, Connectivity, and Compute. The team works on high-performance and scalable architectures, ensuring optimized performance, power efficiency, and reliability to meet evolving data center demands. By collaborating across multiple teams, the group delivers best-in-class silicon solutions that drive innovation in next-generation data center applications. What You Can Expect Architect and implement simulation test bench in UVM. Develop and execute test-plans for verifying correctness and performance of the design. Own and debug failures in simulation to root-cause problems Closely work with logic designers of the block being verified for test plan development, execution, debug, coverage closure and gate level simulations What We're Looking For Bachelor’s degree in CS/EE with 13–15 years of relevant experience, or Master’s degree in CS/EE with 10–12 years of relevant experience Strong background in IP and SoC verification, including methodology and testbench development Proficient in hardware verification languages such as Verilog, SystemVerilog, UVM, and C/C++ Solid understanding of verification methodologies: object-oriented programming, white-box/black-box testing, directed/random testing, coverage analysis, and gate-level simulations Experience in Unix/Linux environments; scripting skills in Shell, Perl, or Python are a plus Strong analytical and problem-solving skills Ability to manage multiple tasks in a fast-paced environment Excellent communication, interpersonal, and teamwork skills Capable of interfacing effectively at all levels within and outside the organization Proactive in participating in problem-solving and quality improvement initiatives Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Alternate Job Titles: ASIC Verification, Sr. Engineer Sr. Engineer, Digital Verification We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated and innovative engineer with a strong background in high-speed protocols and a keen interest in growing your expertise through verification-related work. You thrive in a collaborative environment, working alongside experienced digital design and verification professionals. With a solid foundation in Verilog, VHDL, and/or SystemVerilog, you are eager to expand your knowledge and apply your skills to state-of-the-art products. Your excellent problem-solving abilities and strong communication skills enable you to identify and address design issues effectively. You are organized, detail-oriented, and capable of managing multiple tasks efficiently. With your passion for learning and exploring new technologies, you are committed to contributing to the success of our projects and the broader goals of Synopsys. What You’ll Be Doing: Identify verification environment requirements from various sources, including specifications, design functionality, and interfaces. Generate verification test plans, environment documentation, and usage documentation. Define, develop, and verify complex UVM verification environments. Evaluate and exercise various aspects of the development flow, including Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics. Identify design problems, propose corrective actions, and address inconsistencies in documented functionality. Collaborate with cross-functional teams to ensure the successful integration and verification of projects. The Impact You Will Have: Ensure the robustness and reliability of our digital designs through meticulous verification processes. Contribute to the development of cutting-edge technologies that power the Era of Smart Everything. Enhance the overall quality and performance of our silicon IP products. Help our customers bring differentiated products to market quickly and with reduced risk. Drive continuous improvements in our verification methodologies and practices. Support the growth and success of Synopsys by contributing to our reputation for innovation and excellence. What You’ll Need: Proven desire to learn and explore new state-of-the-art technologies. Demonstrated proficiency in Verilog, VHDL, and/or SystemVerilog. Experience with scripting languages such as BASH, TCSH, PERL, PYTHON, or TCL is a plus. Understanding of verification methodologies such as UVM is a plus. Strong organizational and communication skills. 3+ years of relevant experience in ASIC digital verification. Who You Are: A passionate and innovative engineer with a strong technical background. Detail-oriented and capable of managing multiple tasks efficiently. Excellent problem-solving abilities and a proactive approach to addressing challenges. Strong communication skills, both written and spoken. A collaborative team player who thrives in a dynamic and fast-paced environment. The Team You’ll Be A Part Of: You will join an experienced and dedicated digital design and verification team focused on developing state-of-the-art products. Our team is committed to excellence and continuous improvement, working collaboratively to achieve our goals. You will have the opportunity to learn from experts in various fields and contribute to the success of our projects. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Job Description Key Responsibilities – AMS Verification Work in Analog Mixed-Signal (AMS) Verification for SoCs, subsystems, and IPs. Hands-on experience with AMS simulation environments using Cadence, Synopsys, or Mentor tools. Solid understanding of analog and mixed-signal circuits, including comparators, op-amps, switched-cap circuits, ADCs/DACs, current mirrors, charge pumps, and regulators. Strong knowledge of Verilog, Verilog-A, Verilog-AMS, and Verilog-D for behavioral modeling. Experience in block-level and chip-level AMS verification, including top-level testbench development, self-checking testbenches, and regression suites. Exposure to SystemVerilog (SV) and UVM from an AMS perspective is a plus. Proficiency in scripting languages such as Python, Perl, TCL, or SKILL for automation. Fluency with Cadence Virtuoso-based analog design flow, including schematic capture, simulator/netlist configuration, and SPICE simulation. Ability to extract, analyze, and document simulation results and present findings in technical reviews. Familiarity with test plan development, AMS modeling, and verification methodologies. Supporting post-silicon validation and correlating measurement data with simulations. Team-oriented, proactive, and able to contribute in a multi-site development environment.

We are seeking a highly skilled SOC Functional Verification Engineer with expertise in UVM, Verilog/SystemVerilog , and AMBA bus protocols . The ideal candidate will have a strong background in SOC and ASIC verification and be capable of independently handling complex testbench environments and verification tasks. Key Responsibilities Develop and execute functional verification plans for SOC/ASIC designs using SystemVerilog and UVM methodologies. Design, develop, and maintain testbenches, scoreboards, and checkers. Write and run directed and random tests, analyze results, and debug functional failures. Collaborate closely with design, architecture, and software teams to ensure comprehensive verification coverage. Implement code and functional coverage metrics and drive improvements. Work with AMBA bus protocols (AXI, AHB, APB) and verify IP-level and SOC-level integrations. Contribute to verification methodology improvements and reusable IP verification components. Required Skills Strong hands-on experience with SystemVerilog/UVM for functional verification. Solid understanding of ASIC/SOC verification flows. Familiarity with AMBA bus protocols (AXI, AHB, APB). Experience with Verilog for RTL understanding and analysis. Proficient in debugging using simulators and waveform viewers (e.g., VCS, ModelSim, Questa). Knowledge of functional coverage and assertions (SVA) is preferred. Experience with version control and scripting (e.g., Python, Perl, Shell) is a plus. Skills: shell,amba bus protocols,dv,axi,perl,systemverilog,amba,asic,python,functional coverage,soc,functional verification,verilog,apb,ahb,assertions,uvm,debugging

Alternate Job Titles: ASIC Verification, Sr. Engineer Sr. Engineer, Digital Verification We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated and innovative engineer with a strong background in high-speed protocols and a keen interest in growing your expertise through verification-related work. You thrive in a collaborative environment, working alongside experienced digital design and verification professionals. With a solid foundation in Verilog, VHDL, and/or SystemVerilog, you are eager to expand your knowledge and apply your skills to state-of-the-art products. Your excellent problem-solving abilities and strong communication skills enable you to identify and address design issues effectively. You are organized, detail-oriented, and capable of managing multiple tasks efficiently. With your passion for learning and exploring new technologies, you are committed to contributing to the success of our projects and the broader goals of Synopsys. What You’ll Be Doing: Identify verification environment requirements from various sources, including specifications, design functionality, and interfaces. Generate verification test plans, environment documentation, and usage documentation. Define, develop, and verify complex UVM verification environments. Evaluate and exercise various aspects of the development flow, including Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics. Identify design problems, propose corrective actions, and address inconsistencies in documented functionality. Collaborate with cross-functional teams to ensure the successful integration and verification of projects. The Impact You Will Have: Ensure the robustness and reliability of our digital designs through meticulous verification processes. Contribute to the development of cutting-edge technologies that power the Era of Smart Everything. Enhance the overall quality and performance of our silicon IP products. Help our customers bring differentiated products to market quickly and with reduced risk. Drive continuous improvements in our verification methodologies and practices. Support the growth and success of Synopsys by contributing to our reputation for innovation and excellence. What You’ll Need: Proven desire to learn and explore new state-of-the-art technologies. Demonstrated proficiency in Verilog, VHDL, and/or SystemVerilog. Experience with scripting languages such as BASH, TCSH, PERL, PYTHON, or TCL is a plus. Understanding of verification methodologies such as UVM is a plus. Strong organizational and communication skills. 3+ years of relevant experience in ASIC digital verification. Who You Are: A passionate and innovative engineer with a strong technical background. Detail-oriented and capable of managing multiple tasks efficiently. Excellent problem-solving abilities and a proactive approach to addressing challenges. Strong communication skills, both written and spoken. A collaborative team player who thrives in a dynamic and fast-paced environment. The Team You’ll Be A Part Of: You will join an experienced and dedicated digital design and verification team focused on developing state-of-the-art products. Our team is committed to excellence and continuous improvement, working collaboratively to achieve our goals. You will have the opportunity to learn from experts in various fields and contribute to the success of our projects. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Category Engineering Hire Type Employee Job ID 12162 Remote Eligible No Date Posted 20/07/2025 Alternate Job Titles: ASIC Verification, Sr. Engineer Sr. Engineer, Digital Verification We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated and innovative engineer with a strong background in high-speed protocols and a keen interest in growing your expertise through verification-related work. You thrive in a collaborative environment, working alongside experienced digital design and verification professionals. With a solid foundation in Verilog, VHDL, and/or SystemVerilog, you are eager to expand your knowledge and your skills to state-of-the-art products. Your excellent problem-solving abilities and strong communication skills enable you to identify and address design issues effectively. You are organized, detail-oriented, and capable of managing multiple tasks efficiently. With your passion for learning and exploring new technologies, you are committed to contributing to the success of our projects and the broader goals of Synopsys. What You’ll Be Doing: Identify verification environment requirements from various sources, including specifications, design functionality, and interfaces. Generate verification test plans, environment documentation, and usage documentation. Define, develop, and verify complex UVM verification environments. Evaluate and exercise various aspects of the development flow, including Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics. Identify design problems, propose corrective actions, and address inconsistencies in documented functionality. Collaborate with cross-functional teams to ensure the successful integration and verification of projects. The Impact You Will Have: Ensure the robustness and reliability of our digital designs through meticulous verification processes. Contribute to the development of cutting-edge technologies that power the Era of Smart Everything. Enhance the overall quality and performance of our silicon IP products. Help our customers bring differentiated products to market quickly and with reduced risk. Drive continuous improvements in our verification methodologies and practices. Support the growth and success of Synopsys by contributing to our reputation for innovation and excellence. What You’ll Need: Proven desire to learn and explore new state-of-the-art technologies. Demonstrated proficiency in Verilog, VHDL, and/or SystemVerilog. Experience with scripting languages such as BASH, TCSH, PERL, PYTHON, or TCL is a plus. Understanding of verification methodologies such as UVM is a plus. Strong organizational and communication skills. 3+ years of relevant experience in ASIC digital verification. Who You Are: A passionate and innovative engineer with a strong technical background. Detail-oriented and capable of managing multiple tasks efficiently. Excellent problem-solving abilities and a proactive approach to addressing challenges. Strong communication skills, both written and spoken. A collaborative team player who thrives in a dynamic and fast-paced environment. The Team You’ll Be A Part Of: You will join an experienced and dedicated digital design and verification team focused on developing state-of-the-art products. Our team is committed to excellence and continuous improvement, working collaboratively to achieve our goals. You will have the opportunity to learn from experts in various fields and contribute to the success of our projects. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Lead Verification Engineer Experience: 7+ years Location: Hyderabad Job Description: Work as a member of a geographically distributed verification team to verify next-generation ASIC and FPGAs Develop testplans, implement testbenches, create testcases, and ensure functional coverage closure Handle regression testing and contribute to verification infrastructure development Develop both directed and random verification tests Debug test failures, identify root causes, and work with RTL and firmware engineers to resolve design defects and test issues Review functional and code coverage metrics, modify or add tests or constrain random tests to meet coverage requirement Collaborate with design, software and architecture teams to verify design under test Preferred Experience: Proficient in IP-level FPGA and ASIC verification Knowledge of PCIe, CXL or other IO protocol is preferred Proficient in Verilog/SystemVerilog, and scripting languages such as Perl or Python Hands-on experience with SystemVerilog and UVM is mandatory Experience in developing UVM-based verification testbenches, processes, and flows Solid understanding of design flow, verification methodology, and general computational logic design and verification About Company ACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise spans the entire technology stack, seamlessly integrating AI and data-driven solutions from Chip to cloud. By choosing ACL Digital, you gain a strategic advantage in navigating the complexities of digital transformation. Let us be your trusted partner in shaping the future.

Responsibilities Be the primary point of contact for IP and SoC functional verification for cross-functional teams. Participate with architecture, design teams, silicon validation, and software teams in defining the overall verification strategy of our SoCs. Develop high-performance and low power hardware to enable Google's continuous innovations in consumer hardware. Minimum qualifications: Bachelor's degree in Computer Science or Electrical Engineering or equivalent practical experience. 5 years of experience in driving/leading functional verification for Intellectual Properties (IPs) and System-on-a-Chip (SoCs). Experience working with System Verilog and Universal Verification Methodology (UVM). Preferred qualifications: Master's degree in Computer Science or Electrical Engineering or equivalent practical experience. Experience leading design verification of an SoC or large ASICs. Experience in different verification techniques and methodologies, including formal, Gate Level Simulation, Unified Power Format based Power simulations, UVM, etc. to achieve bug-free Silicon in complex SoC. Experience in scripting languages (e.g., Python, Perl) for automation and analysis. Experience in driving cross-functional teams for high quality tape-outs.

Role Responsibilities: Plan and develop formal verification strategies for complex digital design blocks. Create properties and constraints using formal verification tools for property verification. Resolve verification challenges and improve methodologies for better results. Architect and implement reusable components to enhance formal verification processes. Job Requirements: Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. 3 years of experience with verification methodologies and languages such as UVM and System Verilog. Experience with designing and maintaining verification test benches and environments.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 3 years of experience in ASIC/SoC development with Verilog/SystemVerilog. Experience in micro-architecture and design of IPs and subsystems. Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Preferred qualifications: Experience with programming languages (e.g., Python, C/C++ or Perl). Experience in SoC designs and integration flows. Knowledge of arithmetic units, processor design, accelerators, bus architectures, fabrics/NoC or memory hierarchies. Knowledge of high performance and low power design techniques. Responsibilities Own implementation of IPs and subsystems. Work with Architecture and Design Leads to understand micro-architecture specifications. Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams. Identify and drive Power, Performance, and Area improvements for the domains.

Role Responsibilities: Verify complex digital design blocks (e.g., GPU, CPU, Image processors) by analyzing design specifications and working with design engineers. Create and enhance constrained-random verification environments using SystemVerilog, UVM, or formal verification techniques with SystemVerilog Assertions (SVA). Write coverage measures for stimulus and corner cases, ensuring thorough testing of the design. Debug tests in collaboration with design engineers to ensure functional correctness and close coverage gaps before tape-out. Job Requirements: Bachelor's degree in Mechanical Engineering, Electrical Engineering, Industrial Engineering, or equivalent practical experience. 3 years of experience with standard GPU workloads like Manhattan/3DMark and knowledge of GPU architecture. Experience with AMBA Bus protocols like AHB/AXI/ACE. Experience in creating verification environments and debugging designs.

Senior SOC Verification Engineer Bangalore, Karnataka, India Date posted Jul 22, 2025 Job number 1848626 Work site Up to 50% work from home Travel 0-25 % Role type Individual Contributor Profession Hardware Engineering Discipline Silicon Engineering Employment type Full-Time Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Cloud Compute Development Organization (CCDO) team is instrumental in defining and delivering silicon solutions for the Cobalt program through hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. CCDO is at the forefront of innovation and application of AI to silicon development workflows. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for an Individual contributor to join the team. Qualifications Required Qualification 10+ years in ASIC verification, with deep expertise in performance validation across IP, subsystem, and SoC levels. Strong background in SystemVerilog, UVM, and simulation tools. Strong C and C++ Coding skills Experience with server-class SoCs, including Intel and ARM architectures. Familiarity with protocols such as PCIe, DDR, AXI, CHI and CXL. Proven track record in leading verification teams and delivering high-quality silicon. Strong analytical and debugging skills, with experience in correlating RTL vs C-model performance. Preferred Qualification Experience in one or more of the following: coherency, caches, fabrics, reset, power management, design for debug (DFD), Double Data Rate (DDR) controllers, and PH, virtualization, interrupts, security, Peripheral Component Interconnect Express (PCIe), Compute Express Link (CXL), Universal Serial Bus (USB), low speed IOs (SPI, I3C, etc.), AXI/CHI protocol bridges or other complex IP/blocks or subsystems Hands-on technical leadership experience such as creating bottom’s up schedules, coordinating work across a team, driving verification closure, or solving cross-team technical problems Experience with verification for multiple product cycles from definition to silicon, including writing test plans, developing tests, debugging failures and coverage signoff Experience in creating, maintaining, or integrating test benches, checkers and stimulus using System Verilog Test Bench (SVTB), Universal Verification Methodology (UVM), Formal Verification and/or C Experience in automating verification processes using Python or another scripting language Publications or presentations in industry forums (e.g., SNUG, User2User). Experience with AI-based verification technologies . Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. Responsibilities Lead performance verification strategy and execution for server-class SOC's in a multi-die simulation environment. Collaborate with SoC/IP architects to define performance limits and resolve debug issues. Develop and manage test plans, model strategies, and infrastructure across various flows including DV, power, and performance. Coordinate with cross-functional stakeholders to manage dependencies, schedules, and deliverables. Drive automation for regression management, post-processing, and streamlined execution. Resolve infrastructure challenges to ensure high-quality, single-step production readiness. Contribute to technical readiness studies for new server product proposals and silicon lifecycle planning. Architect reusable verification environments and system-level use cases for performance validation. Make use of and contribute to industry-leading Generative AI verification tools and flows Deploy project planning methodologies and define verification strategies, resource allocation, and risk mitigation plans Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.  Industry leading healthcare  Educational resources  Discounts on products and services  Savings and investments  Maternity and paternity leave  Generous time away  Giving programs  Opportunities to network and connect Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Cadence Design Systems is seeking a Lead Hardware Engineer for their DFT IP R&D team in Noida with 4-6 years of experience. As a member of the R&D staff, you will be working on Cadence's MODUS DFT software solution, a comprehensive product designed to achieve high coverage, reduced test time, and superior PPA. We are looking for candidates with expertise in various areas such as RTL design, DFT architecture, verification, power analysis, and optimization. This role involves developing cutting-edge DFT tools, designing and verifying RTL and test benches, and providing support to application and product engineers. You will be part of a team responsible for creating innovative technologies in the DFT space. Your responsibilities will include designing, developing, and supporting the MODUS software product. This position offers an opportunity to build a solid foundation in logic circuits and contribute to DFT IP tool development. The role involves enhancing usability and quality through feature enhancement and rigorous verification. You will also provide R&D support, problem analysis, debugging, and develop new features to optimize synthesis results for timing, area, and power. At Cadence, we value innovation and research. The successful candidate will receive mentoring and support to contribute to the EDA problem domain and enhance their problem-solving skills. The ideal candidate should be proficient in RTL design using Verilog and SystemVerilog, have knowledge of front-end EDA tools, SystemVerilog assertions, and advanced verification techniques. Familiarity with scripting languages like Perl or Python, DFT methodologies, and synthesis tools is desirable. Excellent communication skills are essential, along with a strong foundation in data structures and algorithms. Qualifications for this position include an M.Tech, M.E, B.Tech, or B.E. in EE/ECE/CS or equivalent, a good understanding of Digital Electronics, prior knowledge of Verilog/System Verilog, and EDA tools. Join us at Cadence to work on projects that truly matter and help us solve challenges that others can't.,

As a member of the QuestaSim (Simulation) R&D team at Siemens EDA, you will play a crucial role in designing and developing AI/ML-driven algorithms and solutions to enhance the performance and capabilities of simulation tools. Your contributions will involve creating cutting-edge engines and components, integrating machine learning techniques into simulation and verification workflows, and enhancing existing codebases. In this role, you will collaborate with a team of experienced engineers to solve complex problems in a dynamic environment. Your expertise in AI/ML frameworks, data-driven problem solving, and traditional simulation technologies will be key in achieving project milestones. Your ability to stay self-motivated, disciplined, and innovative will drive progress within the team. To excel in this position, you should hold a Bachelors or Masters degree in Computer Science, Artificial Intelligence, Electrical Engineering, or a related technical field. Your hands-on experience with AI/ML techniques such as supervised and unsupervised learning, neural networks, and reinforcement learning will be essential. Proficiency in programming languages like C/C++ and Python, along with a strong foundation in algorithms and data structures, is required. Knowledge of machine learning and deep learning frameworks, compiler concepts, optimizations, parallel computing, UNIX/Linux platforms, and problem-solving skills are also crucial for this role. Additionally, familiarity with Digital Electronics, SystemVerilog, Verilog, VHDL, simulation technologies, and formal-based verification methodologies will be advantageous. At Siemens, we value diversity and inclusion, and we are committed to creating a workplace where all individuals are respected and empowered. If you are passionate about shaping the future through innovation and technology, we encourage you to join us on this exciting journey. Your curiosity and creativity will help us build a better tomorrow.,

As a Senior Member of Technical Staff (SMTS) Silicon Design Engineer at AMD, you will be an integral part of the Circuit Technology team, focusing on DFT Methodology/Architect/RTL execution for high-speed SERDES Phys, Next-gen Memory Phys, and Die-to-Die interconnect IPs. Your responsibilities will include defining the DFX architecture for high-speed PHYs and die-to-die connectivity IP designs, RTL coding, supporting scan stitching, developing timing constraints, assisting with ATPG, and post-silicon bringup. Join a dynamic team that delivers cutting-edge IPs crucial for every SOC developed by AMD. The ideal candidate possesses strong analytical and problem-solving skills with keen attention to detail. You must demonstrate the ability to work hands-on, be a self-starter, a leader, and independently drive tasks to completion. Key Responsibilities: - Lead and define Design for Test/Debug/Yield Features specific to PHYs. - Implement DFX features into RTL using Verilog. - Comprehend DFX Architectures and micro-architectures. - Utilize JTAG (1149.1/1687/1500)/IJTAG, Scan Compression (EDT, SSH), and at-speed scan testing implementation. - Conduct gate-level simulation using Synopsys VCS and Verdi. - Perform Spyglass bringup and analysis for scan readiness/test coverage gaps. - Plan, implement, and verify MBIST. - Assist Test Engineering in planning, patterns, and debug. - Support silicon bring-up and debug. - Develop efficient DFx flows and methodology compatible with front-end and physical design flows. Preferred Experience: - Proficiency in industry-standard ATPG and DFx insertion CAD tools. - Familiarity with industry-standard DFX methodology: e.g., Streaming Scan Network (SSN), IJTAG, ICL/PDL, etc. - Knowledge of SystemVerilog and UVM. - Expertise in RTL coding for DFx logic, including lock-up latches, clock gates, and scan anchors. - Understanding of low-power design flows such as power gating, multi-Vt, and voltage scaling. - Strong grasp of high-performance, low-power design fundamentals. - Familiarity with fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware. - Exposure to post-silicon testing and tester pattern debug is advantageous. - Excellent problem-solving and debug skills across various design hierarchies. Academic Credentials: - BS/MS/PhD in EE/ECE/CE/CS with industry experience in advanced DFx techniques. Join AMD and be a part of a culture that values innovation, problem-solving, and collaboration. Together, we can advance technology and shape the future of computing.,

Agnisys is looking for freshers to join our team to work on high tech products for the Semiconductor industry. Agnisys is a leader in automating SoC development. It’s products are considered to be the most comprehensive and best in class. We offer a progressive, innovations-driven, learning environment. Don’t get pigeon-holed into one specific area when you can learn the intricacies of Design, Verification, Firmware and overall chip design all at one company! Not only that, you will be exposed to Product Validation, Customer Support and an Agile development environment. Agnisys focuses on research and development by participating in Accellera Systems Initiative, presenting in worldwide conferences, encouraging creative thinking and initiative. So if you value innovation and creativity and want to create a strong foundation for your career, join Agnisys today. Basic Requirements: Candidates should be B.Tech.CS & MCA freshers/graduate Basic Knowledge in Verilog, VHDL, SystemVerilog & C FPGA, EDA Tools, Linux, Perl, Python, Tcl, Bash scripting Should have excellent communication skills Ability to work independently with little supervision as well as ability to work within a team Excellent multi-tasking skills Self-motivated with strong team spirit Job Type: Full-time Pay: ₹22,000.00 - ₹22,001.00 per month Benefits: Health insurance Internet reimbursement Schedule: Day shift Work Location: In person

Job Description : 7+ years of experience in design verification with at least 2+ years in a leadership role. Expertise in SystemVerilog, UVM, assertions (SVA), and scripting languages (Python, Perl, Tcl, etc.). Solid understanding of digital design, SoC architecture, and bus protocols. Experience with simulation and debug tools (VCS, ModelSim, Questa, Verdi, DVE, etc.). Strong analytical and problem-solving skills with a keen attention to detail. Excellent communication, project management, and interpersonal skills. Good Working experience on protocol like , AXI, PCIe, CXL, Ethernet, DMAC, USB, UFS·

Company Description Spandsons Horizon Engineering revolutionises the AEC industry by integrating sustainability, Design & Build of Infrastructures, Structural Engineering, AI, IoT, and innovative technologies into project management, Virtual Design Construction, and training programs. We are at the forefront of blending advanced technological solutions with environmental consciousness to drive progress and innovation. Our mission is to deliver cutting-edge engineering solutions while fostering a culture of continuous learning and development. Role Description This is a contract role for a VLSI Mentor / Guest Faculty specialising in Advanced Digital Systems & Low Power Design. This is an on-site role located in Salem. You will be instrumental in guiding 5th, 6th, and 7th-semester B.E./B.Tech students in advanced VLSI concepts and practical applications. This role offers a unique opportunity to directly impact the academic and career growth of 60 aspiring engineers. Key Responsibilities: Deliver engaging and in-depth sessions on: Advanced Digital System Design with Verilog HDL: Covering topics from Verilog HDL basics, combinational and sequential circuits, FSM design, to simulation and testing. Low Power VLSI Design: Including the need for low power design, power estimation and optimisation, dynamic power reduction techniques, clock/power gating, and leakage reduction techniques. Potentially other VLSI domains such as Digital Design Verification with SystemVerilog & UVM, Introduction to FPGA-Based Digital System Design, ASIC Design and Verification, and Introduction to RISC-V Architecture and FPGA Design, based on program needs. Provide hands-on guidance for lab assignments and projects, utilising tools like Xilinx Vivado, EDA Playground, ModelSim/Vivado, LTspice, Synopsys Design Compiler, ICC2, PrimeTime, VCS, Verdi, and FPGA boards. Facilitate interactive learning and encourage problem-solving among students. Ensure alignment of content with the recommended semester curriculum and prerequisites. Qualifications: Minimum of 4-5 years of verifiable industry experience in VLSI design, with strong expertise in Advanced Digital System Design and Low Power VLSI Design. Proficiency in relevant EDA tools and hardware platforms as listed above. Excellent communication and presentation skills. A passion for teaching, mentoring, and contributing to student development. Program Details: Total Students: Approximately 60. Schedule: Thursdays & Fridays (12 hours per week). Program Start Date: July 24th & 25th. Duration: Program for Semesters 5, 6, and 7. Benefits: Accommodation and food will be provided by the institution. Opportunity to make a significant impact on the next generation of VLSI engineers. Collaborate with a forward-thinking academic institution.

Key Responsibilities: Define and implement DFT architecture for SoCs and IPs. Develop and integrate scan chains, ATPG, MBIST, LBIST, and boundary scan (JTAG). Work with RTL designers to insert DFT logic and resolve DRC violations. Generate and validate test patterns using tools such as TetraMAX , FastScan , DFT Advisor , etc. Analyze and improve fault coverage and test time reduction. Support silicon bring-up and post-silicon validation of test features. Debug and resolve DFT-related issues during synthesis, simulation, and verification. Collaborate with physical design and verification teams to ensure DFT compliance throughout the flow. Required Skills: 3–10 years of hands-on experience in DFT implementation. Strong knowledge of scan insertion, ATPG, MBIST, LBIST, and boundary scan. Experience with DFT tools: Synopsys DFT Compiler , TetraMAX , Mentor Tessent , FastScan , DFTMAX , etc. Proficient in scripting (TCL, Perl, Python, Shell) for automation. Familiar with RTL coding (Verilog/SystemVerilog) and synthesis flow. Good understanding of timing constraints, STA, and low-power design considerations in DFT. Experience in handling gate-level simulations and testbench development.