Posted:2 weeks ago|
Platform:
On-site
Full Time
Lead and mentor a team of verification engineers.
Define verification strategies and develop reusable testbenches using UVM/OVM.
Drive coverage-driven verification with code coverage, functional coverage, and assertions.
Perform Gate-Level Simulations (GLS) and AMS/Power-aware verification.
Collaborate with design, architecture, and validation teams.
Automate tasks using scripting languages (Python, Perl, Shell, Tcl).
Skills We’re Looking For:
Primary: Verilog, SystemVerilog, UVM/OVM, IP & SoC Verification, scripting (Python, Perl, Shell, Tcl)
Secondary: GLS, LEC, AMS, Emulation, ARM-based SoCs, Protocols (AHB/AXI/APB, USB, PCIe, Ethernet, I2C, SPI, CAN, MIPI CSI/DSI, LPDDR)
Education:
Bachelor’s or Master’s in Electrical/Computer Engineering or related field.
Experience Level: 5yrs-12yrs
Capgemini Engineering
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