Tenstorrent

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. The role is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yield learnings while minimizing design intrusions. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC. This role is hybrid, based out of Bangalore. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Responsibilities Implementation of DFT features into RTL using verilog. Understanding of DFT Architectures and micro-architectures. ATPG and test coverage analysis using industry standard tools. JTAG, Scan Compression, and ASST implementation. Gate level simulation using Synopsys VCS and Verdi. Support silicon bring-up and debug. MBIST planning, implementation, and verification. Support Test Engineering on planning, patterns, and debug. Develop efficient DFx flows and methodology compatible with front end and physical design flows Experience & Qualifications BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of industry experience in advanced DFx techniques. DFx experience implementing in finFET technologies. Experience with industry standard ATPG and DFx insertion CAD tools. Familiarity with SystemVerilog and UVM. Fluent in RTL coding for DFx logic including lock-up latches, clock gates, and scan anchors. Understanding of low-power design flows such as power gating, multi-Vt and voltage scaling. Good understanding of high-performance, low-power design fundamentals. Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware. Exposure to post-silicon testing and tester pattern debug are major assets. Experience with Fault Campaigns a plus. Strong problem solving and debug skills across various levels of design hierarchies. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government. As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and supporting documentation will be required and considered as a condition of employment. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. Show more Show less

Tenstorrent is at the forefront of cutting-edge AI technology, redefining what’s possible in performance, usability, and cost. As AI transforms the computing landscape, it demands integrated innovation across software models, compilers, platforms, networking, and semiconductors. Our team—diverse, curious, and driven—has built a high-performance RISC-V CPU from the ground up and shares a collective passion for advancing AI. We thrive on collaboration and tackling tough challenges, and we’re expanding our team across all experience levels. We’re looking for an experienced CPU/IP / SoC Physical Verification Engineer who can take ownership of full-chip and block-level physical verification across our complex RISC-V based designs. This role is ideal for someone who thrives in a fast-paced, collaborative environment, enjoys solving challenging problems across advanced technology nodes, and is passionate about building clean, manufacturable silicon. What You’ll Be Doing Drive physical verification activities (DRC, LVS, ERC, PERC, Antenna, DFM) from block to full-chip level. Collaborate closely with RTL, PD, CAD, and packaging teams to ensure sign-off readiness. Debug verification issues and work hands-on with tools like Calibre and ICV to root-cause violations. Support ESD planning, padring integration, and bump/RDL layout strategies. Contribute to PV methodology improvements and automation scripts. Lead PV closure for key tapeouts and provide mentorship to junior engineers on the team. Interface with foundry teams for rule deck alignment and tapeout planning. What We’re Looking For 6 to 14 years of hands-on experience in CPU/IP / SoC physical verification. Solid command of physical verification tools and flows (Calibre, ICV, ICC2, Innovus, etc.). Strong understanding of advanced node requirements (7nm, 5nm, 3nm), including FinFET challenges. Proficiency in checking and resolving DRC, LVS, ERC, and PERC violations. Comfortable scripting in Python, TCL, or Perl to automate workflows and debug processes. Awareness of ESD, IR drop, EM, and reliability considerations in full-chip designs. Clear communication and a strong sense of ownership — you enjoy working across teams and taking designs across the finish line. Show more Show less

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Physical design for high-performance designs going into industry leading CPU and AI/ML architecture. The person coming into this role will be involved in all implementation aspects from synthesis to tapeout for various IPs on the chip. The work is done alongside a group of highly experienced engineers across various domains of the AI chip. This role is hybrid, based out of Bangalore. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Responsibilities Define PD requirements by working closely with the front-end team, understand the chip architecture and drive physical aspects early in the design cycle Physical design tasks including such as synthesis, PnR, timing closure, area improvement, floorplanning, clocking, I/O planning and power optimization Discussions with 3rd party IP providers, foundry partners and design services End to end tasks from flow development to sign-off Deploy innovative techniques for improving power, performance and area of the design, drive experiments with RTL, and evaluate synthesis, timing and power results Experience & Qualifications BS/MS/PhD in EE/ECE/CE/CS Hands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools Strong experience in SOC/ASIC/GPU/CPU design flows on taped out designs, expertise in timing closure at block/chip levels and ECO flows Experience with back-end design tools such as Primetime, Innovus, RedHawk, etc. Knowledge of low-power design flows such as power gating, multi-Vt and voltage scaling Strong programming skills in Tcl/Perl/Shell/Python Excellent understanding of logic design fundamentals and gate/transistor level implementation Exposure to DFT is an asset Prior experience working on high performance technology nodes and understanding of deep sub-micron design problems/solutions Strong problem solving and debug skills across various levels of design hierarchies Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government. As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and supporting documentation will be required and considered as a condition of employment. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We’re building high-performance RISC-V CPUs from the ground up, and we need someone who can help us test them thoroughly and thoughtfully. As a testbench lead, you'll design and maintain the infrastructure that makes sure our cores behave exactly as intended. If you enjoy figuring out how things break (and fixing them), building clean and reusable systems, and working with a team that values both rigor and creativity, we’d love to talk. This role is hybrid, based out of Bangalore. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You’ve built and maintained testbenches for CPU cores or similar designs, using SystemVerilog, UVM, and C++. You like creating clean, reusable components — from transactors to functional models — that others can plug in and build on. You’re comfortable working across both software-style C++/UVM environments and hardware-style simulation flows. You enjoy collaborating with design teams and helping them debug issues quickly and clearly. What We Need Someone to design and grow a UVM testbench setup that works for both block-level and full-chip simulation. The ability to write C++ code that fits into a DV framework — and help shape that framework as it evolves. A good understanding of CPU microarchitecture and how to test it effectively. Comfort working across tools, from open-source simulators like Verilator to commercial environments and emulators. What You Will Learn How to design testbenches that scale with complexity — and keep them maintainable as the chip grows. How to support both simulation and emulation from the same DV infrastructure. How custom C++ and UVM environments can coexist to improve verification workflows. How different teams — RTL, DV, software, tools etc — come together to build AI-focused silicon. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government. As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and supporting documentation will be required and considered as a condition of employment. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are seeking an energetic and proactive Office Manager for our Bangalore office. This position will report to the Manager of EMEA & APAC Workplace Operations. Key responsibilities include managing onboarding and placement of employees in desks, vendor management, budgets management, curating the snack and beverage program, and adhering to global workplace standards.The role requires strong cross-functional collaboration with IT, HR, and Marketing, acting as a Workplace Business Partner to address team needs. This role is onsite, based out of Bangalore, India. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A people person who builds strong relationships with vendors, coworkers, and building staff (e.g., janitorial, F&B, office supplies, plant maintenance, repairs). Detail-oriented, efficient, and passionate about creating an organized and welcoming workspace. Great under pressure and energized by making the workplace better every day. What We Need 5+ years managing office ops, preferably in tech or fast-paced, high-growth companies. Someone who understands SEZ compliance, customs, and local regulations. High proficiency in office software and project management tools (e.g., Microsoft Office Suite, Google Workspace, Asana, Trello, Slack, etc.) The ability to partner with HR for onboarding, IT with setups, and Marketing with events and swag while keeping your eye on the bigger picture. What You Will Learn What it is like to work in a fast-paced, ever-evolving environment and open-concept workspace. To coordinate with building management and security teams on access control, badge distribution, and emergency procedures. How to level-up the employee experience through space, service, and surprise-and-delight moments. To be a leader and supervisor of the facilities and housekeeping teams to maintain a clean, functional, and well-maintained office environment. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government. As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and supporting documentation will be required and considered as a condition of employment. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. As part of our Physical Design team, you will work on high-performance designs alongside world-class engineers, covering everything from synthesis to tapeout across various IP blocks. This role is onsite, based out of Bangalore. We’re looking for experienced professionals with hands-on expertise in physical design. Your role and offer will align with the experience demonstrated during interviews, which may differ from the level in this posting. Who You Are You enjoy solving complex timing, power, and layout problems at advanced nodes. You’ve worked on multiple chip tapeouts and understand physical design flows end-to-end. You’re comfortable using tools like Innovus, Primetime, and RedHawk. You like working closely with cross-functional teams to deliver high-quality silicon. What We Need Take ownership of blocks from synthesis to sign-off: floorplanning, PnR, clocking, and optimization. Define physical design needs in collaboration with front-end and architecture teams. Coordinate with foundry partners, IP vendors, and design services during integration. Improve design quality and drive area, power, and performance improvements through flow tuning and RTL experiments. What You Will Learn How high-performance CPU and AI chips are built at leading-edge technology nodes. Techniques to push the limits of performance, power, and area in real silicon. How front-end, back-end, and validation teams work together to ship a product. Ways to evolve implementation workflows and improve team efficiency. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government. As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and supporting documentation will be required and considered as a condition of employment. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.

Tenstorrent is at the forefront of AI technology, setting new standards in performance, usability, and cost efficiency. With the evolution of AI reshaping computing, there is a growing need for innovative solutions that integrate advancements in software models, compilers, platforms, networking, and semiconductors. Our team comprises diverse technologists who have created a high-performance RISC-V CPU and share a common passion for AI, striving to develop the ultimate AI platform. We value collaboration, curiosity, and a dedication to solving complex problems. As we expand our team, we are seeking individuals at all levels to contribute to our mission. We are currently seeking an experienced engineer to lead the clock design efforts for our IP, CPU, and SoC teams. In this role, you will be responsible for defining clocking strategies that strike a balance between stringent timing requirements, power efficiency, and area constraints. You will collaborate closely with RTL, PD, and power engineers to construct robust, high-performance systems. This position is based in Bangalore and requires onsite presence. We invite candidates with a minimum of 6 years of experience to apply for this role. Throughout the interview process, candidates will be evaluated for their proficiency, and job offers will be made based on the assessment, which may vary from the details provided in this listing. As an ideal candidate: - You possess a solid background in clock tree synthesis and clock network design. - You are adept at working with timing, CDC, and low-power design methodologies. - You have experience working with advanced technology nodes, particularly 5nm or below, influencing design decisions. - You enjoy developing scripts to automate tasks and streamline engineering workflows. Key responsibilities include: - Taking charge of the end-to-end clock architecture for intricate SoCs. - Collaborating effectively with RTL, physical design, and power teams to achieve project objectives. - Proficiency in utilizing tools like Synopsys FC, ICC2, and scripting languages such as Python, Perl, or Tcl. - Demonstrating a problem-solving mindset focused on enhancing efficiency and resilience. This role offers the opportunity to: - Architect clocking strategies that are scalable across IP, CPU, and SoC designs. - Learn techniques to minimize power consumption and jitter while meeting aggressive power, performance, and area (PPA) targets. - Enhance workflows and reduce manual interventions through intelligent automation. - Address and resolve challenges specific to cutting-edge technology nodes. Join us at Tenstorrent and be part of a dynamic team dedicated to pushing the boundaries of AI technology.,

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We're looking for a passionate and hands-on RISC-V CPU Cluster/SoC DV Engineer to architect, develop, and evolve world-class verification infrastructure for high-performance RISC-V cores and clusters. If building from scratch, innovating on methodology, and collaborating with top-tier CPU designers excites you — read on. This role is hybrid, based out of Bangalore. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting Who You Are Skilled in building robust verification environments with System Verilog, UVM, and C++, and confident driving verification plans independently. Bring a system-level mindset with experience integrating and verifying multi-IP clusters or SoCs. Strong in stimulus planning, debug, and coverage closure for subsystems like caches, NoCs, and memory hierarchies. Comfortable working on cross-IP features such as coherence and security at the cluster or SoC level. What We Need Bachelor’s or Master’s in Electrical Engineering, Computer Science, or a related field. Hands-on experience with System Verilog and UVM-based verification. Track record of driving subsystem or SoC-level DV projects, including integration and feature validation. Familiarity with AXI/CHI protocols, system IPs (debug, power mgmt), and multi-IP verification flows. What You Will Learn How to scale DV infrastructure for high-performance RISC-V clusters and SoCs. Verification strategies for multi-agent systems across CPUs, IPs, and interconnects. Best practices for integration-level planning and cross-IP feature convergence. Collaborating across RTL, DV, software, and validation teams to drive system-level bring-up. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government. As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and supporting documentation will be required and considered as a condition of employment. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are seeking an energetic and proactive Office Manager for our Bangalore office. This position will report to the Manager of EMEA & APAC Workplace Operations. Key responsibilities include managing onboarding and placement of employees in desks, vendor management, budgets management, curating the snack and beverage program, and adhering to global workplace standards.The role requires strong cross-functional collaboration with IT, HR, and Marketing, acting as a Workplace Business Partner to address team needs. This role is onsite, based out of Bangalore, India. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A people person who builds strong relationships with vendors, coworkers, and building staff (e.g., janitorial, F&B, office supplies, plant maintenance, repairs). Detail-oriented, efficient, and passionate about creating an organized and welcoming workspace. Great under pressure and energized by making the workplace better every day. What We Need 5+ years managing office ops, preferably in tech or fast-paced, high-growth companies. Someone who understands SEZ compliance, customs, and local regulations. High proficiency in office software and project management tools (e.g., Microsoft Office Suite, Google Workspace, Asana, Trello, Slack, etc.) The ability to partner with HR for onboarding, IT with setups, and Marketing with events and swag while keeping your eye on the bigger picture. What You Will Learn What it is like to work in a fast-paced, ever-evolving environment and open-concept workspace. To coordinate with building management and security teams on access control, badge distribution, and emergency procedures. How to level-up the employee experience through space, service, and surprise-and-delight moments. To be a leader and supervisor of the facilities and housekeeping teams to maintain a clean, functional, and well-maintained office environment. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government. As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and supporting documentation will be required and considered as a condition of employment. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We&aposre looking for a passionate and hands-on RISC-V CPU Cluster/SoC DV Engineer to architect, develop, and evolve world-class verification infrastructure for high-performance RISC-V cores and clusters. If building from scratch, innovating on methodology, and collaborating with top-tier CPU designers excites you read on. This role is hybrid, based out of Bangalore. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting Who You Are Skilled in building robust verification environments with System Verilog, UVM, and C++, and confident driving verification plans independently. Bring a system-level mindset with experience integrating and verifying multi-IP clusters or SoCs. Strong in stimulus planning, debug, and coverage closure for subsystems like caches, NoCs, and memory hierarchies. Comfortable working on cross-IP features such as coherence and security at the cluster or SoC level. What We Need Bachelors or Masters in Electrical Engineering, Computer Science, or a related field. Hands-on experience with System Verilog and UVM-based verification. Track record of driving subsystem or SoC-level DV projects, including integration and feature validation. Familiarity with AXI/CHI protocols, system IPs (debug, power mgmt), and multi-IP verification flows. What You Will Learn How to scale DV infrastructure for high-performance RISC-V clusters and SoCs. Verification strategies for multi-agent systems across CPUs, IPs, and interconnects. Best practices for integration-level planning and cross-IP feature convergence. Collaborating across RTL, DV, software, and validation teams to drive system-level bring-up. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government. As this position will have direct and/or indirect access to information, systems, or technologies that are subject to?U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information?and supporting documentation will be required and considered as a condition of employment. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. Show more Show less

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Were building high-performance RISC-V CPUs from the ground up, and we need someone who can help us test them thoroughly and thoughtfully. As a testbench lead, you&aposll design and maintain the infrastructure that makes sure our cores behave exactly as intended. If you enjoy figuring out how things break (and fixing them), building clean and reusable systems, and working with a team that values both rigor and creativity, wed love to talk. This role is hybrid, based out of Bangalore. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Youve built and maintained testbenches for CPU cores or similar designs, using SystemVerilog, UVM, and C++. You like creating clean, reusable components from transactors to functional models that others can plug in and build on. Youre comfortable working across both software-style C++/UVM environments and hardware-style simulation flows. You enjoy collaborating with design teams and helping them debug issues quickly and clearly. What We Need Someone to design and grow a UVM testbench setup that works for both block-level and full-chip simulation. The ability to write C++ code that fits into a DV framework and help shape that framework as it evolves. A good understanding of CPU microarchitecture and how to test it effectively. Comfort working across tools, from open-source simulators like Verilator to commercial environments and emulators. What You Will Learn How to design testbenches that scale with complexity and keep them maintainable as the chip grows. How to support both simulation and emulation from the same DV infrastructure. How custom C++ and UVM environments can coexist to improve verification workflows. How different teams RTL, DV, software, tools etc come together to build AI-focused silicon. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government. As this position will have direct and/or indirect access to information, systems, or technologies that are subject to?U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information?and supporting documentation will be required and considered as a condition of employment. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. Show more Show less

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We're looking for a passionate and hands-on RISC-V CPU Cluster Design Verification Engineer to architect, develop, and evolve world-class verification infrastructure for high-performance RISC-V cores and clusters. If building from scratch, innovating on methodology, and collaborating with top-tier CPU designers excites you — read on. This role is hybrid, based out of Bangalore. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting Who You Are The kind of engineer who can take ownership of verification from day one — building environments in SystemVerilog, UVM, and C++ comes naturally. Thinks at the system level, with experience bringing together multiple IPs and making sure they play well together. Knows how to plan stimulus, track down bugs, and close coverage for complex subsystems like caches, NoCs, and memory. Ready to tackle tricky cross-IP features like coherence and security, and ensure they work reliably at the SoC level. What We Need A background in Electrical Engineering, Computer Science, or a similar field — Bachelor’s or Master’s level. Real experience working with SystemVerilog and UVM to verify complex designs. Someone who’s led DV efforts at the subsystem or SoC level, from integration through validation. Comfort with multi-IP verification flows and familiarity with protocols like AXI or CHI, plus system IPs like debug and power management. What You Will Learn How to scale DV infrastructure for high-performance RISC-V clusters and SoCs. Verification strategies for multi-agent systems across CPUs, IPs, and interconnects. Best practices for integration-level planning and cross-IP feature convergence. Collaborating across RTL, DV, software, and validation teams to drive system-level bring-up. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government. As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and supporting documentation will be required and considered as a condition of employment. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We're looking for a passionate and hands-on RISC-V System IP DV Engineer to architect, develop, and evolve world-class verification infrastructure for System IPs (interrupt controllers, IOMMU, power management, DFD etc) that will be integrated in high-performance RISC-V CPU clusters. If building from scratch, innovating on methodology, and collaborating with top-tier CPU designers excites you — read on. This role is hybrid, based out of Bangalore. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting Who You Are You bring domain understanding of power management flows like clocks, resets, low power states, system management controller interactions etc You thrive in building robust verification environments using SystemVerilog and UVM, and optionally C++, and can define and drive verification plans independently. You have a strong grasp of stimulus planning, checker development, debug techniques, and coverage closure for verifying complex hardware subsystems. You’re comfortable working on features that span multiple IPs and can devise plans to verify them at IP, subsystem and fullchip levels. What We Need A Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field. Strong experience with System Verilog and UVM-based verification. Proven ability to drive IP level and subsystem level DV projects. Familiarity with power management flows, hardware/firmware interactions, bus protocols like AXI. What You Will Learn Owning a large scope with a small focused team. How to structure and deliver an IP/kit to SoCs with seamless integration in mind. How power management impacts the entire SoC, collaborating closely with RTL designers, architects, firmware engineers etc. Building reusable verification components, coverage models, and checkers that scale across multiple abstraction layers. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government. As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and supporting documentation will be required and considered as a condition of employment. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.

Tenstorrent is at the forefront of the AI technology industry, pioneering cutting-edge advancements that are reshaping performance standards, user-friendliness, and cost-effectiveness. In the rapidly evolving landscape of AI technology, it is imperative that solutions evolve to integrate innovations across software models, compilers, platforms, networking, and semiconductors. Our team of diverse technologists has successfully developed a high-performance RISC-V CPU from the ground up, driven by a shared passion for AI and a profound commitment to creating the ultimate AI platform. At Tenstorrent, we cherish values like collaboration, curiosity, and a resolute dedication to tackling complex challenges head-on. As we continue to expand our team, we are seeking individuals at all levels of seniority who can contribute to our mission. We are currently seeking an experienced Sr. Engineering Manager or Director to take on the role of leading the CPU Subsystem Verification team in Bangalore. In this key position, you will be responsible for overseeing a high-performing team, devising verification strategies, and ensuring the utmost quality for our next-generation RISC-V CPU products. Key Responsibilities: - Lead and nurture the CPU Subsystem Verification team, emphasizing technical excellence and efficient execution. - Develop and implement verification strategies, methodologies, and test plans for CPU subsystems. - Supervise the creation of UVM-based test benches, focusing on efficient and coverage-driven verification. - Collaborate closely with the architecture, design, and performance teams to achieve verification closure. - Recruit, mentor, and cultivate a proficient verification team while fostering a culture of innovation and high performance. - Drive debugging initiatives and refine verification methodologies to enhance efficiency and quality. Qualifications: - Possess over 18 years of hands-on experience in CPU or complex SoC/subsystem verification. - Demonstrated expertise in SystemVerilog, UVM, AXI, and cache-coherent interconnects. - Proven track record of leading and managing verification teams effectively. - Experience in verification planning, execution, and coverage closure for CPU cores or subsystems. - Strong troubleshooting and problem-solving abilities. - Previous exposure to a startup or high-growth environment is advantageous. Preferred Skills: - Familiarity with RISCV architecture is highly desirable. - Experience with DFD (Design for Debug) methodologies. - Exposure to performance modeling and workload-driven verification. Why Join Us - Exciting opportunity to lead cutting-edge verification initiatives in a dynamic AI and CPU hardware startup. - Collaborate with a team of exceptional engineers driving innovation in RISC-V and AI computing. - Competitive compensation and abundant career growth opportunities in a rapidly expanding company. If you are enthusiastic about CPU verification and eager to make a substantial impact, we are excited to hear from you!,

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We’re looking for a driven Engineering Program Manager—or a hands-on technical lead ready to step into program management—to help lead the charge on our RISC-V CPU team. In this role, you’ll be at the center of the action, working across architecture, design, verification, physical design, and DFT to drive the full lifecycle of a high-performance CPU—from spec to tapeout to post-silicon debug. You’ll partner with key stakeholders to define bold objectives, lock in milestones, and align the resources needed to bring next-gen compute to life. This role is hybrid, based out of Bangalore, India. We welcome candidates with 10+ years of experience for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A technically strong leader with experience in CPU, SoC, or silicon development. Skilled in aligning cross-functional teams to deliver complex, high-performance hardware programs. Proactive problem solver who thrives in dynamic, fast-paced environments. A clear communicator who can engage engineers and executives alike. What We Need Ownership of full-cycle CPU program management—from spec to tapeout and post-silicon debug. Ability to define scope, schedule, and resources, and lead execution across architecture, design, verification, and DFT teams. Proven experience driving silicon development, managing risk, and delivering milestones. Experience with Functional Safety (FuSa) standards and implementation, especially ISO 26262 and an understanding of automotive industry requirements and standards for hardware development is highly desirable. What You Will Learn How to lead the delivery of cutting-edge RISC-V CPU IP at scale, both internally and for external customers. Partnering with top engineers to resolve real-time design challenges, drive schedule trade-offs, and push forward high-impact decisions. Leading project reviews and reporting to senior leadership on metrics, risks, and mitigation plans. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. RISC-V CPU Core Testbench Lead Responsibilities Design, develop, and maintain highly configurable testbench environments for RISC-V cores and clusters using synthesizable SystemVerilog, UVM and C++. Build key testbench components including harnesses, transactors, functional models, checkers and utilities such as preloaders, trickbox etc. Contribute to the CVM (C++ Verification Methodology) - a UVM-inspired framework - by applying modern C++ features to simplify testbench development and improve maintainability. Enable integration of UVM-based block-level environments into the broader testbench framework to support hybrid simulation workflows. Ensure testbench portability across simulators (including open-source Verilator) and commercial emulation platforms. Support architecture and microarchitecture bring-up for both core and cluster DV teams by enabling rapid validation of new features. Develop debugging tools and automation to accelerate root-cause analysis for failures across simulation and emulation. Collaborate closely with RTL, DV, and tooling teams to define reusable infrastructure and scalable test strategies. Experience and Qualifications Bachelors or Masters degree in Electronics, Computer Engineering, or a related field, with 9+ years of relevant industry experience. Strong proficiency in modern C++ and SystemVerilog, including familiarity with verification libraries or testbench infrastructure. Hands-on experience with SystemVerilog UVM, including environment construction and integration into larger simulation contexts. Experience working with or contributing to custom DV methodologies (e.g., UVM, custom C++-based frameworks). Solid understanding of software engineering principles such as design patterns (e.g., publish-subscribe), multithreaded programming, and coroutines. Working knowledge of CPU architectures (RISC-V, ARM, or x86) and microarchitectural design elements such as pipelines, caches, MMUs etc. Strong debugging and analytical skills across layers of abstraction from software and compiler traces to assembly programs and RTL waveforms. Excellent communication and collaboration skills, with a track record of working effectively in fast-paced team environments. Self-driven and adaptable, with a bias for automation, reuse, and scalable infrastructure. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Show more Show less

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We’re looking for a driven Engineering Program Manager—or a hands-on technical lead ready to step into program management—to help lead the charge on our RISC-V System IP team. In this role, you’ll be at the center of the action, working across architecture, design, verification, physical design, and DFT to drive the full lifecycle of high-performance System IPs that complement our high performance CPUs —from spec to tapeout to post-silicon debug. You’ll partner with key stakeholders to define bold objectives, lock in milestones, and align the resources needed to bring next-gen compute to life. This role is hybrid, based out of Bangalore, India. We welcome candidates with 10+ years of experience for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A technically strong leader with experience in System IP, CPU, SoC, or silicon development. Skilled in aligning cross-functional teams to deliver complex, high-performance hardware programs. Proactive problem solver who thrives in dynamic, fast-paced environments. A clear communicator who can engage engineers and executives alike. What We Need Ownership of full-cycle System IP program management—from spec to tapeout and post-silicon debug. Ability to define scope, schedule, and resources, and lead execution across architecture, design, verification, and DFT teams. Proven experience driving silicon development, managing risk, and delivering milestones. Experience with Functional Safety (FuSa) standards and implementation, especially ISO 26262 and an understanding of automotive industry requirements and standards for hardware development is highly desirable. What You Will Learn How to lead the delivery of cutting-edge RISC-V System IP at scale, both internally and for external customers. Partnering with top engineers to resolve real-time design challenges, drive schedule trade-offs, and push forward high-impact decisions. Leading project reviews and reporting to senior leadership on metrics, risks, and mitigation plans. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are seeking a passionate and detail-oriented Design Verification Engineer to join our Functional Safety (FuSa) Subsystem team. You will focus on verifying safety-critical subsystems that integrate multiple IPs, ensuring robustness, traceability, and compliance with ISO 26262/ASIL-B/ASIL-D and similar safety standards at the subsystem level. The role emphasizes integration verification, fault campaign development, and validation of safety features across IP boundaries. This role is on-site, based out of Bangalore, India. We welcome candidates at various experience levels. During the interview process, you will beevaluated and offered a level that aligns with your experience, which may differ from the one in this posting. Who You Are Experienced DV engineer with strong SystemVerilog and UVM expertise at both block and subsystem levels. Familiar with ISO 26262 and integration-level safety requirements (ASIL B–D). Able to analyze and verify cross-IP safety mechanisms and subsystem interactions. Clear communicator who thrives in collaborative, multi-IP, cross-functional environments. What We Need Ability to build UVM-based environments and author test plans that validate safety mechanisms across subsystem boundaries. Experience with fault injection campaigns, diagnostic coverage analysis, and safety mechanism validation at integration level. Hands-on experience with tools like Synopsys VC Z01X, Siemens Tessent, or Cadence Safety Verification for subsystem-level fault simulation. Familiarity with coverage-driven verification, assertion-based verification, and FMEDA/diagnostic metrics (e.g., SPFM, LFM, PMHF) at subsystem granularity. What You Will Learn How to perform functional safety verification across complex subsystems integrating multiple safety-critical IPs. Techniques for tracking and reporting ASIL-level diagnostic coverage in real-world fault campaigns. Integration of safety subsystems into next-generation CPUs and SoCs. Practical experience collaborating across design, safety architecture, and system verification teams in cutting-edge compute platforms. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

As an experienced Sr. Engineering Manager or Director, you will lead the CPU Subsystem Verification team at Tenstorrent in Bangalore. Your role will involve defining verification strategies, ensuring the quality of next-generation RISC-V CPU products, and driving technical excellence and execution within the team. **Key Responsibilities:** - Lead and grow the CPU Subsystem Verification team, focusing on technical excellence and execution. - Define and implement verification strategies, methodologies, and test plans for CPU subsystems. - Oversee the development of UVM-based test benches to ensure efficiency and coverage-driven verification. - Collaborate closely with architecture, design, and performance teams to achieve verification closure. - Hire, mentor, and develop a strong verification team while fostering an innovative and high-performance culture. - Drive debugging efforts and enhance verification methodologies to improve efficiency and quality. **Qualifications:** - 18+ years of hands-on experience in CPU or complex SoC/subsystem verification. - Strong expertise in SystemVerilog, UVM, AXI, and cache-coherent interconnects. - Proven experience in leading and managing verification teams. - Experience in verification planning, execution, and coverage closure for CPU cores or subsystems. - Strong debugging and problem-solving skills. - Prior experience in a startup or high-growth environment is a plus. **Preferred Skills:** - Knowledge of RISCV architecture is highly desirable. - Experience in DFD (Design for Debug) methodologies. - Exposure to performance modeling and workload-driven verification. If you're passionate about CPU verification and want to make a significant impact, this is an exciting opportunity to lead cutting-edge verification efforts in one of the most innovative AI and CPU hardware startups. You will work alongside an exceptional team of engineers and have access to competitive compensation and career growth opportunities in a fast-growing company.,

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We're looking for a driven Engineering Program Manageror a hands-on technical lead ready to step into program managementto help lead the charge on our RISC-V System IP team. In this role, you'll be at the center of the action, working across architecture, design, verification, physical design, and DFT to drive the full lifecycle of high-performance System IPs that complement our high performance CPUs from spec to tapeout to post-silicon debug. You'll partner with key stakeholders to define bold objectives, lock in milestones, and align the resources needed to bring next-gen compute to life. This role is hybrid, based out of Bangalore, India. We welcome candidates with 10+ years of experience for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A technically strong leader with experience in System IP, CPU, SoC, or silicon development. Skilled in aligning cross-functional teams to deliver complex, high-performance hardware programs. Proactive problem solver who thrives in dynamic, fast-paced environments. A clear communicator who can engage engineers and executives alike. What We Need Ownership of full-cycle System IP program managementfrom spec to tapeout and post-silicon debug. Ability to define scope, schedule, and resources, and lead execution across architecture, design, verification, and DFT teams. Proven experience driving silicon development, managing risk, and delivering milestones. Experience with Functional Safety (FuSa) standards and implementation, especially ISO 26262 and an understanding of automotive industry requirements and standards for hardware development is highly desirable. What You Will Learn How to lead the delivery of cutting-edge RISC-V System IP at scale, both internally and for external customers. Partnering with top engineers to resolve real-time design challenges, drive schedule trade-offs, and push forward high-impact decisions. Leading project reviews and reporting to senior leadership on metrics, risks, and mitigation plans. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.