Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.We are seeking a passionate and detail-oriented Design Verification Engineer to join our Functional Safety (FuSa) Subsystem team. You will focus on verifying safety-critical subsystems that integrate multiple IPs, ensuring robustness, traceability, and compliance with ISO 26262/ASIL-B/ASIL-D and similar safety standards at the subsystem level. The role emphasizes integration verification, fault campaign development, and validation of safety features across IP boundaries.This role is on-site, based out of Bangalore, India.We welcome candidates at various experience levels. During the interview process, you will beevaluated and offered a level that aligns with your experience, which may differ from the one in this posting.
Who You Are
- Experienced DV engineer with strong SystemVerilog and UVM expertise at both block
and subsystem levels.
- Familiar with ISO 26262 and integration-level safety requirements (ASIL B–D).
- Able to analyze and verify cross-IP safety mechanisms and subsystem interactions.
- Clear communicator who thrives in collaborative, multi-IP, cross-functional environments.
What We Need
- Ability to build UVM-based environments and author test plans that validate safety mechanisms across subsystem boundaries.
- Experience with fault injection campaigns, diagnostic coverage analysis, and safety mechanism validation at integration level.
- Hands-on experience with tools like Synopsys VC Z01X, Siemens Tessent, or Cadence Safety Verification for subsystem-level fault simulation.
- Familiarity with coverage-driven verification, assertion-based verification, and FMEDA/diagnostic metrics (e.g., SPFM, LFM, PMHF) at subsystem granularity.
What You Will Learn
- How to perform functional safety verification across complex subsystems integrating multiple safety-critical IPs.
- Techniques for tracking and reporting ASIL-level diagnostic coverage in real-world fault campaigns.
- Integration of safety subsystems into next-generation CPUs and SoCs.
- Practical experience collaborating across design, safety architecture, and system verification teams in cutting-edge compute platforms.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
