869 Synopsys Jobs

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned digital design expert with a passion for innovation and a drive for technical excellence. With over 15 years of hands-on experience in ASIC digital design using Verilog, you have a proven track record in developing high-performance microprocessor IP and optimizing designs for performance, area, power, and speed. Your background in RISC architectures and embedded processor design makes you a go-to authority in your field. You thrive on solving complex engineering challenges and have a deep understanding of microprocessor architecture, including multi-core systems and digital signal processing. Your programming skills in assembly and C/C++ enable you to bridge the gap between hardware and software, ensuring efficient and robust designs. Collaboration is at your core—you excel at working with multi-site teams, sharing your expertise, and mentoring junior engineers. Your attention to detail, commitment to quality, and ability to debug challenging issues set you apart. You are driven by continuous learning and are always eager to adopt and deploy the latest development techniques. As a Principal Engineer, you take ownership of your projects, communicate effectively with stakeholders, and contribute to both technical and project management aspects of product development. What You’ll Be Doing: Architecting and implementing embedded RISC microprocessor IP at both architectural and RTL levels using Verilog. Optimizing processor designs for performance, speed, area, and power to meet demanding silicon requirements. Generating comprehensive hardware benchmarks, analyzing results, and iterating on design improvements. Developing standalone Verilog testbenches and collaborating closely with the verification team to ensure thorough validation. Debugging complex design issues and bugs, proactively identifying root causes and implementing robust solutions. Maintaining and enhancing the current processor product line and derivative products, ensuring continuous improvement and innovation. Developing and managing detailed project plans, working in close partnership with program managers and cross-functional teams. Contributing to architectural reviews, technical documentation, and process improvements across multi-site teams. The Impact You Will Have: Drive the development of cutting-edge processor IP that powers next-generation smart devices and systems. Enhance the performance, efficiency, and reliability of Synopsys’ industry-leading ARC Processor family. Enable customers to achieve breakthrough results in silicon design and integration through your technical leadership. Mentor and elevate the skills of fellow engineers, fostering a culture of technical excellence and innovation. Shape the direction of processor architecture and design methodologies within the organization. Support the successful delivery of high-quality silicon solutions that meet and exceed customer expectations. Strengthen Synopsys’ reputation as a leader in semiconductor IP by contributing to successful product launches and deployments. What You’ll Need: Bachelor’s degree or higher in Electrical Engineering, Computer Engineering, or related field. 15+ years of experience in digital design, specifically using Verilog for ASIC development. Deep expertise in RISC architectures and microprocessor IP design, including multi-core systems. Strong programming skills in assembly language and C/C++ for embedded systems. Proven ability to optimize digital designs for performance, area, speed, and power. Experience with debugging, verification, and developing standalone testbenches. Familiarity with DSP techniques and multi-site development environments is a plus. Who You Are: Analytical thinker with exceptional problem-solving skills and attention to detail. Effective communicator who can articulate complex technical concepts to diverse audiences. Collaborative team player who thrives in a multi-site, multicultural environment. Proactive, self-motivated, and able to manage multiple priorities efficiently. Mentor and leader who supports the growth and development of colleagues. Adaptable and open to learning new technologies and methodologies. The Team You’ll Be A Part Of: You’ll join the Synopsys Designware ARC Processor development team—a global group of talented engineers dedicated to pushing the boundaries of embedded processor technology. The team values innovation, knowledge sharing, and collaboration, working across multiple sites to deliver world-class IP solutions that enable Synopsys’ customers to succeed in a dynamic marketplace. You’ll be empowered to contribute your expertise, champion best practices, and help shape the future of high-performance silicon design. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Category Engineering Hire Type Employee Job ID 10898 Remote Eligible No Date Posted 29/07/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and meticulous engineer with a deep commitment to excellence in analog and high-speed mixed signal layout design. With a minimum of 2 years of hands-on experience in advanced technology nodes (5nm and below), you thrive in dynamic, collaborative environments where quality, precision, and innovation are valued above all. You are well-versed in the intricacies of SerDes, CTLE, AFE, PLL, LDO, and transmitter/receiver sub-blocks, and you relish the challenge of delivering robust designs for cutting-edge semiconductor products. You are motivated by the opportunity to work alongside some of the brightest minds in the industry, continuously learning and contributing your expertise. You are eager to be part of a team that values diversity, inclusion, and the relentless pursuit of innovation, and you bring a growth mindset that seeks to elevate those around you. Your ability to communicate effectively, adapt to evolving requirements, and deliver under tight timelines sets you apart as a trusted contributor and future leader. What You’ll Be Doing: Designing and implementing high-quality analog and mixed signal layouts for advanced technology nodes (5nm and below). Collaborating closely with circuit design, verification, and physical implementation teams to optimize layout performance and manufacturability. Executing full custom layout of SerDes blocks including CTLE, AFE, PLL, LDO, and transmitter/receiver sub-blocks. Performing layout verification tasks such as DRC, LVS, and parasitic extraction to ensure compliance with design and process requirements. Participating in design reviews and providing technical input to ensure the robustness and reliability of delivered IP blocks. Documenting layout methodologies, design decisions, and best practices to drive organizational knowledge sharing. Supporting silicon debug and post-silicon validation activities as needed. The Impact You Will Have: Drive the successful delivery of high-performance, low-power analog and mixed signal IP for next-generation semiconductor products. Enable rapid time-to-market for customer solutions by ensuring first-pass silicon success through meticulous layout practices. Enhance Synopsys’ reputation as a leader in advanced technology node design by delivering innovative, reliable, and manufacturable layouts. Influence the development of best-in-class methodologies and automation for layout design and verification. Contribute to cross-functional learning and mentorship within a diverse, inclusive team environment. Support customer engagements and help resolve complex technical challenges, ensuring satisfaction and repeat business. What You’ll Need: Minimum of 2 years of experience in analog and high-speed mixed signal layout at 5nm or below technology nodes. Proven expertise in full custom layout of SerDes blocks (CTLE, AFE, PLL, LDO, transmitter/receiver sub-blocks). Strong command of industry-standard EDA tools for layout and verification (e.g., Cadence Virtuoso, Mentor Calibre, Synopsys IC Compiler). Demonstrated ability to interpret and implement complex circuit schematics into robust, high-quality layouts. Hands-on experience with DRC, LVS, and parasitic extraction flows and methodologies. Who You Are: Detail-oriented, with a strong commitment to quality and continuous improvement. Collaborative and communicative, able to work seamlessly across multidisciplinary teams. Self-motivated and proactive, taking ownership of deliverables and driving them to completion. Flexible and adaptive, thriving in fast-paced, evolving environments. Curious, eager to learn, and enthusiastic about sharing knowledge with peers. Committed to diversity, equity, and inclusion in the workplace. The Team You’ll Be A Part Of: You will join a diverse and highly skilled team of analog and mixed signal design professionals who are passionate about pushing the boundaries of semiconductor technology. The team collaborates closely with global engineering, product, and customer teams, focusing on delivering best-in-class IP for advanced technology nodes. We foster a culture of innovation, mentorship, and continuous learning, where every voice is heard and every contribution matters. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values ; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await! Job Description: o Create System and FPGA designs to exercise all the use models targeted for each product mimicking end applications in a customer setting. o Write system and product level validation plans for new and existing silicon products and projects; execute per plan, record and communicate results o FPGA prototyping and emulation. Understanding spec., writing emulation plan and executing per plan. Record and communicate results. o Understand hardware architectures, use models and system level design implementations required to utilize the silicon features. o Be an effective contributor in a cross-functional team-oriented environment. o Write high quality code in Verilog, VHDL and C code for embedded processors. Maintain existing code. o Learn new system designs and validation methodologies. Understand FPGA architectures. o Be conversant with on-chip debug tool Requirements/Qualifications: Excellent verbal and written communication skills in English 5+ Years experience in Design with RTL coding in Verilog and VHDL and Verification of RTL Possess an in-depth understanding of hardware architectures, system level IC design implementation, knowledge of how to create end use scenarios Optimizing code for FPGA architectures Experience using Simulation (ModelSim) and Synthesis (Synplicity) tools Basic knowledge of embedded processors such as ARM Cortex-M3 or RISC and familiarity with AMBA protocols APB, AHB, AXI, ACE Working knowledge on embedded software C/C++ is also a plus Strong technical background in FPGA prototype emulation, and debug Strong technical background in silicon validation, failure analysis and debug Excellent Board level debug capabilities in lab environment : hands-on troubleshooting skills for digital logic and analog circuit on PCB’s using oscilloscopes, digital analyzers, protocol exercisers and analyzers, integrated logic analyzers (e.g. Synopsys Idenitfy, Xilinx Chipscope, Altera Signalscope, Lattice Reveal Design with RTL coding in Verilog and VHDL is a must Experience using Simulation (ModelSim) and Synthesis (Synplicity) tools Hands-on systems level design and debug experience with at least two of the following high-speed serial communications protocols: i. PCIe Gen1/2/3 ii. Interlaken (10.3125 Gbps) iii. CPRI (614.4Mbps – 12.672 Gbps) iv. SGMII or QSGMII v. XAUI or HiGig/+/II vi. 10GBASE-R/-KR vii. Serial Rapid IO Travel Time: 0% - 25% To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and detail-oriented engineer with a drive to deliver high-quality, innovative hardware solutions. You thrive in collaborative, cross-functional environments and are energized by working on world-class microprocessor IP that powers some of the most advanced embedded systems on the planet. With a strong foundation in electronics engineering or computer science, you bring at least five years of hands-on experience in ASIC physical design, particularly in physical verification and IR analysis. Your expertise enables you to navigate complex design flows, and you are keen to expand your knowledge by engaging with the latest industry tools and methodologies. You are comfortable scripting in Unix, Perl, and TCL, and you have a working knowledge of hardware description languages like Verilog or VHDL. You possess excellent written and verbal communication skills, allowing you to work effectively with international teams and assist in customer engagements. Your methodical and analytical mindset helps you troubleshoot and optimize designs for performance, power, and area. Eager to learn, you look forward to being involved in both in-house test chip projects and customer-facing design-ins, gaining exposure to a wide range of applications for Synopsys’ ARC processor IP. You are committed to continuous personal and professional growth, and you value the opportunity to contribute to a team that is shaping the future of microprocessor technology. What You’ll Be Doing: Developing and optimizing physical design implementation flows for ARC family microprocessor IPs, ensuring best-in-class performance and power efficiency. Performing comprehensive physical verification, including LVS, DRC, and IR drop analysis, to ensure first-pass silicon success. Collaborating with cross-functional teams, including logic design, verification, and library development, to drive seamless integration and qualification of IP. Supporting benchmarking, test chip implementation, and qualification activities for new microprocessor IP families. Assisting with customer support, design-ins, and technical sales engagements, providing insights into implementation best practices. Automating and enhancing existing design flows using scripting languages such as Perl and TCL to improve efficiency and reproducibility. Participating in internal knowledge-sharing initiatives and contributing to the continuous improvement of team processes and methodologies. The Impact You Will Have: Enable Synopsys customers to achieve rapid, successful integration of advanced ARC processor IP into their SoC designs. Drive the delivery of highly optimized, silicon-proven IP, reducing time-to-market for embedded and high-performance applications. Enhance the robustness and scalability of Synopsys’ implementation flows, setting industry benchmarks for physical design quality. Support the development and qualification of next-generation microprocessor IP, fueling innovation in diverse application domains. Strengthen customer relationships by providing expert technical guidance and support during pre- and post-sales engagements. Contribute to the continuous improvement of Synopsys’ engineering excellence, maintaining our leadership in silicon design. What You’ll Need: Bachelor’s degree in electronics engineering or computer science (Master’s preferred). Minimum 5 years of hands-on experience in ASIC physical design, with a focus on physical verification and IR analysis. Proficiency in scripting languages such as Unix shell, Perl, and TCL to automate design tasks. Exposure to hardware description languages such as Verilog or VHDL. Strong analytical and troubleshooting skills, with attention to detail in solving complex design challenges. Who You Are: A collaborative team player who communicates effectively with colleagues across the globe. Methodical and analytical, with a passion for continuous learning and improvement. Adaptable and open to new ideas, technologies, and design methodologies. Self-motivated and proactive in identifying and resolving technical issues. Customer-focused, with the ability to translate technical concepts into actionable solutions. The Team You’ll Be A Part Of: You’ll join a diverse, international team of experts dedicated to developing and delivering industry-leading microprocessor IP for the ARC family. The team works at the intersection of hardware design, implementation, and customer enablement, supporting a full suite of Synopsys memory compilers and standard cell libraries. You will collaborate closely with colleagues across logic design, verification, and applications engineering, learning from and contributing to a vibrant culture of innovation, knowledge sharing, and technical excellence. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and detail-oriented analog/mixed-signal engineer driven by a desire to create world-class solutions that enable the next generation of smart, connected devices. You thrive in fast-paced, collaborative environments and are excited by the challenges of high-speed SERDES development. You possess a strong foundation in analog transistor-level circuit design, particularly in nanometer CMOS technologies, and you have a proven track record of innovating and optimizing full-custom analog circuit macros. You are adept at translating system-level requirements into robust, high-performance designs and are eager to refine your skills by working alongside a diverse, global team of industry experts. Your curiosity and commitment to excellence fuel your ability to push technological boundaries, ensuring that your designs not only meet but exceed stringent performance, power, and area targets. You value clear communication, enjoy mentoring and learning from peers, and are motivated by the impact your work has on products that power everything from cloud infrastructure to autonomous vehicles. If you’re looking to make a tangible difference in the world of silicon design and crave opportunities for continuous learning and professional growth, you’ll find your home at Synopsys. What You’ll Be Doing: Designing and developing full-custom analog circuit macros for high-speed SERDES PHY IP, including analog front-end transceivers, voltage/current-mode drivers, PLLs, DLLs, regulators, equalizers, and more in planar and FinFET CMOS technologies. Ensuring analog sub-block performance adheres to SERDES standards and architecture specifications, with rigorous simulation and verification. Identifying and refining circuit implementations to achieve optimal power, area, and performance targets. Proposing and executing design and verification strategies that leverage advanced simulator features for highest quality output. Collaborating closely with layout engineers to minimize parasitic effects, device stress, and process variations in physical designs. Presenting simulation data and design reviews to peers, cross-functional teams, and customers, and consulting on electrical characterization within the SERDES IP product. Documenting design features, test plans, and contributing to the continuous improvement of design methodologies and best practices. The Impact You Will Have: Enable the delivery of industry-leading, high-speed SERDES IP that accelerates the performance of next-generation silicon chips. Contribute to faster, more reliable chip design cycles by optimizing analog circuits for power, cost, and performance. Advance Synopsys’ reputation as the global leader in silicon design and verification through technical innovation and excellence. Collaborate across global teams, sharing knowledge and driving improvements in design methodologies and processes. Support customers in achieving their product goals by providing robust, high-quality IP solutions and expert consultation. Play a key role in enabling the technologies that power AI, 5G, cloud computing, and the Internet of Things. What You’ll Need: BE + 3 years of relevant experience or MTech + 2 years in mixed-signal analog or custom circuit design. Educational background in Electrical/Electronics/VLSI Engineering or related fields. Strong proficiency in analog transistor-level design in nanometer CMOS technologies. Experience with multi-Gbps, high-speed design protocols such as PCIe, Ethernet, SATA, USB, etc. Expertise in full-custom design and verification using SPICE simulation and static timing analysis (STA) tools. Familiarity with ESD/latchup verification, crosstalk analysis, and sub-micron design methodologies. Understanding of layout effects, parasitic extraction, and design for manufacturability in advanced process nodes. Who You Are: Collaborative team player who thrives in a multicultural, global environment. Excellent communicator with strong presentation and documentation skills. Analytical thinker with a keen attention to detail and a passion for problem-solving. Proactive, self-motivated, and eager to take ownership of challenging projects. Open to feedback, with a growth mindset and commitment to continuous learning. Adaptable and resilient in the face of technical challenges and shifting priorities. The Team You’ll Be A Part Of: You’ll join Synopsys’ High-Speed SERDES Analog Design team, a group of innovative engineers specializing in the development of advanced analog and mixed-signal circuits for next-generation PHY IP. The team is renowned for its technical excellence, collaborative spirit, and commitment to pushing the boundaries of high-speed silicon design. Working alongside experienced professionals in Noida and across global sites, you’ll contribute to a culture of innovation, mentorship, and shared success. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Category Engineering Hire Type Employee Job ID 12393 Remote Eligible No Date Posted 29/07/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned engineer with a passion for pushing the boundaries of technology. With 3 -7 years of experience, you bring a wealth of knowledge in software architecture. You excel in C/C++ software development, digital simulation, compiler optimizations and your strong background in design patterns, data structures, and algorithms sets you apart. Your expertise in Verilog, SystemVerilog, coupled with your experience in Unix/Linux platforms, makes you a valuable asset. You are well-versed in developer tools like gdb and Valgrind. Your analytical and problem-solving skills are top-notch, and you are always eager to learn and explore new technologies. As a highly enthusiastic and energetic team player, you are ready to go the extra mile to achieve success. What You’ll Be Doing: - Designing, developing, and troubleshooting core algorithms for compiler. - Collaborating with local and global teams to enhance runtime performance for verilog compiler. - Engaging in pure technical roles focused on software development and architecture. - Utilizing your knowledge of digital simulation flows and EDA tools to drive innovation. - Leveraging your expertise in Verilog, SystemVerilog, and VHDL to develop cutting-edge solutions. The Impact You Will Have: - Driving technological innovation in chip design and verification. - Enhancing the performance and quality of simulation tools used globally. - Solving complex compiler optimizations problems to improve simulation performance. - Collaborating with cross-functional teams to achieve project milestones. - Pioneering new software architectures that set industry standards. What You’ll Need: - Strong hands-on experience in C/C++ based software development. - Deep understanding of design patterns, data structures, algorithms, and programming concepts. - Knowledge of ASIC design flow and EDA tools and methodologies. - Proficiency in Verilog, SystemVerilog, and VHDL HDL. Who You Are: - Highly enthusiastic and energetic team player with excellent communication skills. - Strong desire to learn and explore new technologies. - Effective problem-solver with a keen analytical mind. - Experienced in working on Unix/Linux platforms. - Adept at using developer tools such as gdb and Valgrind. The Team You’ll Be A Part Of: You will be part of the performance team in Digital Simulation. You will work closely with both local and global teams to drive technological advancements and achieve project goals. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Category Interns/Temp Hire Type Intern Job ID 9722 Date Posted 30/07/2025 We Are: Drive technology innovations that shape the way we live and connect. Our technology drives the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life. From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world. Apprenticeship Experience: At Synopsys, Apprentices dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide—and having fun in the process! You'll have the freedom to

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Knowledge in Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Good knowledge of Tcl/Perl Scripting Strong problem-solving skills and good communication skills. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3- 6yrs years of experience in Physical Design/Implementation Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Bachelor's/Master’s degree in Electrical/Electronic Engineering from reputed institution 2-10 years of experience in Physical Design/Implementation Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

www.omnidesigntech.com Senior SoC Director / SoC Director Bangalore / Hyderabad About Omni Design Technologies Omni Design Technologies is a leading provider of high-performance, ultra-low power IP cores, from 28nm down through advanced FinFET nodes, which enable differentiated system-on-chip (SoC), in applications ranging from 5G, wireline and optical communications, LiDAR, radar, automotive networking, AI, image sensors, and the internet-of-things (IoT). Our data converter (ADC and DAC) IP cores range from 6-bit to 14-bit resolution and from a few MSPS to more than 100 GSPS sampling rates. Omni Design, founded in 2015 by semiconductor industry veterans, has an excellent track record of innovation and collaboration with customers to enable their success. The company is headquartered in Milpitas, California with additional design centers in Fort Collins-Colorado, Bangalore-India, Hyderabad-India, Dublin-Ireland, Boston-Massachusetts. Bangalore Engineering – Digital Circuit Design / Hyderabad / Bangalore SOC Development – Engineering / Full-time / Hybrid Omni Design is working on exciting solutions and chips for next generation automotive and space applications and looking for talented and capable engineers. The Manager of digital and mixed-signal engineering will be responsible for development of mixed-signal SOC being developed at ODT and build the digital engineering team and will work Analog/RF engineering, FW engineering, verification, Systems Validation team, Operations, SOC Architects, and report to the VP / SVP of ASIC Engineering. Roles and Responsibilities Manage digital team, hire, and retain best talent Lead SOC integration design team to develop and productize next generation mixed-signal RF/communication SOCs Work with cross-functional project teams to define product specifications, system architecture, HW/SW partitioning, and execution plan Implement best SoC development practices and improve design methodology to maximize efficiency and predictability Deliver chip architecture, design, integration, programming model, verification, and manage hand-off to backend Support Silicon and System Validation, support system integration, and production testing Drive innovation and provides leadership to the organization to ensure world-class system solutions and flawless execution Qualifications BSEE Required, MSEE Preferred Proven track record of success in high-performance/high-volume semiconductor industry SoC, embedded CPU and bus architectures, networking, and control interfaces Communications / DSP algorithms and power / area efficient implementations Digital IC design, design for low power and high speed, design for test (DFT) System modeling, RTL coding, Lint / CDC checking, simulation, synthesis, power analysis, timing analysis in Cadence / Synopsys design environments Directed and constrained random verification, UVM methodology Embedded systems FPGA emulation, lab debug and chip validation Project planning and execution, and performing design tradeoffs to achieve performance, power, die size, and schedule targets Self-motivated, excellent communication skills, and ability to excel and to provide leadership in a fast-paced environment Senior Management experience preferred Work with architecture, physical design, and design teams to lead the implementation of the digital architecture. Develop and refine specification of the micro-architecture for the digital architecture. Is in tune with industry trends and contributes to consistent roadmap decisions. Experience 15-30+ years of experience in the area of RTL design and verification of silicon At Least 3+ years experience in leading low-power mixed-Signal SOC design 10+ years of experience with FPGA architecture specification and design (Altera or Xilinx) for high-speed serial protocols, including USB-SS, PCIe, SATA/SAS, DisplayPort Experience in leading, specifying, and work with Analog/RF team in developing, verifying, and productizing SERDES, CDR, and PLL/DLL designs Experience with USB 3.0, DisplayPort, PCIe, or SATA based silicon designs preferred Strong background in analog/mixed-signal integrated SOC Development Strong Hardware design knowledge and familiarity with signal integrity Strong foundation in SoC architecture, design, verification and physical implementation Strong analytical problem solving, and attention to details Knowledge of wireless, mobile, and storage domains Expertise in Verilog/System Verilog, C/C++/SystemC, UVM, Scripting languages like Perl/Python, etc. Excellent technical documentation skills Excellent written and verbal communication skills Excellent interpersonal skills, self-motivated, self-starter Experience in startup environment Expectations Put the RTL for the Full chip together. Evaluate the IP we have to license – like PCIe, LPDDR4, JESD 204C PHY Help develop any BIST Work with Verification Team to develop the FC Simulation test suites Develop the RTL for the various state machines and interfaces Run a few of the simulations Help with the FC simulations debug Help close the timing issues if any come up and work with the PD person to resolve any SI issues. Be a mentor and lead a team of Digital design engineers Work with Systems and Test engineering team to help validate the parts and release them to production We are looking for trailblazers ... We strongly believe that the pace of the ongoing hardware revolution will be greatly accelerated by Design’s IP cores and the rapidly emerging semiconductor embedded design business ecosystem. we have created an exciting environment with amazing talent across multiple disciplines. We like self-motivated individuals, we encourage initiative, we look for leadership qualities, we value teamwork, we like diversity, and we reward excellence. We are looking for trailblazers to bring our vision to fruition. If you are interested in making an impact as part of a young, fast growing, cutting edge technology company, please reach out to us. We are a equal opportunity employer. We offer excellent compensation. We seek individuals that share our high standards and commitment to excellence. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com 'Mining The Knowledge Community'

We Are Hiring! 📢Role: Design Verification Engineer 📌Experience: 3 - 8 Years 📌Location: Hyderabad Key Responsibilities: 🔹M.Tech/B.Tech in Electronics and Communication Engineering or related field and 3+ years of relevant experience. 🔹Proficiency in Verilog, System Verilog and UVM methodology. 🔹Ability to develop VIPs. 🔹Write test plans based on the feature list. 🔹Strong understanding of Digital Design Concepts, SoC Architecture, Processor architecture. 🔹Ability to debug test failures, excellent problem solving skills. 🔹Scripting (Perl, Python) for test automation. 🔹Familiarity with Simulati on environment (Synopsys, Cadence). 🔹Knowledge on Assertion based Verification. 🔹Knowledge on SystemC modelling is a plus. 🔹Knowledge of AMBA protocols. 🔹Knowledge of the C programming language is a plus. 🔹Strong in Verilog, System Verilog, UVM, and digital design concepts. Bonus Skills (Preferred but Not Mandatory): 🔹SystemC, PCIe/CXL/DDR/USB, and C programming. 📩 Send Your Resume: hr1@vconnectech.in 📞 9281014443 🌐 For more info visit: vconnectechsystems.com #Hiring #DesignVerification #VLSIJobs #UVM #SystemVerilog #VerificationEngineer #SemiconductorJobs #HyderabadJobs #TechJobs #Verilog #EmbeddedJobs #DigitalDesign #SoC #EDAtools #Python #Perl #AMBA #SystemC #FirmwareJobs #ChipDesign #CareerOpportunity #JobOpening #JoinOurTeam #VConnecTechSystems #EmbeddedSystems #VLSI #HiringNow #Opentowork

Master's degree in Electrical Engineering or a related field Experience with industry-standard physical design tools (Cadence, Synopsys, Mentor Graphics) Knowledge of advanced process nodes (7nm, 5nm, etc.) Experience with scripting languages such as Python, TCL, or Perl Strong understanding of VLSI design principles Experience in low-power design techniques Bachelor's or Master's degree in Electrical Engineering or related field Minimum of 5 years of experience in physical design of digital, mixed-signal, or RF integrated circuits Expert knowledge of industry-standard EDA tools for physical design and verification, such as Synopsys ICC, Primetime, and StarRC Proven experience with advanced physical implementation techniques, such as multi-patterning, layout-dependent effects, and low-power design Excellent analytical and problem-solving skills Strong interpersonal and communication skills with the ability to collaborate effectively with cross-functional teams Self-motivated and able to work independently in a fast-paced and dynamic environment

The job opportunity is based in Bangalore, Karnataka, India, where a new Silicon R&D center is being established. The center aims to pioneer the IPs that will power the digital ASICs for the future mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks, including the Ericsson Radio System - RAN Compute, Radio, and Transport. The goal is to enable communication service providers to exceed the expectations of their end-customers. The design centers aim to lead innovation in the telecommunications sector by leveraging cutting-edge tools and methodologies. As a team member, you will play a crucial role in shaping the future of global connectivity and contributing to the advancement of 5G and 6G technologies. You will have the opportunity to collaborate with talented teams globally, fostering a collaborative and innovative work environment that encourages creativity and teamwork. The work environment prioritizes work-life balance, professional growth, and continuous learning opportunities. The culture values diversity, innovation, and inclusivity. Key Responsibilities: - Participate in the verification of designs at the block or subsystem level. - Define and implement UVM-based test environments. - Contribute to the development and execution of Verification Strategies and Plans. - Develop, run, and debug test cases to ensure design quality. - Optimize verification methodologies and generate documentation. - Collaborate with verifiers, designers, and architects. - Build competence in the technical domain and engage in cross-team collaboration. Required Qualifications: - Bachelor's degree in electrical or computer engineering. - 5+ years of industry experience in verification using SystemVerilog and UVM. - Strong experience in developing verification test plans and test cases, formal verification, and implementing scoreboards and checkers. - Proficiency in SystemVerilog Assertions. Additional Requirements: - Experience with Cadence or Synopsys verification suites. - Team-oriented with strong communication skills. - Attention to detail, commitment to quality, and focus on meeting project deadlines. Preferred Skills: - Understanding of radio access systems and low-power design verification. - Knowledge of continuous integration systems, simulation environments, and issue-tracking tools. - Experience in verification of hardware domains such as AMBA-based designs, ARM-based systems, and digital signal processing systems. Join Ericsson for an outstanding opportunity to push the boundaries of technological possibilities, collaborate with diverse innovators, and craft solutions for the future.,

As a Formal Verification Engineer at our Global Technology organization, you will be responsible for leading formal verification activities for single or multiple design blocks and IPs. This includes developing and executing formal verification strategies and test plans to ensure the correctness of designs. Your role will involve creating detailed formal verification plans, identifying design properties, and collaborating with design teams to enhance micro-architectures. You will play a key role in crafting innovative solutions to verify complex design architectures by developing reusable formal models and verification code bases. Additionally, you will mentor junior team members and provide technical leadership in formal verification methodologies, including training on industry-standard tools and techniques. Collaboration with cross-functional teams, such as design and verification, will be essential to ensure the seamless integration of formal verification into the overall verification flow. The ideal candidate for this position should possess expertise in formal verification techniques and methodologies, a strong command of System Verilog and Universal Verification Methodology (UVM), and hands-on experience with tools like Jasper or VC Formal (Synopsys). You should have the ability to develop reusable verification models and formal strategies, along with strong debugging, problem-solving, and team collaboration skills. Experience in mentoring engineers and driving technical leadership will be beneficial in this role. To qualify for this position, you should hold a Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or a related field. Join us in our dynamic team environment where you can contribute to cutting-edge technology developments and drive innovation in formal verification processes.,

About Newton School Come be part of a rocket ship thats creating a massive impact in the world of education! On one side you have over a million college graduates every year with barely 5% employability rates and on the other side, there are thousands of companies struggling to find talent. Newton School aims to bridge this massive gap through its personalized learning platform. We are building an online university and solving the deep problem of the employability of graduates.We have a strong core team consisting of alumni from IITs and IIM, having several years of industry experience in companies like Unacademy, Inmobi, Ola, and Microsoft - among others. On this mission, we are backed by some of the most respected investors around the world, - RTP Global, Nexus Venture Partners, and a slew of angel investors including CREDs Kunal Shah, Flipkarts Kalyan Krishnamoorthy, Unacademy and Razorpay founders, Udaans Sujeet Kumar among others. About the Role: We are looking for VLSI engineers with a strong foundation in digital systems and computer architecture to take on an academic teaching role. This full-time position is ideal for engineers with hands-on experience in RTL design, processor components, or SoC architecture who are excited to teach how computers are built from logic gates to microarchitectures. You will lead classroom instruction, mentor student projects, and help shape curriculum at the intersection of digital logic, hardware systems, and architectural design. Key Responsibilities Teach Computer Architecture by drawing from real-world VLSI design experience covering instruction sets, pipelining, memory systems, and microprocessor implementation. Guide students through lab simulations and RTL projects that explore how architectural concepts are implemented in hardware (e.g., datapaths, control units, cache design). Design and evaluate lab work, assessments, and hands-on student projects that simulate industry applications. Mentor and support students in their academic and professional development journeys. Continuously update course content to reflect current industry trends and technologies. Contribute to curriculum development, academic research, and internal learning initiatives. Host technical workshops, design challenges, and guest sessions to extend classroom learning. Collaborate with fellow faculty, industry mentors, and curriculum designers to enrich learning outcomes Must-Have Skills & Qualifications B.Tech / M.Tech / Ph.D. in Computer Engineering, Electronics, Electrical, or a related field. Experience working on processor subsystems, SoC integration, RTL for custom compute blocks, or related architecture-level VLSI work. Strong technical command over topics such as: ? Computer Architecture: Instruction sets, microprocessors, memory hierarchy, pipelining, cache systems. ? VLSI Design: CMOS circuits, RTL design, ASIC/FPGA flow, timing analysis, layout. Proficiency in tools such as Cadence, ModelSim, Synopsys, Xilinx, Mentor Graphics, etc. Working knowledge of HDL languages (Verilog/VHDL) and scripting (Tcl, Shell, Python). Excellent communication and classroom delivery skills. Demonstrated interest in teaching and mentoring students. Good-to-Have Skills: Prior experience as a faculty member or technical trainer. Familiarity with RISC-V, ARM-based processors, SoC Design, or low-power systems Exposure to DFT, verification methodologies, and EDA flows. Contributions to open-source, academic publications, or online technical content. Comfort with digital tools, LMS platforms, and collaborative teaching formats. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and detail-oriented analog/mixed-signal engineer driven by a desire to create world-class solutions that enable the next generation of smart, connected devices. You thrive in fast-paced, collaborative environments and are excited by the challenges of high-speed SERDES development. You possess a strong foundation in analog transistor-level circuit design, particularly in nanometer CMOS technologies, and you have a proven track record of innovating and optimizing full-custom analog circuit macros. You are adept at translating system-level requirements into robust, high-performance designs and are eager to refine your skills by working alongside a diverse, global team of industry experts. Your curiosity and commitment to excellence fuel your ability to push technological boundaries, ensuring that your designs not only meet but exceed stringent performance, power, and area targets. You value clear communication, enjoy mentoring and learning from peers, and are motivated by the impact your work has on products that power everything from cloud infrastructure to autonomous vehicles. If you’re looking to make a tangible difference in the world of silicon design and crave opportunities for continuous learning and professional growth, you’ll find your home at Synopsys. What You’ll Be Doing: Designing and developing full-custom analog circuit macros for high-speed SERDES PHY IP, including analog front-end transceivers, voltage/current-mode drivers, PLLs, DLLs, regulators, equalizers, and more in planar and FinFET CMOS technologies. Ensuring analog sub-block performance adheres to SERDES standards and architecture specifications, with rigorous simulation and verification. Identifying and refining circuit implementations to achieve optimal power, area, and performance targets. Proposing and executing design and verification strategies that leverage advanced simulator features for highest quality output. Collaborating closely with layout engineers to minimize parasitic effects, device stress, and process variations in physical designs. Presenting simulation data and design reviews to peers, cross-functional teams, and customers, and consulting on electrical characterization within the SERDES IP product. Documenting design features, test plans, and contributing to the continuous improvement of design methodologies and best practices. The Impact You Will Have: Enable the delivery of industry-leading, high-speed SERDES IP that accelerates the performance of next-generation silicon chips. Contribute to faster, more reliable chip design cycles by optimizing analog circuits for power, cost, and performance. Advance Synopsys’ reputation as the global leader in silicon design and verification through technical innovation and excellence. Collaborate across global teams, sharing knowledge and driving improvements in design methodologies and processes. Support customers in achieving their product goals by providing robust, high-quality IP solutions and expert consultation. Play a key role in enabling the technologies that power AI, 5G, cloud computing, and the Internet of Things. What You’ll Need: BE + 3 years of relevant experience or MTech + 2 years in mixed-signal analog or custom circuit design. Educational background in Electrical/Electronics/VLSI Engineering or related fields. Strong proficiency in analog transistor-level design in nanometer CMOS technologies. Experience with multi-Gbps, high-speed design protocols such as PCIe, Ethernet, SATA, USB, etc. Expertise in full-custom design and verification using SPICE simulation and static timing analysis (STA) tools. Familiarity with ESD/latchup verification, crosstalk analysis, and sub-micron design methodologies. Understanding of layout effects, parasitic extraction, and design for manufacturability in advanced process nodes. Who You Are: Collaborative team player who thrives in a multicultural, global environment. Excellent communicator with strong presentation and documentation skills. Analytical thinker with a keen attention to detail and a passion for problem-solving. Proactive, self-motivated, and eager to take ownership of challenging projects. Open to feedback, with a growth mindset and commitment to continuous learning. Adaptable and resilient in the face of technical challenges and shifting priorities. The Team You’ll Be A Part Of: You’ll join Synopsys’ High-Speed SERDES Analog Design team, a group of innovative engineers specializing in the development of advanced analog and mixed-signal circuits for next-generation PHY IP. The team is renowned for its technical excellence, collaborative spirit, and commitment to pushing the boundaries of high-speed silicon design. Working alongside experienced professionals in Noida and across global sites, you’ll contribute to a culture of innovation, mentorship, and shared success. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

We are hiring a strong Design Verification (DV) engineer. This opening is with our CPU Design Verification team. This role is for you if you are curious about Computer organisation and design, and possess strong digital design fundamentals. This role is with a Hardware design and verification team that develops and builds chips enabling the AI revolution. What You Will Be Doing You will own and develop verification components, such as checkers, models, coverage, and stimulus. You will work closely with the Architecture, RTL, and Formal Verification teams to design and verify the microarchitecture. You will propose methodology, tests and frameworks to ensure bug-free RTL. You will participate in Design specification reviews, architecture reviews, and reviews of other unit test plans. Build DV code and Algorithms that are of high quality, with excellent time and space complexity, that scale well to higher testbenches. You will actively work on understanding the ARM architecture and coherency protocols, such as CHI. You will learn the microarchitectures of the interconnect, cache, ordering, and memory units in the system. This role will enable you to develop expertise in CPU load/store, MMU, caching, coherency/consistency, fabric, and related areas. You will design and verify the next generation of NVIDIA CPUs and SoCs! What We Need To See BS or MS in Electronics Engineering with a minimum of 3+ years of proven experience Knowledge in Design Verification Methodologies SV/UVM verification languages and methodologies. Strong problem solving - more specifically, DV code like stimulus, models, constraints, coverage Prior experience in Testbench architecture and Verification components A strong understanding of CPU architecture and microarchitecture Way To Stand Out From The Crowd Understanding CPU Architecture concepts related to load/store, caching, coherency, consistency and ordering Strong Python and other software methodologies for scripting and build automation Experience in handling EDA tools from Synopsys or Cadence With competitive salaries and a generous benefits package, we are widely considered as one of the technology world’s most desirable employers. We have some of the most dedicated and experienced professionals in the world working for us, and, due to unprecedented growth, our elite engineering teams are expanding rapidly. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you! We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, colour, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. JR1999557

Category Engineering Hire Type Employee Job ID 12350 Remote Eligible No Date Posted 28/07/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned digital design expert with a passion for innovation and a drive for technical excellence. With over 15 years of hands-on experience in ASIC digital design using Verilog, you have a proven track record in developing high-performance microprocessor IP and optimizing designs for performance, area, power, and speed. Your background in RISC architectures and embedded processor design makes you a go-to authority in your field. You thrive on solving complex engineering challenges and have a deep understanding of microprocessor architecture, including multi-core systems and digital signal processing. Your programming skills in assembly and C/C++ enable you to bridge the gap between hardware and software, ensuring efficient and robust designs. Collaboration is at your core—you excel at working with multi-site teams, sharing your expertise, and mentoring junior engineers. Your attention to detail, commitment to quality, and ability to debug challenging issues set you apart. You are driven by continuous learning and are always eager to adopt and deploy the latest development techniques. As a Principal Engineer, you take ownership of your projects, communicate effectively with stakeholders, and contribute to both technical and project management aspects of product development. What You’ll Be Doing: Architecting and implementing embedded RISC microprocessor IP at both architectural and RTL levels using Verilog. Optimizing processor designs for performance, speed, area, and power to meet demanding silicon requirements. Generating comprehensive hardware benchmarks, analyzing results, and iterating on design improvements. Developing standalone Verilog testbenches and collaborating closely with the verification team to ensure thorough validation. Debugging complex design issues and bugs, proactively identifying root causes and implementing robust solutions. Maintaining and enhancing the current processor product line and derivative products, ensuring continuous improvement and innovation. Developing and managing detailed project plans, working in close partnership with program managers and cross-functional teams. Contributing to architectural reviews, technical documentation, and process improvements across multi-site teams. The Impact You Will Have: Drive the development of cutting-edge processor IP that powers next-generation smart devices and systems. Enhance the performance, efficiency, and reliability of Synopsys’ industry-leading ARC Processor family. Enable customers to achieve breakthrough results in silicon design and integration through your technical leadership. Mentor and elevate the skills of fellow engineers, fostering a culture of technical excellence and innovation. Shape the direction of processor architecture and design methodologies within the organization. Support the successful delivery of high-quality silicon solutions that meet and exceed customer expectations. Strengthen Synopsys’ reputation as a leader in semiconductor IP by contributing to successful product launches and deployments. What You’ll Need: Bachelor’s degree or higher in Electrical Engineering, Computer Engineering, or related field. 15+ years of experience in digital design, specifically using Verilog for ASIC development. Deep expertise in RISC architectures and microprocessor IP design, including multi-core systems. Strong programming skills in assembly language and C/C++ for embedded systems. Proven ability to optimize digital designs for performance, area, speed, and power. Experience with debugging, verification, and developing standalone testbenches. Familiarity with DSP techniques and multi-site development environments is a plus. Who You Are: Analytical thinker with exceptional problem-solving skills and attention to detail. Effective communicator who can articulate complex technical concepts to diverse audiences. Collaborative team player who thrives in a multi-site, multicultural environment. Proactive, self-motivated, and able to manage multiple priorities efficiently. Mentor and leader who supports the growth and development of colleagues. Adaptable and open to learning new technologies and methodologies. The Team You’ll Be A Part Of: You’ll join the Synopsys Designware ARC Processor development team—a global group of talented engineers dedicated to pushing the boundaries of embedded processor technology. The team values innovation, knowledge sharing, and collaboration, working across multiple sites to deliver world-class IP solutions that enable Synopsys’ customers to succeed in a dynamic marketplace. You’ll be empowered to contribute your expertise, champion best practices, and help shape the future of high-performance silicon design. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Category Engineering Hire Type Employee Job ID 12379 Remote Eligible No Date Posted 28/07/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and detail-oriented engineer with a drive to deliver high-quality, innovative hardware solutions. You thrive in collaborative, cross-functional environments and are energized by working on world-class microprocessor IP that powers some of the most advanced embedded systems on the planet. With a strong foundation in electronics engineering or computer science, you bring at least five years of hands-on experience in ASIC physical design, particularly in physical verification and IR analysis. Your expertise enables you to navigate complex design flows, and you are keen to expand your knowledge by engaging with the latest industry tools and methodologies. You are comfortable scripting in Unix, Perl, and TCL, and you have a working knowledge of hardware description languages like Verilog or VHDL. You possess excellent written and verbal communication skills, allowing you to work effectively with international teams and assist in customer engagements. Your methodical and analytical mindset helps you troubleshoot and optimize designs for performance, power, and area. Eager to learn, you look forward to being involved in both in-house test chip projects and customer-facing design-ins, gaining exposure to a wide range of applications for Synopsys’ ARC processor IP. You are committed to continuous personal and professional growth, and you value the opportunity to contribute to a team that is shaping the future of microprocessor technology. What You’ll Be Doing: Developing and optimizing physical design implementation flows for ARC family microprocessor IPs, ensuring best-in-class performance and power efficiency. Performing comprehensive physical verification, including LVS, DRC, and IR drop analysis, to ensure first-pass silicon success. Collaborating with cross-functional teams, including logic design, verification, and library development, to drive seamless integration and qualification of IP. Supporting benchmarking, test chip implementation, and qualification activities for new microprocessor IP families. Assisting with customer support, design-ins, and technical sales engagements, providing insights into implementation best practices. Automating and enhancing existing design flows using scripting languages such as Perl and TCL to improve efficiency and reproducibility. Participating in internal knowledge-sharing initiatives and contributing to the continuous improvement of team processes and methodologies. The Impact You Will Have: Enable Synopsys customers to achieve rapid, successful integration of advanced ARC processor IP into their SoC designs. Drive the delivery of highly optimized, silicon-proven IP, reducing time-to-market for embedded and high-performance applications. Enhance the robustness and scalability of Synopsys’ implementation flows, setting industry benchmarks for physical design quality. Support the development and qualification of next-generation microprocessor IP, fueling innovation in diverse application domains. Strengthen customer relationships by providing expert technical guidance and support during pre- and post-sales engagements. Contribute to the continuous improvement of Synopsys’ engineering excellence, maintaining our leadership in silicon design. What You’ll Need: Bachelor’s degree in electronics engineering or computer science (Master’s preferred). Minimum 5 years of hands-on experience in ASIC physical design, with a focus on physical verification and IR analysis. Proficiency in scripting languages such as Unix shell, Perl, and TCL to automate design tasks. Exposure to hardware description languages such as Verilog or VHDL. Strong analytical and troubleshooting skills, with attention to detail in solving complex design challenges. Who You Are: A collaborative team player who communicates effectively with colleagues across the globe. Methodical and analytical, with a passion for continuous learning and improvement. Adaptable and open to new ideas, technologies, and design methodologies. Self-motivated and proactive in identifying and resolving technical issues. Customer-focused, with the ability to translate technical concepts into actionable solutions. The Team You’ll Be A Part Of: You’ll join a diverse, international team of experts dedicated to developing and delivering industry-leading microprocessor IP for the ARC family. The team works at the intersection of hardware design, implementation, and customer enablement, supporting a full suite of Synopsys memory compilers and standard cell libraries. You will collaborate closely with colleagues across logic design, verification, and applications engineering, learning from and contributing to a vibrant culture of innovation, knowledge sharing, and technical excellence. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Job Description HPC is an organization responsible for Renesas' business operations primarily focused on automotive MCUs (Microcontrollers) and SoCs (System-on-Chips). It specializes in high-performance computing technology that supports the evolution of automobiles, providing essential semiconductors for next-generation automotive systems such as advanced driver assistance systems (ADAS), connected cars, EV control, and infotainment. HPC offers diverse roles, including MCU/SoC design and development, marketing, and business management. HPC operates globally, collaborating with locations in Japan, the United States, Europe, China, India, and other countries. We are seeking a highly motivated and experienced Principal SoC/MCU Verification Engineer to join our team. In this role, you will contribute to the verification of complex System-on-Chip (SoC/MCU) designs, ensuring functionality, performance, and quality meet project and customer specifications. This position requires expertise in advanced verification methodologies, formal verification, strong technical leadership, and excellent problem-solving skills. Principal Engineer, DV Job Description We are seeking a highly motivated and experienced Principal SoC/MCU Design Verification Engineer to join our team. In this role, you will contribute to the verification of complex System-on-Chip (SoC/MCU) designs, ensuring functionality, performance, and quality meet project and customer specifications. This position requires expertise in advanced verification methodologies, strong technical leadership, and excellent problem-solving skills. Key Responsibilities Formal Verification Strategy: Define and implement formal verification methodologies for pre-silicon validation. Tool Ownership: Master industry tools (e.g., Cadence JasperGold, Synopsys VC Formal) to prove correctness of RTL designs. Constraint Development: Create assertions (SVA), assumptions, and cover points to model design behavior. Debugging: Root-cause formal failures and collaborate with RTL teams to resolve design flaws. Cross-Team Collaboration: Work with architects, designers, and DV teams to align formal efforts with simulation/emulation. 12+ years of experience required. Soft Skills Demonstrated ability to provide clear and transparent communication within teams and with global customers. Agile mindset to adapt to dynamic project requirements and timelines. Innovative thinker capable of contributing ideas to enhance designs or optimize workflows. Proven ability to manage daily tasks and lead a design team with a sense of ownership and accountability. Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement . Job title Principal Engineer- Design Verification Department Engineering Location Hyderabad Remote No Requisition ID 20021202_2025-06-30

Job Title: Sr. Staff Analog/IO Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned and enthusiastic professional who thrives on solving complex technical challenges and is committed to ongoing learning. You excel in dynamic environments and embrace advanced technologies with curiosity and confidence. With a proven track record in high-speed analog and mixed-signal circuit design, you bring a deep understanding of circuit analysis, semiconductor physics, and signal integrity. As a natural leader, you are adept at guiding and motivating teams, fostering collaboration, and driving projects to successful completion. Your expertise extends to modeling complex, non-linear circuit behavior for stability and jitter analysis, and you are skilled at micro-architecting circuits from initial specifications to final implementation. You are comfortable managing regression analysis and collaborating with design, layout, and ESD teams to resolve challenges and align on requirements. Your approach is detail-oriented and strategic, always seeking ways to optimize power, performance, and area (PPA) in your designs while reducing turnaround times. You value open communication, knowledge sharing, and mentoring, and you are dedicated to staying updated with the latest advancements in analog design. Your passion for technology and innovation inspires those around you, and your commitment to continuous improvement ensures you deliver impactful solutions that shape the future of our industry. What You’ll Be Doing: Collaborating with design, layout, and ESD teams to align requirements and efficiently resolve bottlenecks. Innovating and refining design methodologies to enhance scalability, efficiency, and reliability of analog and mixed-signal circuits. Designing, developing, and verifying high-speed analog and mixed-signal integrated circuits, ensuring they meet stringent performance criteria. Modeling complex and non-linear circuit behaviors to linear models for effective stability and jitter analysis. Performing rigorous circuit simulations and layout verifications to ensure accuracy and optimal performance. Optimizing circuit designs for power, performance, and area (PPA), continuously seeking ways to reduce turnaround time. Contributing to the development and documentation of best practices and methodologies for analog design. The Impact You Will Have: Advance the design and verification of high-speed analog and mixed-signal ICs, enabling next-generation technology solutions. Ensure the accuracy, reliability, and robustness of analog designs through meticulous verification and testing. Collaborate across disciplines to deliver innovative, high-performance products that meet evolving market demands. Continuously improve design methodologies and processes, raising the standard for excellence in analog design. Support the development of industry-leading technologies that power Synopsys’ portfolio and customer success. Drive innovation, efficiency, and quality in all aspects of analog design, reinforcing Synopsys’ leadership in the field. What You’ll Need: Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field. 10+ years of experience in analog circuit design and analysis. Deep expertise in analog circuit design and analysis techniques, including high-speed and mixed-signal environments. Proficiency in modeling complex/non-linear circuit behavior for stability and jitter analysis. Strong understanding of network/transmission line/SI analysis and semiconductor device physics. Demonstrated ability to micro-architect circuits from specifications, focusing on enhancing PPA and reducing turnaround time. Experience with design reliability analysis and modern EDA tools for simulation and verification. Who You Are: A strong leader with excellent communication and mentoring skills. Innovative and committed to continuous improvement. Detail-oriented with a strategic mindset and problem-solving abilities. Collaborative, with the ability to work effectively in a cross-functional team environment. Passionate about technology and eager to work on cutting-edge projects. You are a meticulous and innovative leader who excels in high-speed analog and mixed-signal design. Your ability to communicate effectively and work collaboratively with cross-functional teams makes you an essential team leader. You are passionate about staying current with the latest advancements in analog design and are always looking for ways to improve design methodologies and processes. Your strong technical skills, combined with your problem-solving abilities and attention to detail, enable you to tackle complex challenges and drive innovation at Synopsys. The Team You’ll Be A Part Of: You will join a team of dedicated professionals who are passionate about analog and mixed-signal design. Our team collaborates closely with various business groups to deliver high-performance integrated circuits that meet market demands. We value innovation, collaboration, and continuous learning, and we are committed to making a significant impact on the future of technology. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. If you have the capability to make things happen, drive results, and work with a Yes-if attitude, then Synopsys Inc will provide the right environment for you to prosper.

Work location: Netherlands Sponsorship will be provided. About Us: At Dabster, we specialise in connecting top engineering talent with leading global companies. We are currently seeking an experienced Subsystem/SOC Integration Senior Engineer to join our client's team. Our goal is to deliver world-class recruitment solutions, helping our clients build the future of semiconductor innovation. Who Will You Work With: Our client is a globally recognised leader in semiconductor design and development, with teams based in Sophia Antipolis, France, and Cambridge, UK. You will work alongside industry experts focused on cutting-edge SoC and subsystem integration for next-generation products. About the Role: As a Subsystem/SOC Integration Senior Engineer , you will contribute to IP integration, RTL development, and design reviews as part of complex SoC and subsystem projects. You will support micro-architecture design, manage IP configurations, implement power intent using proprietary flows, and assist with synthesis and verification activities. This is a 6-month B2B contract with strong potential for extension, and the role is fully remote within the EU or UK, with occasional travel required for face-to-face meetings at client sites. Key Responsibilities: Develop and review micro-architecture based on final requirement specifications. Manage and render IP configurations per design requirements. Perform RTL coding and lead design reviews. Integrate IP at subsystem/SoC level in line with micro-architecture specifications. Implement power intent using customer-specific tools and flows. Support trial synthesis, update constraints, and perform LEC (logical equivalency checking). Provide verification and debug support. Preferred Skills: Strong experience in micro-architecture design and RTL coding using SystemVerilog. Proficient with synthesis tools like Design Compiler or Fusion Compiler. Hands-on experience in SDC (Synopsys Design Constraints) development. Ability to debug LEC failures and perform RTL/gate-level debug using tools such as Verdi. Strong analytical and problem-solving skills in IP and SoC design environments.

Sr. Engineer - ASIC Digital Design (Physical Im plementation/D esign/STA, 2+ years of exp) We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performan ce silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled and experienced ASIC Digital Design Engineer passionate about working on the latest processes for STA and physical implementation flows on cutting-edge technology nodes. You thrive in dynamic environments and excel in collaborating with functional teams to optimize and develop IO validation vehicles, Mixed Signal IPs, 3DIO PHYs and UCIe-3D PHY. You have a strong focus on Timing Closure and are adept at defining signoff criteria. Your background includes extensive experience with ASIC design flow, hierarchical physical design strategies, and a deep understanding of sub-micron technology issues. You possess a strong knowledge of timing analysis, constraints management, and various verification strategies, including Primepower-bas ed power analysis. Your scripting skills are excellent, and you are innovative, s elf-motivated, and able to work both independently and as part of a team. Your communication skills, both verbal and written, are outstanding, and you have a desire to understand RTL/Timing signoff criteria. What You’ll Be Doing: Working on new processes for physical implementation flows and cutting-edge technology nodes. Collaborating with functional teams to optimize and develop Qualificaition vehicles and 3D PHYs. Defining signoff criteria with a strong focus on Timing Closure. Maturing the physical implementation guide used for customers and internal hardening teams. Participating in next-generatio n physical design methodology and flow development. Performing physical design i mplementation, including synthesis, floor planning, PG Grid design, PnR, CTS, STA, and power/signal integrity signoff. Evaluating PPA targets (Area/Speed/Po wer) and collaborating with the design team to improve design and constraints. The Impact You Will Have: Ensuring the optimization and successful implementation of cutting-edge technology nodes. Contributing to the development of high-performan ce silicon chips and software content. Enhancing the efficiency and performance of Synopsys’ IPs through rigorous timing closure and signoff criteria. Improving customer satisfaction by maturing physical implementation guides. Supporting the achievement of Synopsys' operational goals through innovative design solutions. What You’ll Need: Extensive experience with ASIC design flow and hierarchical physical design strategies. Strong background in timing analysis, constraints management, and frontend synthesis. Experience with physical-aware synthesis, formality, and various verification strategies. Knowledge of Primepower-bas ed power analysis and clock gating for power reduction. Fair knowledge of FC design planning methodologies, floor planning, and PG Grid creation using Synopsys Tools. Strong physical implementation flow debugging skills and scripting abilities. Who You Are: Innovative, s elf-motivated, and able to work independently or as a team player. Excellent verbal and written communication skills. Strong analytical and problem-solvin g abilities. Passionate about continuous learning and staying updated with the latest technological advancements in ASIC digital design. The Team You’ll Be A Part Of: You will join a highly skilled and collaborative team focused on developing and optimizing physical design flows for cutting-edge technology nodes. The team is dedicated to innovation, continuous improvement, and delivering high-performan ce solutions that meet the evolving needs of our customers. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

The ideal candidate for this role will be an RTL engineer with over 8 years of practical design and verification experience using SystemVerilog UVM and ASIC verification. You should have hands-on experience with Synopsys and/or Cadence simulation tools, as well as proficiency in RTL and possibly Gate level debug. Desirable skills for this position include experience with Synopsys and/or Cadence Synthesis, STA, DFT, Formal Equivalence tools, and familiarity with JIRA. It would be beneficial to have knowledge of scripting languages such as Python or equivalent, understanding of PLLs, and experience with mixed-signal design modelling and debugging. Keywords: UVM, RTL, SystemVerilog, Synthesis, Analog.,

Sr. Engineer - ASIC Digital Design (Physical Implementation/Design/STA, 2+ years of exp) We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled and experienced ASIC Digital Design Engineer passionate about working on the latest processes for STA and physical implementation flows on cutting-edge technology nodes. You thrive in dynamic environments and excel in collaborating with functional teams to optimize and develop IO validation vehicles, Mixed Signal IPs, 3DIO PHYs and UCIe-3D PHY. You have a strong focus on Timing Closure and are adept at defining signoff criteria. Your background includes extensive experience with ASIC design flow, hierarchical physical design strategies, and a deep understanding of sub-micron technology issues. You possess a strong knowledge of timing analysis, constraints management, and various verification strategies, including Primepower-based power analysis. Your scripting skills are excellent, and you are innovative, self-motivated, and able to work both independently and as part of a team. Your communication skills, both verbal and written, are outstanding, and you have a desire to understand RTL/Timing signoff criteria. What You’ll Be Doing: Working on new processes for physical implementation flows and cutting-edge technology nodes. Collaborating with functional teams to optimize and develop Qualificaition vehicles and 3D PHYs. Defining signoff criteria with a strong focus on Timing Closure. Maturing the physical implementation guide used for customers and internal hardening teams. Participating in next-generation physical design methodology and flow development. Performing physical design implementation, including synthesis, floor planning, PG Grid design, PnR, CTS, STA, and power/signal integrity signoff. Evaluating PPA targets (Area/Speed/Power) and collaborating with the design team to improve design and constraints. The Impact You Will Have: Ensuring the optimization and successful implementation of cutting-edge technology nodes. Contributing to the development of high-performance silicon chips and software content. Enhancing the efficiency and performance of Synopsys’ IPs through rigorous timing closure and signoff criteria. Improving customer satisfaction by maturing physical implementation guides. Supporting the achievement of Synopsys' operational goals through innovative design solutions. What You’ll Need: Extensive experience with ASIC design flow and hierarchical physical design strategies. Strong background in timing analysis, constraints management, and frontend synthesis. Experience with physical-aware synthesis, formality, and various verification strategies. Knowledge of Primepower-based power analysis and clock gating for power reduction. Fair knowledge of FC design planning methodologies, floor planning, and PG Grid creation using Synopsys Tools. Strong physical implementation flow debugging skills and scripting abilities. Who You Are: Innovative, self-motivated, and able to work independently or as a team player. Excellent verbal and written communication skills. Strong analytical and problem-solving abilities. Passionate about continuous learning and staying updated with the latest technological advancements in ASIC digital design. The Team You’ll Be A Part Of: You will join a highly skilled and collaborative team focused on developing and optimizing physical design flows for cutting-edge technology nodes. The team is dedicated to innovation, continuous improvement, and delivering high-performance solutions that meet the evolving needs of our customers. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.