Design Verification Manager We need an experienced DV lead/manager to verify IP/SoC using System Verilog/UVM Exposure to various interface IP like I2C/SPI/UART/USB/NVM/PCIe; Buses AXI/AHB/APB; ARM based SoC designs is needed. Skills: Overall 7+ years industry experience with 5+ years in Design Verification using System-Verilog/C/UVM. Generic knowhow on Digital Design and Verification methodologies. Experience in System Verilog/UVM based IP/SoC verification using advanced technologies. Good understanding of Constraint based Random verification; VIP coding; Test Plan design; Test cases coding; Coverage strategies and measurement Proficient in EDA tools used for Design Verification (e.g. Cadence/Mentor/Synopsys simulation suites; Verilator). Working knowledge of Unix, Linux and SKILL, Shell/Python Script ability. Quick learner with excellent interpersonal, verbal/written communications, problem solving and decision-making skills Traits: Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency. Solutions orientation; Quality driven; Execution minded Show more Show less

RTL Design Engineers at Hyderabad We need experienced engineers to work on cutting edge technology and with complex functionality. Skills: Overall 3+ years industry experience with 2+ years in RTL Design and SoC Integration. Proven hands-on experience with RTL design for IP, the subsystem for ASIC. Hands-on experience with SoC integration issues like clocking, reset, memory map, hierarchical bus interconnect Knowledge of IP and SoC design flows and methodologies (Lint, CDC, Synthesis, power). Ability to work with local and remote teams (Architecture, DV, DFT, and Physical Design) Proficient in EDA tools used (e.g. Cadence/Mentor/Synopsys) Working knowledge of Unix, Linux and SKILL, Shell/Python Script ability. Quick learner with excellent interpersonal, verbal/written communications, problem solving and decision-making skills Traits: Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency. Solutions orientation; Quality driven; Execution minded Show more Show less

Analog Layout Design Engineer with 3+ years of relevant work experience You will be doing Analog Layout in advanced process technologies, serving global Semiconductor product MNC clients. What you get: Inducted in the advanced Analog VLSI projects Get an opportunity to work with clients that are world-class VLSI MNCs Skills: Hands-on knowhow in analog and mixed-signal layout techniques and experience with Cadence Layout tools (Virtuoso) and Mentor Graphics verification tools (Calibre) Experience in Custom Analog Layout (one or more) of I/O, Amplifiers/OPAMP circuits, ADCs/DACs, LDOs, Bandgaps & Bias Circuits, Temperature Sensor, Oscillators Physical Verification ( LVS, DRC, ERC, ANT with Calibre) Ability to recognize and correct problematic circuit and layout structures Knowledge of relevant device physics, matching techniques, ESD/Latchup mitigation techniques, circuit parasitic extraction & reduction, VXL compliance etc., is expected Ability to closely and independently work with Analog Designers to solve performance and area challenges Traits: Quick learner with excellent interpersonal, verbal/written communication, problem-solving, and decision-making skills Adaptable, Flexible, Global Approach/Synthesis, Creative Willing to work on customer site for deployment and support Show more Show less

SoC Physical Design Engineers We need experienced engineers to work on the Physical Design & Implementation of SoCs in cutting edge technology and with complex functionality. Skills: 3+ years of relevant experience in Block/SoC level Physical Design. Experience in Block/SoC Physical Design in the following topics: PnR tools like ICC2/Innovus with regards to physical/timing convergence 14nm / 10nm / 7nm / 5nm process nodes Tapeout sign-off experience is a must using industry standard tools. Cadence Encounter/Synopsys ICC2 tool set SDC, STA and Equivalence checking Flow automation exposure will be an added advantage. Working knowledge of Unix, Linux and SKILL, Shell/Python Script ability. Quick learner with excellent interpersonal, verbal/written communications, problem solving and decision-making skills Traits: Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency. Solutions orientation; Quality driven; Execution minded

Design Verification Manager We need an experienced DV lead/manager to verify IP/SoC using System Verilog/UVM Exposure to various interface IP like I2C/SPI/UART/USB/NVM/PCIe; Buses AXI/AHB/APB; ARM based SoC designs is needed. Skills: Overall 7+ years industry experience with 5+ years in Design Verification using System-Verilog/C/UVM. Generic knowhow on Digital Design and Verification methodologies. Experience in System Verilog/UVM based IP/SoC verification using advanced technologies. Good understanding of Constraint based Random verification; VIP coding; Test Plan design; Test cases coding; Coverage strategies and measurement Proficient in EDA tools used for Design Verification (e.g. Cadence/Mentor/Synopsys simulation suites; Verilator). Working knowledge of Unix, Linux and SKILL, Shell/Python Script ability. Quick learner with excellent interpersonal, verbal/written communications, problem solving and decision-making skills Traits: Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency. Solutions orientation; Quality driven; Execution minded

Analog Layout Design Engineer with 3+ years of relevant work experience You will be doing Analog Layout in advanced process technologies, serving global Semiconductor product MNC clients. What you get: Inducted in the advanced Analog VLSI projects Get an opportunity to work with clients that are world-class VLSI MNCs Skills: Hands-on knowhow in analog and mixed-signal layout techniques and experience with Cadence Layout tools (Virtuoso) and Mentor Graphics verification tools (Calibre) Experience in Custom Analog Layout (one or more) of I/O, Amplifiers/OPAMP circuits, ADCs/DACs, LDOs, Bandgaps & Bias Circuits, Temperature Sensor, Oscillators Physical Verification ( LVS, DRC, ERC, ANT with Calibre) Ability to recognize and correct problematic circuit and layout structures Knowledge of relevant device physics, matching techniques, ESD/Latchup mitigation techniques, circuit parasitic extraction & reduction, VXL compliance etc., is expected Ability to closely and independently work with Analog Designers to solve performance and area challenges Traits: Quick learner with excellent interpersonal, verbal/written communication, problem-solving, and decision-making skills Adaptable, Flexible, Global Approach/Synthesis, Creative Willing to work on customer site for deployment and support

RTL Design Engineers at Hyderabad We need experienced engineers to work on cutting edge technology and with complex functionality. Skills: Overall 3+ years industry experience with 2+ years in RTL Design and SoC Integration. Proven hands-on experience with RTL design for IP, the subsystem for ASIC. Hands-on experience with SoC integration issues like clocking, reset, memory map, hierarchical bus interconnect Knowledge of IP and SoC design flows and methodologies (Lint, CDC, Synthesis, power). Ability to work with local and remote teams (Architecture, DV, DFT, and Physical Design) Proficient in EDA tools used (e.g. Cadence/Mentor/Synopsys) Working knowledge of Unix, Linux and SKILL, Shell/Python Script ability. Quick learner with excellent interpersonal, verbal/written communications, problem solving and decision-making skills Traits: Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency. Solutions orientation; Quality driven; Execution minded

As ASIC Physical Design Lead y ou will be leading the design of IP/SoC in advanced process technologies, serving global Semiconductor product MNC clients. Job Summary: We are looking for an ASIC Physical Design Lead with extensive experience in timing closure and full-chip physical design. The candidate should be adept at interacting with the packaging team and managing tasks such as pads log, bump placement, and RDL routing. Key Responsibilities: Lead the physical design of complex ASIC projects from Netlist to GDSII. Perform timing closure tasks including synthesis, place and route, and static timing analysis. Oversee full-chip physical design processes, including floor planning, power grid design, clock tree synthesis, and signal integrity analysis. Collaborate with the packaging team to ensure seamless integration of the chip design with the package, including pads log management , bump placement , and RDL routing . Mentor junior engineers and guide them on physical design methodologies. Drive innovation and efficiency in physical design workflows. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Minimum of 10 years of experience in ASIC physical design. Expertise in industry-standard EDA tools for physical design and verification. Strong understanding of timing closure techniques and challenges. Experience with full-chip design and familiarity with multi-voltage and multi-clock domain designs. Excellent problem-solving and analytical skills. Strong communication and leadership abilities.