Chip Lead (Sr Mgr/Director) Hyderabad A Hyderabad based SoC product design company is looking for a talented, energetic and diligent SoC Director for leading the development of a new generation of devices. Job Description: We are seeking an experienced professional to lead full chip design for multi-million gate SoCs in the area of HBM. Job responsibilities include: Driving the specification of the chip with architect and design leads – eventually cascading into block specifications.Make PPA decisions for the chip.Defining multiple development checkpoints – for IP/SoC Design/DV/PDCome up with overall project plan and cascaded schedule details for other teamsWork with Analog/Digital IP teams to laydown integration details for the IPs.Drive the full chip floorplan / bump maps and provide area/floorplan targets to IP teams.Define the sign-off criteria for the device.Define the SoC verification plan items/scenarios to be covered.Assist/Review the micro architecture definition for digital blocksDefine RTL Quality gate criteria for integration – Lint/CDC/Drive the timing constraints/timing analysis/closure activities.Define the DFT targets for the chip and cascade that into activities needed on the DFT front.Work with PD enginers to get the physical design closure.Handle tapeout formalities Qualifications:Close to 15 years of solid experience in SoC design. A self starter. Candidate ready to define things where none exist. Ready for once in a lifetime project exposure, but ready to do heavy lifting for the effort.Proven ability to develop architecture and micro-architecture from specifications.Understanding of chip I/O design and packaging is advantageous.Experience in reviewing top-level test plans.Expertise in Synopsys Design Compiler for synthesis and formal verification.Strong working knowledge of timing closure processes.Experience with post-silicon bring-up and debugging.Familiarity with SoC integration challenges.Knowledge of design verification aspects is essential.Experience from SoC specification to GDS and commercialization is highly desired.Ability to make timely and effective decisions, even with incomplete information.Demonstrated expertise in specific technical areas, with significant experience in related fields.Provide direction, mentoring, and leadership to small to medium-sized teams.Strong communication and leadership skills are necessary for effective collaboration with program stakeholders. Contact:UdayMulya Technologiesmuday_bhaskar@yahoo.com"Mining The Knowledge Community"

Principal STA / Synthesis Engineer Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ BangaloreA US based well-funded product-based startup looking for Highly talented Engineers for the following roles.Constraint developmentConstraint managementConstraint validationChip top level synthesis, sta and Timing Closure.RTL2GDS flow.Ability to handle synthesis,sta, lec, upf flow methodologies.TCL/perl/python scripting.Candidate with 12+ yrs exp in Synthesis / STA roleExperience in handling complex data path-oriented multi-million gate synthesisWorking Knowledge of Physical synthesis using tools like Genus, Design CompilerExperience in debugging for multi-clock domains hierarchical/flat timing analysis.Hands-on experience in LEC along with strong debugging skills for resolving issues/aborts.Netlist and constraint sign in checks and validation.Prime time constraint development at full chip level and clean up.Multimode multi corner timing knowledge and timing closure at block/top level using tools like DMSAExcellent debugging skills in timing convergence issues and ability to come up with creative solutions .Technical leadership and ability to mentor and make the team deliver. Contact:UdayMulya Technologiesmuday_bhaskar@yahoo.com"Mining The Knowledge Community"

Name of position: Senior Software Developer - Sec Master Location of Position: GurgaonRequired Experience level: 5 - 7 yearsRequired Key Skills: Python / Security masters / Risk Data / Referential Data Notice Period: Immediate / Serving Notice Period / 30 - 60 DaysThis is a complete IC ROLE Please find the JD below: About the jobWe are , a high-frequency proprietary trading firm founded two decades back, seeks an Associate to join our Central Finance Team in Gurgaon. Responsibilities Strengthening and maintaining our security referential infrastructure to address trading and back-office needsTaking end-to-end ownership: development, testing, release and support Being a subject matter expert, functionally and technically, to deliver security referential data needs for our global trading footprintInteracting with trading teams and users to handle issuesThe ideal candidate will have: Brilliant problem-solving abilities Solid background in data structures and algorithmsProgramming expertise in one or more of the following languages - C++, Rust, PythonGood breadth of knowledge in widely used industry technologies, including Python, Bash and databasesClear understanding of computer architecture fundamentalsAbility to manage multiple tasks in a fast-paced environment Understanding of Relational databases is a plusBenefits We continues to enhance the in-house trading system and strategies that have positioned the firm as a leader in the thriving field of quantitative trading. While we offer challenges and rewards rivaling those of any Wall Street firm, Benefits include: Competitive salary and performance-based bonuses5 weeks of paid vacation per yearBreakfast, lunch, dinner, and snacks on a daily basisCab facility within GurgaonHealth club allowances UdayMulya Technologiesmuday_bhaskar@yahoo.com"Mining The Knowledge Community"

Senior SoC Director / SoC DirectorHyderabadFounded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/Bangalore A US based well-funded product-based startup looking for highly talented SoC Director for the following roles Senior Director / SoC Director of SOC is : Trust, loyalty, and ability to command Technical respect with foreign partners after having Taped out Successfully multiple chips to high volume production….this should be easily achieved under his/her belt !!!!!!!!Somebody we can trust to drive on the World stage without embarrassing us Job Description:We are seeking an experienced professional to lead full chip design for multi-million gate SoCs. The ideal candidate will have expertise in digital design and RTL development, with a deep understanding of the design convergence cycle, including architecture, micro-architecture, synthesis, timing closure, and verification.Key Responsibilities:Proficiency inInterconnect FabricCache CoherencyD2DC2COversee full chip design for complex SoCs.Develop and implement digital designs (RTL).Manage IP dependencies and track all front-end design tasks.Drive project milestones across design, verification, and physical implementation phases.Qualifications:At least 15-25 years of solid experience in SoC design.Proven ability to develop architecture and micro-architecture from specifications.Familiarity with bus protocols such as AHB and AXI, as well as peripherals like QSPI, NVMe, and I3C.Knowledge of memory controller designs and microprocessors is a plus.Understanding of chip I/O design and packaging is advantageous.Experience in reviewing top-level test plans.Expertise in Synopsys Design Compiler for synthesis and formal verification.Strong working knowledge of timing closure processes.Experience with post-silicon bring-up and debugging.Familiarity with SoC integration challenges.Knowledge of design verification aspects is essential.Experience from SoC specification to GDS and commercialization is highly desired.Ability to make timely and effective decisions, even with incomplete information.Demonstrated expertise in specific technical areas, with significant experience in related fields.Provide direction, mentoring, and leadership to small to medium-sized teams.Strong communication and leadership skills are necessary for effective collaboration with program stakeholders. Contact:UdayMulya Technologiesmuday_bhaskar@yahoo.com"Mining The Knowledge Community"

Senior Software Technical Director / Software Technical DirectorWe are looking for a Software Technical Director with a strong technical foundation in systems software, Linux platforms, or machine learning compiler stacks to lead and grow a high-impact engineering team in Bangalore. You will be responsible for shaping the architecture, contributing to codebases, and managing execution across projects that sit at the intersection of systems programming, AI runtimes, and performance-critical software. Key Responsibilities: Technical Leadership:Lead the design and development of Linux platform software, firmware, or ML compilers and runtimes.Drive architecture decisions across compiler, runtime, or low-level platform components.Write production-grade C++ code and perform detailed code reviews.Guide performance analysis and debugging across the full stack—from firmware and drivers to user-level runtime libraries.Collaborate with architects, silicon teams, and ML researchers to build future-proof software stacks. Team & Project Management:Mentor and coach junior and senior engineers to grow technical depth and autonomy.Own end-to-end project planning, execution, and delivery, ensuring high-quality output across sprints/releases.Facilitate strong cross-functional communication with hardware, product, and other software teams globally.Recruit and grow a top-tier engineering team in Bangalore, contributing to the hiring strategy and team culture. Required Qualifications:Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or related field.18+ years of experience in systems software development with significant time spent in C++, including architectural and hands-on roles.Proven experience in either:Linux kernel, bootloaders, firmware, or low-level platform software, orMachine Learning compilers (e.g., MLIR, TVM, Glow) or runtimes (e.g., ONNX Runtime, TensorRT, vLLM).Excellent communication skills—written and verbal.Prior experience in project leadership or engineering management with direct reports. Highly Desirable:Understanding of AI/ML compute workloads, particularly Large Language Models (LLMs).Familiarity with performance profiling, bottleneck analysis, and compiler-level optimizations.Exposure to AI accelerators, systolic arrays, or vector SIMD programming. Why Join Us?Work at the forefront of AI systems software, shaping the future of ML compilers and runtimes.Collaborate with globally distributed teams in a fast-paced, innovation-driven environment.Build and lead a technically elite team from the ground up in a growth-stage organization. Contact:UdayMulya Technologiesmuday_bhaskar@yahoo.com"Mining The Knowledge Community"

Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore A US based well-funded product-based startup looking for Highly talented Senior Physical Fri, Mar 28 at 9:39 AM Principal / Staff IP/RTL Design Engineer (AI Accelerator) – Multiple positions - Hyderabad Well-funded product startup is looking for RTL Design Engineers to contribute to the development of novel high performance AI accelerators from scratch. In this role you will collaborate with cross-functional teams, including architect, software, verification, physical design, systems engineers, to define and implement next generation AI architectures. We are seeking highly experienced individuals who have a passion for innovation and are excited about the opportunity to create world class products from India. The key responsibilities for this role include, but are not limited to: Key Responsibilities Design and implement high-performance TPUs/MPUs and other related AI blocks using RTL. Own IP/block-level RTL from spec to GDS, including design, synthesis, and timing closure. Optimize design for power, performance, and area (PPA). Interface with physical design and DFT (Design for Test) engineers for seamless integration. Drive design reviews, write design documentation, and support post silicon bring-up/debug. Minimum Qualifications B.S./M.S./Ph.D. in ECE/CS from top engineering college with 5-15 years of related experience. Previous experience in either high performance processor design or AI accelerator design is plus. Clear understanding of floating-point arithmetic, vector processing, SIMD, MIMD, VLIW, EPIC concepts. Strong grasp of digital design fundamentals, computer architecture, virtual memory and high-speed data-path design. Proficiency in Verilog/SystemVerilog and simulation tools. Experience with EDA tools (e.g., Synopsys, Cadence) for synthesis, lint, CDC, and timing analysis. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

Senior Software Technical Director / Software Technical Director We are looking for a Software Technical Director with a strong technical foundation in systems software, Linux platforms, or machine learning compiler stacks to lead and grow a high-impact engineering team in Bangalore. You will be responsible for shaping the architecture, contributing to codebases, and managing execution across projects that sit at the intersection of systems programming, AI runtimes, and performance-critical software. Key Responsibilities: Technical Leadership: Lead the design and development of Linux platform software, firmware, or ML compilers and runtimes. Drive architecture decisions across compiler, runtime, or low-level platform components. Write production-grade C++ code and perform detailed code reviews. Guide performance analysis and debugging across the full stack—from firmware and drivers to user-level runtime libraries. Collaborate with architects, silicon teams, and ML researchers to build future-proof software stacks. Team & Project Management: Mentor and coach junior and senior engineers to grow technical depth and autonomy. Own end-to-end project planning, execution, and delivery, ensuring high-quality output across sprints/releases. Facilitate strong cross-functional communication with hardware, product, and other software teams globally. Recruit and grow a top-tier engineering team in Bangalore, contributing to the hiring strategy and team culture. Required Qualifications: Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or related field. 18+ years of experience in systems software development with significant time spent in C++, including architectural and hands-on roles. Proven experience in either: Linux kernel, bootloaders, firmware, or low-level platform software, or Machine Learning compilers (e.g., MLIR, TVM, Glow) or runtimes (e.g., ONNX Runtime, TensorRT, vLLM). Excellent communication skills—written and verbal. Prior experience in project leadership or engineering management with direct reports. Highly Desirable: Understanding of AI/ML compute workloads, particularly Large Language Models (LLMs). Familiarity with performance profiling, bottleneck analysis, and compiler-level optimizations. Exposure to AI accelerators, systolic arrays, or vector SIMD programming. Why Join Us? Work at the forefront of AI systems software, shaping the future of ML compilers and runtimes. Collaborate with globally distributed teams in a fast-paced, innovation-driven environment. Build and lead a technically elite team from the ground up in a growth-stage organization. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

Senior SoC Director / SoC Director Bangalore / Delhi / Pune / Chennai with some travel to Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/Bangalore A US based well-funded product-based startup looking for highly talented SoC Director for the following roles Senior Director / SoC Director of SOC is : Trust, loyalty, and ability to command Technical respect with foreign partners after having Taped out Successfully multiple chips to high volume production….this should be easily achieved under his/her belt !!!!!!!! Somebody we can trust to drive on the World stage without embarrassing us Job Description: We are seeking an experienced professional to lead full chip design for multi-million gate SoCs. The ideal candidate will have expertise in digital design and RTL development, with a deep understanding of the design convergence cycle, including architecture, micro-architecture, synthesis, timing closure, and verification. Key Responsibilities: Proficiency in Interconnect Fabric Cache Coherency D2D C2C Oversee full chip design for complex SoCs. Develop and implement digital designs (RTL). Manage IP dependencies and track all front-end design tasks. Drive project milestones across design, verification, and physical implementation phases. Qualifications: At least 15-25 years of solid experience in SoC design. Proven ability to develop architecture and micro-architecture from specifications. Familiarity with bus protocols such as AHB and AXI, as well as peripherals like QSPI, NVMe, and I3C. Knowledge of memory controller designs and microprocessors is a plus. Understanding of chip I/O design and packaging is advantageous. Experience in reviewing top-level test plans. Expertise in Synopsys Design Compiler for synthesis and formal verification. Strong working knowledge of timing closure processes. Experience with post-silicon bring-up and debugging. Familiarity with SoC integration challenges. Knowledge of design verification aspects is essential. Experience from SoC specification to GDS and commercialization is highly desired. Ability to make timely and effective decisions, even with incomplete information. Demonstrated expertise in specific technical areas, with significant experience in related fields. Provide direction, mentoring, and leadership to small to medium-sized teams. Strong communication and leadership skills are necessary for effective collaboration with program stakeholders. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

Staff PCIe / CXL / D2D based memory expander Verification Location: Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/Bangalore A US based well-funded product-based startup looking for Highly talented Verification Engineers for the following roles. PCIe/CXL based memory expander - Verification Engineer: looking for experienced and talented professional for CXL based memory expander. Minimum Qualifications: BE/BTech in Electrical/Computer engineering with 6-8+ years of experience or Should have hands on experience in System Verilog, UVM and Object-Oriented Programming Proven track record in USB / PCIe / CXL / D2D IP verification both on FPGA and ASIC, with ability to bring up testbenches from scratch to defining test plan and sign-off for tape out. Integration and verification of complex System IP features. Work closely with RTL designers and SOC team to scope out integration and verification requirements. Good understanding of any memory protocol like DDR, ONFI, NAND, Flash SPI/QSPI. Proficiency in bus protocols AXI/AHB Proficiency in scripting languages like Perl, Python etc. Strong communication, collaboration, and interpersonal skills Strong analytical and problem-solving skills Preferred Qualifications: Experience in verification of PCIe/CXL based sub-system/SoC/IP. Knowledge of SoC with processor boot-flow. Knowledge of FPGA setup and running FPGA simulations. Experience in GLS is added advantage. Verification expertise in Physical Layer, Link Layer, and Transaction Layer of PCIe/CXL protocols. Experience with compliance at the physical and transaction layers for PCIe/CXL endpoints or root ports. Analysing performance metrics of CXL / PCIe / D2D System-level verification experience for PCIe / CXL / D2D Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

Senior SoC Director / SoC Director Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/Bangalore A US based well-funded product-based startup looking for highly talented SoC Director for the following roles Senior Director / SoC Director of SOC is : Trust, loyalty, and ability to command Technical respect with foreign partners after having Taped out Successfully multiple chips to high volume production….this should be easily achieved under his/her belt !!!!!!!! Somebody we can trust to drive on the World stage without embarrassing us Job Description: We are seeking an experienced professional to lead full chip design for multi-million gate SoCs. The ideal candidate will have expertise in digital design and RTL development, with a deep understanding of the design convergence cycle, including architecture, micro-architecture, synthesis, timing closure, and verification. Key Responsibilities: Proficiency in AI Accelerators DNN Accelerators co-processors Interconnect Fabric Cache Coherency D2D C2C SoC Director Bangalore We are a AI semiconductor startup company headquartered in Ann Arbor, Michigan, with branches in , Taiwan and Bangalore, India. We develop highly scalable and innovative AI accelerator chips that offer high performance, low energy, and customer ease of implementation for embedded Edge AI vision-based applications and real-time data processing. Company has working HW & SW for customer sampling, with production designs in the pipeline, and a system architecture designed a future of neuromorphic computing. We are backed by excellent VC funding and is currently in a stage of rapid growth. While our tech is one of a kind we would not be able to make these advancements without our team. Our collaborative culture is one of the keys to our success. Who You Are You are an open and honest communicator who values your team You are innovative, enjoy bringing new ideas to the table and are receptive to ideas and feedback from others You’re passionate about advancing the state of the world through new technology You enjoy the ambiguity and pace of a startup environment The role This leadership role will be responsible for the global VLSI efforts at and India Site Management. It is a highly visible role reporting to Senior Director with ownership of all pre/post Si activities, leading interface with external EDA, IP, Design Service partners, managing the India site operations and a global VLSI team. What you will be doing: Ownership of pre-Si Design of the next-gen AI accelerator at driving deliverables with Design and IP Service providers, CAD tools, IPs, DFT/PD/Packaging and Test. Work closely with internal Architecture, SW, Emulation, and system board designers on product definition, microarchitecture, and design implementation. Build and manage the VLSI team of front-end design and verification engineers across India and Taiwan. Establish best practices for development, testing, reviews, and documentation. Participate in strategic discussions for product features and roadmap. What we expect to see: BS/MS in Electrical/Electronic Engineering with 18+ years of experience in VLSI, SOC design, several Si tape-out/production. Hands-on experience in front-end design, VLSI flows, and working experience for all aspects of Si tape-out, post-Si validation. Self-driven, organized with strong leadership and communication skills. Experience in building and managing teams with the ability to motivate and lead in a startup environment. Proven track record in several successful productizations. What we would be happy to see: Knowledge of AI, specifically Deep Neural Networks Application-specific accelerators or co-processors Startup experience Site Leadership experience Reports to: Site Lead Work location: Bangalore, India Hours: Full time Employment Opportunity and Benefits of Employment: We are committed to creating and fostering a diverse and inclusive workplace environment for all of our employees. We are an equal opportunity employer. Contact: Uday Mulya Technologies Email: muday_bhaskar@yahoo.com Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

Senior SoC Director / SoC Director Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/Bangalore A US based well-funded product-based startup looking for highly talented SoC Director for the following roles Senior Director / SoC Director of SOC is : Trust, loyalty, and ability to command Technical respect with foreign partners after having Taped out Successfully multiple chips to high volume production….this should be easily achieved under his/her belt !!!!!!!! Somebody we can trust to drive on the World stage without embarrassing us Job Description: We are seeking an experienced professional to lead full chip design for multi-million gate SoCs. The ideal candidate will have expertise in digital design and RTL development, with a deep understanding of the design convergence cycle, including architecture, micro-architecture, synthesis, timing closure, and verification. Key Responsibilities: Proficiency in Interconnect Fabric Cache Coherency D2D C2C Oversee full chip design for complex SoCs. Develop and implement digital designs (RTL). Manage IP dependencies and track all front-end design tasks. Drive project milestones across design, verification, and physical implementation phases. Qualifications: At least 15-25 years of solid experience in SoC design. Proven ability to develop architecture and micro-architecture from specifications. Familiarity with bus protocols such as AHB and AXI, as well as peripherals like QSPI, NVMe, and I3C. Knowledge of memory controller designs and microprocessors is a plus. Understanding of chip I/O design and packaging is advantageous. Experience in reviewing top-level test plans. Expertise in Synopsys Design Compiler for synthesis and formal verification. Strong working knowledge of timing closure processes. Experience with post-silicon bring-up and debugging. Familiarity with SoC integration challenges. Knowledge of design verification aspects is essential. Experience from SoC specification to GDS and commercialization is highly desired. Ability to make timely and effective decisions, even with incomplete information. Demonstrated expertise in specific technical areas, with significant experience in related fields. Provide direction, mentoring, and leadership to small to medium-sized teams. Strong communication and leadership skills are necessary for effective collaboration with program stakeholders. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

Chip Lead (Sr Mgr/Director) Hyderabad A Hyderabad based SoC product design company is looking for a talented, energetic and diligent SoC Director for leading the development of a new generation of devices. Job Description: We are seeking an experienced professional to lead full chip design for multi-million gate SoCs in the area of HBM. Job responsibilities include: Driving the specification of the chip with architect and design leads – eventually cascading into block specifications. Make PPA decisions for the chip. Defining multiple development checkpoints – for IP/SoC Design/DV/PD Come up with overall project plan and cascaded schedule details for other teams Work with Analog/Digital IP teams to laydown integration details for the IPs. Drive the full chip floorplan / bump maps and provide area/floorplan targets to IP teams. Define the sign-off criteria for the device. Define the SoC verification plan items/scenarios to be covered. Assist/Review the micro architecture definition for digital blocks Define RTL Quality gate criteria for integration – Lint/CDC/ Drive the timing constraints/timing analysis/closure activities. Define the DFT targets for the chip and cascade that into activities needed on the DFT front. Work with PD enginers to get the physical design closure. Handle tapeout formalities Qualifications: Close to 15 years of solid experience in SoC design. A self starter. Candidate ready to define things where none exist. Ready for once in a lifetime project exposure, but ready to do heavy lifting for the effort. Proven ability to develop architecture and micro-architecture from specifications. Understanding of chip I/O design and packaging is advantageous. Experience in reviewing top-level test plans. Expertise in Synopsys Design Compiler for synthesis and formal verification. Strong working knowledge of timing closure processes. Experience with post-silicon bring-up and debugging. Familiarity with SoC integration challenges. Knowledge of design verification aspects is essential. Experience from SoC specification to GDS and commercialization is highly desired. Ability to make timely and effective decisions, even with incomplete information. Demonstrated expertise in specific technical areas, with significant experience in related fields. Provide direction, mentoring, and leadership to small to medium-sized teams. Strong communication and leadership skills are necessary for effective collaboration with program stakeholders. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

www.Sevyamultimedia.com Verification Design Manager / Senior Manager About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills Our embedded design services are centered around FW validation & Test Automation Chip Design Services Analog IP Design Foundation - OpAmp, Bandgap IOs - GPIO, I2C, LVDS Clocking - PLL Power - LDO SoC Design RTL Design, Integration, Lint/CDC/RDC, UPF IP/SoC UVM Verification PPA, Synthesis, Constraints Management Physical Design, Timing Closure, ECOs Sign-off - Timing, Power, EM/IR, DRC/LVS/ERC PDK, Design Automation DRC/LVS/Extraction Rule deck Development PCell Development Automation Tools in Perl, Python, GoLang Approach We support a mix of engagement models to support diverse client requirements. Engagement Models Turnkey (SoW) Engagement Staff Augmentation (T&M) Offshore Design Center Key Enablers Hands on Leadership Proven Industry Experts TSMC DCA Parternship Collaboration with Academia ================ Design Verification Manager / Lead ### Job Description: Design Verification Manager / Lead DV lead/manager to verify IP/SoC using System Verilog / UVM --------------------------------------------------------------------------------------- Exposure to various interface IP like I2C/SPI/UART/USB/NVM/PCIe; Buses AXI/AHB/APB; ARM based SoC designs is needed. Skills: Overall 10+ years industry experience with 5+ years in Design Verification using System-Verilog/C/UVM. Generic knowhow on Digital Design and Verification methodologies. Experience in System Verilog/UVM based IP/SoC verification using advanced technologies. Good understanding of Constraint based Random verification; VIP coding; Test Plan design; Test cases coding; Coverage strategies and measurement Proficient in EDA tools used for Design Verification (e.g. Cadence/Mentor/Synopsys simulation suites; Verilator). Working knowledge of Unix, Linux and SKILL, Shell/Python Script ability. Quick learner with excellent interpersonal, verbal/written communications, problem solving and decision-making skills Traits: Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency. Solutions orientation; Quality driven; Execution minded Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

www.Sevyamultimedia.com Physical Design Manager / Senior Manager About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills SoC Design RTL Design, Integration, Lint/CDC/RDC, UPF IP/SoC UVM Verification PPA, Synthesis, Constraints Management Physical Design, Timing Closure, ECOs Sign-off - Timing, Power, EM/IR, DRC/LVS/ERC Approach We support a mix of engagement models to support diverse client requirements. Engagement Models Turnkey (SoW) Engagement Staff Augmentation (T&M) Offshore Design Center Key Enablers Hands on Leadership Proven Industry Experts TSMC DCA Parternship Collaboration with Academia ================ Physical Design Manager / Senior Manager #### **Job Summary:** We are seeking a highly experienced, hands-on and motivated Physical Design Manager/ Director to lead our physical design team. The ideal candidate will have extensive experience in block and top-level implementation, RDL/bump, pad location, EM/IR analysis, timing closure, physical verification closure, CAD flow bring-up, automation, planning, and estimation. This role involves managing complex design projects, leading a team of engineers, and ensuring the successful execution of physical design tasks from planning to tape-out. #### **Key Responsibilities:** - **Team Leadership:** - Lead, mentor, and manage a team of physical design engineers. - Foster a collaborative and innovative team environment. - Develop team skills through training and professional development initiatives. - **Project Management:** - Plan and estimate physical design tasks, resources, and schedules. - Track and report on project progress, ensuring timely delivery of milestones. - Coordinate with cross-functional teams, including design, verification, and packaging, to align physical design activities with project goals. - **Block and Top-Level Implementation:** - Perform and oversee block-level and top-level physical design implementation. - Ensure designs meet performance, power, area, and manufacturability requirements. - Perform detailed floorplanning, placement, and routing. - Constraints clean up, robustness of implementation - Timing feedback to design team and sign-off timing. - **RDL/Bump and Pad Location:** - Manage redistribution layer (RDL) and bump design for advanced packaging. - Optimize pad location for signal integrity and manufacturability. - **EM/IR Analysis and Timing Closure:** - Conduct electromigration (EM) and IR drop analysis to ensure robust power delivery. - Achieve timing closure through detailed static timing analysis (STA) and optimization. - **Physical Verification Closure:** - Perform physical verification (PV) closure, including design rule checking (DRC) and layout versus schematic (LVS). - Ensure designs comply with foundry and industry standards. - **CAD Flow and Automation:** - Develop and bring up CAD flows for physical design tasks. - Implement automation scripts to enhance efficiency and productivity. - **Continuous Improvement:** - Stay updated with the latest industry trends, tools, and methodologies in physical design. - Drive continuous improvement initiatives to enhance design processes and methodologies. - Implement best practices for physical design and contribute to the development of standards and processes. #### **Qualifications:** - **Education:** - Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. - **Experience:** - 10-15+ years of experience in physical design, with at least 3 years in a managerial or leadership role. - **Technical Skills:** - Extensive experience in block and top-level physical design implementation. - Proficiency in RDL/bump design and pad location optimization. - Strong knowledge of EM/IR analysis and timing closure techniques. - Experience with physical verification closure (DRC, LVS). - Familiarity with CAD flow development and automation. - **Soft Skills:** - Excellent leadership and team management abilities. - Strong problem-solving and analytical skills. - Effective communication and interpersonal skills. - Ability to work in a fast-paced, dynamic environment and manage multiple projects simultaneously. #### **Preferred Qualifications:** - Experience with advanced node technologies (e.g., FinFET, SOI). - Knowledge of scripting languages (e.g., Python, Perl) for automation. - Experience with EDA tools such as Cadence, Synopsys, or Mentor Graphics. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

Principal Physical Design Engineer Greater Bangalore -Hybrid/Hyderabad (Hybrid ) PrincipalPhysical Design Engineer Company Background We are a well-funded, stealth-mode startup based in Mountain View, CA, founded by senior technical and business executives hailing from category leaders in infrastructure semiconductors and hyperscale cloud services, and backed by top-tier investors with an immensely successful formula & track record on early-stage investments. We are a diverse team of expert chip/software/systems architects and developers who excel in hardware/software solution co-design. Our team has built, and delivered into production, technologies that process over half of the world's global data center traffic. Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, from CAD tool flow setup, early floorplan exploration in conjunction with microarchitecture development, through block partitioning, power planning, clock network design and construction, through P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout. Roles and Responsibilities Build and support the CAD tool flow for physical implementation in a cloud-first development environment. Work with architects and microarchitects on the chip-level floorplan and block partitioning. Evaluate tradeoffs in functional partitioning, block size, and interface complexity with other stakeholders. Define and construct the major physical structures, including the clock and reset architecture, the power delivery network, and interconnect topologies. Execute on block-level, cluster-level, and top-level physical implementation, from synthesis, floorplan and power plan, through P+R, through timing closure, physical verification, and tapeout. Interface with foundry and library partners on 3rd party IP and process technology issues, including updates to device models, IP integration requirements, and pre-tapeout signoff. Skills/Qualifications : Proven industry experience and successful track record in the physical implementation of large, high-performance network switching/routing fabrics (Ethernet, Infiniband, HPC), Network Interface Controllers, Smart-NICs, CPUs, or GPUs in the latest silicon process nodes. Deep experience with the latest CAD tools through the entire physical design workflow, e.g., Cadence Genus and Innovus, Synopsys ICC2/FusionCompiler, Tempus, PrimeTime SI, PrimeTime PX, StarRC, ICV, Calibre. Strong familiarity with various analysis tools such as Redhawk, Voltus. Experience with circuit analysis using HSPICE is a plus. Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages. Minimum BSEE/CE + 12 years or MSEE/CE + 10 years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

Principal Physical Design Engineer Greater Bangalore -Hybrid/Hyderabad (Hybrid ) PrincipalPhysical Design Engineer Company Background We are a well-funded, stealth-mode startup based in Mountain View, CA, founded by senior technical and business executives hailing from category leaders in infrastructure semiconductors and hyperscale cloud services, and backed by top-tier investors with an immensely successful formula & track record on early-stage investments. We are a diverse team of expert chip/software/systems architects and developers who excel in hardware/software solution co-design. Our team has built, and delivered into production, technologies that process over half of the world's global data center traffic. Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, from CAD tool flow setup, early floorplan exploration in conjunction with microarchitecture development, through block partitioning, power planning, clock network design and construction, through P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout. Roles and Responsibilities Build and support the CAD tool flow for physical implementation in a cloud-first development environment. Work with architects and microarchitects on the chip-level floorplan and block partitioning. Evaluate tradeoffs in functional partitioning, block size, and interface complexity with other stakeholders. Define and construct the major physical structures, including the clock and reset architecture, the power delivery network, and interconnect topologies. Execute on block-level, cluster-level, and top-level physical implementation, from synthesis, floorplan and power plan, through P+R, through timing closure, physical verification, and tapeout. Interface with foundry and library partners on 3rd party IP and process technology issues, including updates to device models, IP integration requirements, and pre-tapeout signoff. Skills/Qualifications : Proven industry experience and successful track record in the physical implementation of large, high-performance network switching/routing fabrics (Ethernet, Infiniband, HPC), Network Interface Controllers, Smart-NICs, CPUs, or GPUs in the latest silicon process nodes. Deep experience with the latest CAD tools through the entire physical design workflow, e.g., Cadence Genus and Innovus, Synopsys ICC2/FusionCompiler, Tempus, PrimeTime SI, PrimeTime PX, StarRC, ICV, Calibre. Strong familiarity with various analysis tools such as Redhawk, Voltus. Experience with circuit analysis using HSPICE is a plus. Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages. Minimum BSEE/CE + 12years or MSEE/CE + 10 years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

DFT Lead / Manager Location: Bangalore Description Our main business focuses on automotive microcontrollers and SoCs. The solutions cover a wide range, such as Edge-ECU to ADAS applications, dedicated to creating a comprehensive solution for automotive chips. we will continue to integrate the latest electronic and electrical architecture (E/EA) designs from automakers, realize the demands of the next-generation software-defined vehicle, and apply a chip design-oriented, human-centric service-oriented architecture (SOA) to the automotive field. This approach aims to meet the diverse neaeds of users and provide consumers with a new user experience. Job Location: Bangalore We are seeking a skilled Design for Test (DFT) Architect/Lead/Manager to join our team. This role is pivotal in ensuring the testability and manufacturability of our ASIC/SoC products designed for the automotive industry. The ideal candidate will have extensive experience in DFT methodologies and will lead a team of engineers to develop robust test strategies that meet industry standards. Key Responsibilities: DFT Strategy Development: Design and implement DFT methodologies for ASIC/SoC products, focusing on automotive applications to ensure high quality and reliability. Architecture Design: Collaborate with hardware and software teams to integrate DFT features into the product architecture, ensuring compatibility with automotive testing standards. Team Leadership: Lead a team of DFT engineers, providing mentorship and technical guidance to enhance their skills and capabilities. Test Planning: Develop comprehensive test plans, including ATPG, BIST, and scan insertion strategies, to optimize fault coverage and reduce test costs. Collaboration: Work closely with design, validation, and manufacturing teams to align DFT strategies with overall product goals and requirements. Quality Assurance: Establish metrics and benchmarks for DFT processes, and ensure compliance with automotive industry standards (e.g., ISO 26262). Tool Development: Evaluate and implement DFT tools and methodologies to improve test efficiency and effectiveness. Continuous Improvement: Stay updated with industry trends and technologies in DFT and automotive testing, driving innovation within the team. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 10+ years of experience in DFT for ASIC/SoC design, with a strong background in automotive applications. Proven experience leading DFT teams and managing complex projects. In-depth knowledge of DFT techniques such as scan design, boundary scan, BIST, and fault simulation. Familiarity with automotive industry standards and regulations (e.g., ISO 26262). Proficiency in using DFT tools and EDA software. Strong problem-solving skills and ability to work collaboratively in a fast-paced environment. Excellent communication skills, both verbal and written. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

Principal Physical Design Engineer Greater Bangalore -Hybrid/Hyderabad (Hybrid ) PrincipalPhysical Design Engineer Company Background We are a well-funded, stealth-mode startup based in Mountain View, CA, founded by senior technical and business executives hailing from category leaders in infrastructure semiconductors and hyperscale cloud services, and backed by top-tier investors with an immensely successful formula & track record on early-stage investments. We are a diverse team of expert chip/software/systems architects and developers who excel in hardware/software solution co-design. Our team has built, and delivered into production, technologies that process over half of the world's global data center traffic. Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, from CAD tool flow setup, early floorplan exploration in conjunction with microarchitecture development, through block partitioning, power planning, clock network design and construction, through P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout. Roles and Responsibilities Build and support the CAD tool flow for physical implementation in a cloud-first development environment. Work with architects and microarchitects on the chip-level floorplan and block partitioning. Evaluate tradeoffs in functional partitioning, block size, and interface complexity with other stakeholders. Define and construct the major physical structures, including the clock and reset architecture, the power delivery network, and interconnect topologies. Execute on block-level, cluster-level, and top-level physical implementation, from synthesis, floorplan and power plan, through P+R, through timing closure, physical verification, and tapeout. Interface with foundry and library partners on 3rd party IP and process technology issues, including updates to device models, IP integration requirements, and pre-tapeout signoff. Skills/Qualifications : Proven industry experience and successful track record in the physical implementation of large, high-performance network switching/routing fabrics (Ethernet, Infiniband, HPC), Network Interface Controllers, Smart-NICs, CPUs, or GPUs in the latest silicon process nodes. Deep experience with the latest CAD tools through the entire physical design workflow, e.g., Cadence Genus and Innovus, Synopsys ICC2/FusionCompiler, Tempus, PrimeTime SI, PrimeTime PX, StarRC, ICV, Calibre. Strong familiarity with various analysis tools such as Redhawk, Voltus. Experience with circuit analysis using HSPICE is a plus. Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages. Minimum BSEE/CE + 12years or MSEE/CE + 10 years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

DFT Lead / Manager Location: Bangalore Description Our main business focuses on automotive microcontrollers and SoCs. The solutions cover a wide range, such as Edge-ECU to ADAS applications, dedicated to creating a comprehensive solution for automotive chips. we will continue to integrate the latest electronic and electrical architecture (E/EA) designs from automakers, realize the demands of the next-generation software-defined vehicle, and apply a chip design-oriented, human-centric service-oriented architecture (SOA) to the automotive field. This approach aims to meet the diverse neaeds of users and provide consumers with a new user experience. Job Location: Bangalore We are seeking a skilled Design for Test (DFT) Architect/Lead/Manager to join our team. This role is pivotal in ensuring the testability and manufacturability of our ASIC/SoC products designed for the automotive industry. The ideal candidate will have extensive experience in DFT methodologies and will lead a team of engineers to develop robust test strategies that meet industry standards. Key Responsibilities: DFT Strategy Development: Design and implement DFT methodologies for ASIC/SoC products, focusing on automotive applications to ensure high quality and reliability. Architecture Design: Collaborate with hardware and software teams to integrate DFT features into the product architecture, ensuring compatibility with automotive testing standards. Team Leadership: Lead a team of DFT engineers, providing mentorship and technical guidance to enhance their skills and capabilities. Test Planning: Develop comprehensive test plans, including ATPG, BIST, and scan insertion strategies, to optimize fault coverage and reduce test costs. Collaboration: Work closely with design, validation, and manufacturing teams to align DFT strategies with overall product goals and requirements. Quality Assurance: Establish metrics and benchmarks for DFT processes, and ensure compliance with automotive industry standards (e.g., ISO 26262). Tool Development: Evaluate and implement DFT tools and methodologies to improve test efficiency and effectiveness. Continuous Improvement: Stay updated with industry trends and technologies in DFT and automotive testing, driving innovation within the team. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 10+ years of experience in DFT for ASIC/SoC design, with a strong background in automotive applications. Proven experience leading DFT teams and managing complex projects. In-depth knowledge of DFT techniques such as scan design, boundary scan, BIST, and fault simulation. Familiarity with automotive industry standards and regulations (e.g., ISO 26262). Proficiency in using DFT tools and EDA software. Strong problem-solving skills and ability to work collaboratively in a fast-paced environment. Excellent communication skills, both verbal and written. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

Principal Physical Design Engineer Greater Bangalore -Hybrid/Hyderabad (Hybrid ) PrincipalPhysical Design Engineer Company Background We are a well-funded, stealth-mode startup based in Mountain View, CA, founded by senior technical and business executives hailing from category leaders in infrastructure semiconductors and hyperscale cloud services, and backed by top-tier investors with an immensely successful formula & track record on early-stage investments. We are a diverse team of expert chip/software/systems architects and developers who excel in hardware/software solution co-design. Our team has built, and delivered into production, technologies that process over half of the world's global data center traffic. Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, from CAD tool flow setup, early floorplan exploration in conjunction with microarchitecture development, through block partitioning, power planning, clock network design and construction, through P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout. Roles and Responsibilities Build and support the CAD tool flow for physical implementation in a cloud-first development environment. Work with architects and microarchitects on the chip-level floorplan and block partitioning. Evaluate tradeoffs in functional partitioning, block size, and interface complexity with other stakeholders. Define and construct the major physical structures, including the clock and reset architecture, the power delivery network, and interconnect topologies. Execute on block-level, cluster-level, and top-level physical implementation, from synthesis, floorplan and power plan, through P+R, through timing closure, physical verification, and tapeout. Interface with foundry and library partners on 3rd party IP and process technology issues, including updates to device models, IP integration requirements, and pre-tapeout signoff. Skills/Qualifications : Proven industry experience and successful track record in the physical implementation of large, high-performance network switching/routing fabrics (Ethernet, Infiniband, HPC), Network Interface Controllers, Smart-NICs, CPUs, or GPUs in the latest silicon process nodes. Deep experience with the latest CAD tools through the entire physical design workflow, e.g., Cadence Genus and Innovus, Synopsys ICC2/FusionCompiler, Tempus, PrimeTime SI, PrimeTime PX, StarRC, ICV, Calibre. Strong familiarity with various analysis tools such as Redhawk, Voltus. Experience with circuit analysis using HSPICE is a plus. Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages. Minimum BSEE/CE + 12 years or MSEE/CE + 10 years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less