601 Synopsys Jobs - Page 5

Job Requirements The responsibilities will include several of the following, but not be limited to: Performing floor-planning and routing studies and implementation at block and full-chip level Push down the top-level floorplan and clock to Partition. IO Planning and bump planning Closely working with Package team and reaching Die file milestones Full chip and partition level timing analysis. Evaluate low power techniques and power reduction opportunities Perform clock distribution design and analysis Perform Physical verification activities at full-chip level. Drive technical activities of physical design during technology readiness, design & execution In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience in Physical Design Methodologies and sub-micron technology of 16nm and lower technology nodes Work Experience Experience Range:- 4Yrs - 10 Yrs Should be able to handle PD task independently and also should be able to manage the small team Should have experience in handling >1M instance count, 1 GHz frequency designs Should have experience in programming in Tcl/Tk/Perl to automate the design process and improve efficiency Must have hands-on experience on PNR Suite from Cadence & Synopsys (Innovus & ICC2) Strong experience in Static Timing Analysis (PrimeTime – SI), EM/IR-Drop analysis (PT-PX, Redhawk), Physical Verification (Calibre). Show more Show less

Skill:Formal verification in synopsys or cadence or siemens flow. Exp: 12- 18 yrs Location : PAN INDIA

Job TitleAI/ML Engineer - Time Series Forecasting & Clustering LocationBangalore Experience2+ Years Job TypeFull-Time Mandatory Skills: AI/ML Engineer with Time Series Forecasting & Clustering experience Responsibilities in Brief: Time Series Forecasting Build models to predict trends from time series data. Clustering Develop algorithms to group and analyze data segments. Data Insights Analyze data to enhance model performance. Team Collaboration Work with teams to integrate models into products. Stay Updated Apply the latest AI techniques to improve solutions. Qualifications: Education Bachelor s/Master s in Computer Science or related field. Experience Hands-on experience with time series forecasting and clustering. Skills Proficient in Python, R, and relevant ML tools Perks & Benefits: Health and WellnessHealthcare policy covering your family and parents. FoodEnjoy scrumptious buffet lunch at the office every day. Professional DevelopmentLearn and propel your career. We provide workshops, funded online courses and other learning opportunities based on individual needs. Rewards and RecognitionsRecognition and rewards programs in place to celebrate your achievements and contributions. Why join Relanto Health & FamilyComprehensive benefits for you and your loved ones, ensuring well-being. Growth MindsetContinuous learning opportunities to stay ahead in your field. Dynamic & InclusiveVibrant culture fostering collaboration, creativity, and belonging. Career LadderInternal promotions and clear path for advancement. Recognition & RewardsCelebrate your achievements and contributions. Work-Life HarmonyFlexible arrangements to balance your commitments. To find out more about us, head over to our Website and LinkedIn

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. General Summary: Low Power CAD Engineer – Key Responsibilities The Low Power CAD team is actively hiring for a Low Power CAD Engineer, responsible for optimizing power domains and ensuring efficient system-level power modeling. This role involves working with cutting-edge technologies like AI, ML, and 3DIC to enhance power efficiency. Key Responsibilities Include: Developing advanced Low Power flows and methodologies for estimation, optimization, and signoff Architecting AI & ML-driven LP flows to improve efficiency and design scalability Collaborating with SoC and Subsystems teams for seamless deployment of robust LP methodologies Working with EDA tool providers (Synopsys, Cadence) to enhance methodologies supporting emerging technologies in Automotive, AI/ML, and 3DIC Integrating Low Power methodologies across different stages of chip design, from RTL to final tape-out Performing deep analysis on power reduction strategies for high-performance computing, AI accelerators, and edge devices Programming & Automation – Expertise in Python and Perl to develop automation scripts and enhance workflow efficiency. Power Verification & Modeling – Strong knowledge of Unified Power Format (UPF) and hands-on experience with CLP/VCLP tools for Low Power static verification. Power Optimization – Practical experience with leading power estimation and optimization tools, including Synopsys PrimeTime PtPx and Ansys Power Artist. Methodology Development & Global Deployment – Spearheading Low Power methodology improvements and ensuring seamless integration across worldwide teams. Vendor Engagement & Tool Enhancement – Working closely with EDA vendor R&D teams (Synopsys, Cadence, etc.) to debug tools and implement enhancements. New Technology Assessment – Evaluating next-generation power tools, assessing feasibility, and leading deployment efforts. Technical Communication & Collaboration – Effectively conveying complex power concepts through both verbal and written communication, making them accessible to diverse audiences. Cross-Functional Teamwork – Operating in a fast-paced environment, requiring strong communication, planning, and execution skills while working with SoC, subsystem, and power management teams. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3075399 Show more Show less

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. IPPD: Physical design engineer Physical Implementation activities for high performance Cores for 16/14/7/5nm or lower technologies, which includes all or some of the below. Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), Low Power verification, PDN, Timing Closure and / or power optimization Exposure to PD implementation of PPA critical cores. Exposure to timing convergence of high frequency data-path intensive Cores and advanced STA concepts. Able to handle Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes. Understanding of clocking architecture. Tcl/Python/Perl Scripting aware for small automation Strong problem-solving skills , good communication skills and good team player Collaborate with design, DFT and PNR teams and support issue resolutions wrt constraints validation, verification, STA, Physical design, etc. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3073060 Show more Show less

Manager, AMS Design Analog/Mixed Signal Design PVT Sensor IP development is a critical offering for process , voltage , temperature and other monitoring Ips within SOC subsystem. Synopsys is market leader for these IP developments which are integral part of Silicon lifecycle monitoring. Job Overview Part of the rapidly expanding Sensor group, Manager, AMS Design drives and owns some of the leading Sensor IP design along with the team. This technical as well as management leadership position is responsible for IP group’s Analog/Mixed Signal Design abilities. This includes designing blocks like bandgap, temperature sensor, Analog to Digital converters, Oscillators, Power-on-reset , glitch detector and many other mixed signal Ips from scratch in latest technology nodes. The person needs to be a master of analog design with innovative mindset. Work will include architecture development, design, simulations and final ownership of silicon performance of the Ips in production. In addition to this understanding of digital flow and post silicon test/characterization is a desirable skill. Right candidate would have had good leadership experience and ability to manage a sizeable team towards its mission. Very strong people leadership with key drive. Also the leader will have a team responsible for the overall research and development of the IPs . Ensure productivity and efficiency of each team member ensuring career growth. Responsibilities And Duties Responsible for Analog design for MSIPs from architecture to production silicon Will set up and manage the team of Analog/Mixed Signal design experts Work out innovative design techniques to overcome challenges Team designs of bandgap, temperature sensors, Signa Delta ADCs , DAC, Voltage monitoring Ips, PLL Ensure right talent is identifies , managed , groomed and enable a stellar team performance Works together with global cross functional team for team’s success Qualifications BS or MS degree in Electrical Engineering/Computer Science/Computer Engineering. 10 - 15 years of experience in the fields of Analog/Mixed Signal design for leading edge technologies Innovation mindset with system modelling, architecture and best design practices Ability to lead a large team that will cover different R&D project for AMS IP development . Strong knowledge about custom SOC flow desirable. Understanding of Analog, digital flow and post silicon test/characterization is a desirable skill High in drive and bringing positive energy leading towards a mission Strong personal value system Preferred Skills High drive and people leadership skill Demonstrated experience with Analog/Mixed Signal Design and IP/Product ownership with Analog and Digital subsystems Thorough knowledge of AMS design flow with digital top SOC integration methodology Closely work with Analog Design and layout team by reviewing and guiding for best-in-class performance People management expertise, ability to bring good people and lead them from front Location: To be hired for Bhubaneswar About Us Synopsys, Inc. (Nasdaq:SNPS) is the Silicon to Software™ partner for creative companies developing the electronic products and software applications we rely on every single day. As the world’s 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software quality and security solutions. Whether you’re a system-on-chip (SoC) designer building advanced semiconductors, or a software developer writing applications that require the highest quality and security, Synopsys has the solutions needed to deliver exceptional, secure products for the era of connected everything. The company is headquartered in Mountain View, California, and has approximately 113 offices located throughout North America, South America, Europe, Japan, Asia and India. Since 1986, Synopsys has been at the heart of accelerating electronics innovation with engineers around the world having used Synopsys technology to successfully design and create billions of chips and systems that are found in the electronics that people rely on every single day. Synopsys considers all applicants for employment without regard to race, color, religion, sex, gender preference, national origin, age, disability, or status as a Covered Veteran in accordance with federal law. In addition, Synopsys complies with applicable state and local laws prohibiting discrimination in employment in every jurisdiction in which it maintains facilities. Synopsys Inc. also provides reasonable accommodation to individuals with a disability in accordance with applicable laws. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. PVT Sensor IP development is a critical offering for process, voltage, temperature and other monitoring IPs within SOC subsystems. Synopsys is a market leader for these IP developments which are integral parts of Silicon lifecycle monitoring. You Are: As a new, exciting, and challenging position, we are looking for a talented person that can show a great level of initiative and ability to work in a busy and fast-changing environment. This rewarding role is fundamental to the successful and smooth operation of the engineering teams. You will play a vital role in helping to strengthen and develop forecasting capabilities, based upon improved monitoring capacity and forward-looking project schedules. Contribute to the development and enhancement of layout design methodologies and best practices. Work closely with different function design leaders to understand/enhance processes and help to enhance methodology. Collaborate with internal infrastructure teams on compute grid, storage management, and job scheduling architecture, efficiency, maintenance, and forecasting. Understanding CAD infrastructure and methodology will help to set up project environments. Contribute to enhancing quality assurance methodology by adding more quality checks/gatings. Front End development process understanding and support internal tools development and automation to help improve productivity across ASIC design cycles. Work with design engineers on new tools/technology and new features evaluation and adoption. Perform physical verification and design rule checks to ensure design integrity and manufacturability. Stay updated with the latest industry trends and advancements in A&MS layout design. Understanding of tools like VC Spyglass, Verdi, & views like SDF, Liberty, etc., and other frontend views will add value to this position. Writing RTL Code and TCL is a good addition. The Impact You Will Have: Enhance layout design methodologies and best practices, contributing to the overall quality and efficiency of the design process. Improve project forecasting capabilities by leveraging advanced monitoring and scheduling techniques. Boost productivity across ASIC design cycles through the development and automation of internal tools. Ensure design integrity and manufacturability through meticulous physical verification and design rule checks. Stay at the forefront of industry advancements, bringing the latest trends and technologies into Synopsys' design practices. Collaborate effectively with cross-functional teams, driving innovation and continuous improvement in design methodologies. What You’ll Need: Bachelor’s or master’s degree in engineering or a related field. 2 to 3+ years of experience in A&MS frontend and backend views & collaterals development flows. Proficiency in industry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler. Exceptional knowledge of layout design methods, techniques, and methodologies. Experience with physical verification tools, such as Calibre or Assura. Understanding of semiconductor process technologies and their impact on layout design. Excellent problem-solving and systematic skills. Ability to work effectively in a team-oriented environment. Familiarity with Synopsys Tool set (such as FC/ICC2, Primetime, Formality, ICV). Good communication and interpersonal skills. Who You Are: You are a highly motivated individual with a strong technical background and a passion for innovation. You possess excellent problem-solving skills and thrive in a collaborative, team-oriented environment. Your ability to adapt to fast-paced, dynamic work settings and your proactive approach to challenges make you an invaluable asset to the team. You are dedicated to continuous learning and staying updated with industry advancements, ensuring that your contributions drive Synopsys' success in the competitive semiconductor landscape. The Team You'll Be A Part Of: You will be joining a dynamic and forward-thinking team focused on developing cutting-edge PVT Sensor IPs and enhancing SOC subsystems. Our team is dedicated to pushing the boundaries of technology and innovation, ensuring that Synopsys remains a market leader in the semiconductor industry. Collaboration, continuous improvement, and a commitment to excellence are the core values that drive our team's success. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process Show more Show less

R2R Accountant We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned accounting professional with over 10 years of proven experience in multi-country R2R (Record to Report) administration, particularly with a strong focus on Europe. You possess a deep understanding of Europe tax regulations and have a high degree of professionalism. You are adept at handling sensitive and confidential material and have excellent decision-making, problem-solving, and analytical skills. You have a degree or master’s degree from a recognized university and are proficient in both business needs and the technologies to implement them. Your interpersonal, written, and verbal communication skills are excellent, and you have a knack for delivering compelling presentations. You thrive in a collaborative environment and are always ready to support your peers to complete tasks efficiently. What You’ll Be Doing: Managing end-to-end R2R operations and related compliance activities for Europe entities. Performing month-end accruals and other closing deliverables for multiple Europe entities. Calculating Tax provision and CIT supporting. Setting up and monitoring recurring JVs in Blackline/SAP. Conducting cash forecasting and intercompany revenue forecasting. Reconciling open item GLs of the balance sheet using Blackline. Collaborating closely with departments such as AP, Treasury, Payroll, and Tax to minimize disputes. Understanding and applying Accounting Standards (US GAAP/IFRS). Preparing, posting, and reconciling intercompany invoices. Ensuring accuracy of financial report packs through R2R controls. Managing year-end statutory filings and closure activities. Organizing R2R function documentation (e.g., Desktop procedures, SOX Docs). Participating in ad-hoc projects to deliver process improvements and add value to the R2R organization. Contributing to tasks related to mergers and acquisitions. The Impact You Will Have: Ensuring timely and accurate financial reporting for multiple Europe entities. Maintaining compliance with Europe tax regulations and statutory requirements. Improving cash flow management through effective forecasting. Enhancing the accuracy and reliability of financial statements. Facilitating smooth audits through meticulous preparation and coordination. Driving process improvements and efficiency within the R2R function. Supporting organizational growth through participation in mergers and acquisitions. Fostering cross-departmental collaboration to resolve disputes and enhance operations. Contributing to a high-performance finance team through knowledge sharing and teamwork. What You’ll Need: 10+ years of experience in multi-country R2R administration, with a focus on Europe. A degree or master’s degree from a recognized university. Strong knowledge of Europe tax regulations. High degree of professionalism and ability to handle confidential material. Excellent decision-making, problem-solving, and analytical skills. Proficiency in accounting standards (US GAAP/IFRS). Experience with Blackline and SAP. Who You Are: Detail-oriented with a strong focus on accuracy. Effective communicator with excellent interpersonal skills. Team player who supports peers to achieve common goals. Proactive and able to work independently with minimal supervision. Adaptable and open to change, with a continuous improvement mindset. The Team You’ll Be A Part Of: As a member of the COE Finance team, you will be responsible for the daily operations of the Record to Report processes, ensuring that these processes are handled timely and efficiently. You will work closely with various departments such as AP, Treasury, Payroll, and Tax to ensure quality in reporting and compliance. The team is dedicated to continuous improvement and collaboration, striving to add value to the organization through innovative approaches and solutions. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

You Are: You are a seasoned professional with a robust understanding of project and program management. You have a knack for driving the on-time delivery of patches and releases for small products and can assist with larger product releases. You possess excellent interpersonal and communication skills, enabling you to interface seamlessly between R&D, DevOps, management, and Application Engineers. You bring a wealth of experience in software development, particularly in C/C++, and have an in-depth knowledge of project management concepts. Your passion for customer focus and quality is evident in your work, and you are always on the lookout for tools and automation to improve productivity and quality. You thrive in a process-oriented environment, are confident in handling conflicting situations, and can work effectively across multiple teams and geographies. Your background in the EDA domain and knowledge of configuration management tools and Unix environments make you a valuable asset. With over 5 years of relevant experience in program management, process and releases, or software development, you are ready to take on new challenges and drive success for Synopsys. What You’ll Be Doing: Take ownership and drive on-time delivery of patches and releases for small products. Assist other Release Managers on larger products and assignments. Independently drive commitments and convergence of patches and releases as per established processes, welcoming new ideas. Act as the interface between R&D, DevOps, management, and Application Engineers. Utilize excellent interpersonal, communication, and follow-up skills to ensure team collaboration and success. Apply hands-on experience in C/C++ software development to enhance project outcomes. What You’ll Need: Hands-on experience in C/C++ software development. In-depth knowledge of program management concepts. Experience with Perforce, Perl, Shell scripts, Python, Make, and other industry-standard configuration management tools. Proficiency in Unix environments. 5+ years of relevant experience in program management, process and releases, or software development. Excellent academic background with a B.E./B.Tech/M.Tech in Computer Science, Electrical, or Electronic Engineering from reputed universities. Who You Are: Process-oriented and confident in handling conflicting situations. Flexible, resourceful, and responsible in completing assigned tasks. Passionate about customer focus and quality. Enthusiastic about trying new tools and automation for productivity and quality improvements. Experienced in multi-team, cross-geography product delivery. Show more Show less

You Are: You are a seasoned professional with a robust understanding of project and program management. You have a knack for driving the on-time delivery of patches and releases for small products and can assist with larger product releases. You possess excellent interpersonal and communication skills, enabling you to interface seamlessly between R&D, DevOps, management, and Application Engineers. You bring a wealth of experience in software development, particularly in C/C++, and have an in-depth knowledge of project management concepts. Your passion for customer focus and quality is evident in your work, and you are always on the lookout for tools and automation to improve productivity and quality. You thrive in a process-oriented environment, are confident in handling conflicting situations, and can work effectively across multiple teams and geographies. Your background in the EDA domain and knowledge of configuration management tools and Unix environments make you a valuable asset. With over 5 years of relevant experience in program management, process and releases, or software development, you are ready to take on new challenges and drive success for Synopsys. What You’ll Be Doing: Take ownership and drive on-time delivery of patches and releases for small products. Assist other Release Managers on larger products and assignments. Independently drive commitments and convergence of patches and releases as per established processes, welcoming new ideas. Act as the interface between R&D, DevOps, management, and Application Engineers. Utilize excellent interpersonal, communication, and follow-up skills to ensure team collaboration and success. Apply hands-on experience in C/C++ software development to enhance project outcomes. What You’ll Need: Hands-on experience in C/C++ software development. In-depth knowledge of program management concepts. Experience with Perforce, Perl, Shell scripts, Python, Make, and other industry-standard configuration management tools. Proficiency in Unix environments. 5+ years of relevant experience in program management, process and releases, or software development. Excellent academic background with a B.E./B.Tech/M.Tech in Computer Science, Electrical, or Electronic Engineering from reputed universities. Who You Are: Process-oriented and confident in handling conflicting situations. Flexible, resourceful, and responsible in completing assigned tasks. Passionate about customer focus and quality. Enthusiastic about trying new tools and automation for productivity and quality improvements. Experienced in multi-team, cross-geography product delivery. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned network engineering professional with a robust background in designing and implementing enterprise network architectures. You thrive in dynamic environments and excel in providing strategic direction and innovative solutions. With your extensive experience in network and security operations, you are adept at collaborating with executive management and cross-functional teams. You possess a proactive approach, identifying opportunities for improvement and automation while maintaining a keen eye on security and performance. Your technical expertise is complemented by your ability to communicate complex concepts clearly and effectively. What You’ll Be Doing: Create architectural approaches for Enterprise Network design and implementation. Provide architectural governance and oversight over MSP supplied solutions. Explore, investigate, recommend, benchmark, and implement technologies for SDN and service orchestration. Offer in-depth Network & Security Operations subject matter expertise and guidance to executive management and other stakeholders. Collaborate with cross-functional teams to resolve complex technical issues, ensuring minimal disruption to business operations. Liaise with various vendors and suppliers to optimize existing Network Services. Provide technological vision and strategy for Network transformation, leading architecture discussions to address risk, security, capacity, and performance concerns. Maintain vulnerability management processes and policies using a risk-based priority methodology. Identify and implement opportunities for process automation and improvement. Aid with change management processes, including impact analysis, risk assessment, change plan, test plan, monitoring, and user communications. The Impact You Will Have: Drive significant productivity, robustness, agility, and time-to-market advantage in the creation of Synopsys products and solutions. Lead corporate infrastructure transformation, enhancing IT operations leadership. Improve and optimize Network Services, contributing to the overall efficiency and performance of the enterprise network. Enhance security measures and risk management, safeguarding the organization’s critical assets. Facilitate seamless collaboration across teams, ensuring timely resolution of technical issues. Contribute to the continuous improvement of network services and user experience. What You’ll Need: Demonstrated experience with risk assessments and vulnerability assessments, using tools like Qualys, Rapid7, Tenable, Wiz, etc. Expertise in Enterprise Network Architecture Designs and Security Implementations. Knowledge of Internet/DMZ/Internal Firewalls, Identity Access Management (IAM), Risk Management, Security Information Event Management (SIEM), and Web Proxy Services. Hands-on experience with network security areas such as NGFWs, IDS/IPS, SSE/SASE, SWG, ZTNA. Management and patching experience with DataCenter network technologies (e.g., Cisco ACI, Whitebox Switching with SONiC OS, BeyondEdge orchestrator, Cisco Nexus Platforms). Administration of campus infrastructure: Cisco Catalyst and Aruba OS Switching, Aruba Wireless Controllers, APs, Versa Networks SD-WAN appliances. Understanding of cloud architectures (AWS, Azure, GCP, IBM Cloud) and cloud connectivity solutions. Strong knowledge of routing protocols and failover scenarios, including BGP and OSPF. Network device configuration and infrastructure automation skills using tools such as Python and Ansible. Who You Are: Proactive and self-motivated, able to drive results with minimal supervision. Excellent communicator, capable of conveying complex technical concepts to diverse audiences. Strategic thinker with a focus on continuous improvement and innovation. Collaborative team player, adept at working with cross-functional teams. Detail-oriented and highly organized, with strong problem-solving skills. The Team You’ll Be A Part Of: The Engineering Excellence Group drives innovation velocity and enterprise infrastructure automation, which are critical elements of our growth and scaling strategy. This team is chartered to drive significant productivity, robustness, agility, and time-to-market advantage in the creation of Synopsys products and solutions. The group also leads corporate infrastructure transformation as we continue to drive IT operations leadership and invest in the next wave of disruptive technologies. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and skilled R&D Engineer with a deep understanding of system verification. You are enthusiastic about developing cutting-edge verification solutions for high-performance computing, data centers, mobile/client devices, automotive systems, and IoT segments. Your experience in architecting and building SystemVerilog UVM-based verification components, coupled with your expertise in cache coherency protocols and functional verification, makes you an ideal candidate for this role. You are a team player with excellent problem-solving abilities, strong analytical skills, and a keen attention to detail. Your background in verification IP development and your programming prowess in languages like Perl, Python, and Shell scripting set you apart as a valuable asset to our team. What You’ll Be Doing: Responsible for functional verification involving coherent and non-coherent IP designs. Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. Developing verification plans and driving functional coverage-driven verification closure of real designs. Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You’ll Need: B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 5-8 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 4-8 years of relevant experience. Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. In-depth understanding of cache coherency protocols such as Protocol experience: Should have experience in any of the protocols, UCIe/PCIe/CXL/Unipro/USB/MIPI/HDMI/Ethernet/DDR/LPDDR/HBM memory protocol Experience in creating verification plans and achieving functional coverage-driven verification closure of real designs. Proficiency in writing scripts using Perl, Python, and Shell scripting. Who You Are: Excellent problem-solving, debugging, and analytical skills. Strong programming skills and familiarity with object-oriented programming concepts. Creative and innovative mindset. Excellent verbal and written communication skills. A collaborative team player with a passion for functional verification. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and skilled R&D Engineer with a deep understanding of system verification. You are enthusiastic about developing cutting-edge verification solutions for high-performance computing, data centers, mobile/client devices, automotive systems, and IoT segments. Your experience in architecting and building SystemVerilog UVM-based verification components, coupled with your expertise in cache coherency protocols and functional verification, makes you an ideal candidate for this role. You are a team player with excellent problem-solving abilities, strong analytical skills, and a keen attention to detail. Your background in verification IP development and your programming prowess in languages like Perl, Python, and Shell scripting set you apart as a valuable asset to our team. What You’ll Be Doing: Responsible for functional verification involving coherent and non-coherent IP designs. Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. Developing verification plans and driving functional coverage-driven verification closure of real designs. Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You’ll Need: B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 5-8 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 4-8 years of relevant experience. Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. In-depth understanding of cache coherency protocols such as Protocol experience: Should have experience in any of the protocols, UCIe/PCIe/CXL/Unipro/USB/MIPI/HDMI/Ethernet/DDR/LPDDR/HBM memory protocol Experience in creating verification plans and achieving functional coverage-driven verification closure of real designs. Proficiency in writing scripts using Perl, Python, and Shell scripting. Who You Are: Excellent problem-solving, debugging, and analytical skills. Strong programming skills and familiarity with object-oriented programming concepts. Creative and innovative mindset. Excellent verbal and written communication skills. A collaborative team player with a passion for functional verification. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and skilled R&D Engineer with a deep understanding of system verification. You are enthusiastic about developing cutting-edge verification solutions for high-performance computing, data centers, mobile/client devices, automotive systems, and IoT segments. Your experience in architecting and building SystemVerilog UVM-based verification components, coupled with your expertise in cache coherency protocols and functional verification, makes you an ideal candidate for this role. You are a team player with excellent problem-solving abilities, strong analytical skills, and a keen attention to detail. Your background in verification IP development and your programming prowess in languages like Perl, Python, and Shell scripting set you apart as a valuable asset to our team. What You’ll Be Doing: Responsible for functional verification involving coherent and non-coherent IP designs. Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. Developing verification plans and driving functional coverage-driven verification closure of real designs. Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You’ll Need: B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 5-8 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 4-8 years of relevant experience. Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. You will be responsible for functional verification involving coherent and non-coherent IP designs. Proficiency in writing scripts using Perl, Python, and Shell scripting. Who You Are: Excellent problem-solving, debugging, and analytical skills. Strong programming skills and familiarity with object-oriented programming concepts. Creative and innovative mindset. Excellent verbal and written communication skills. A collaborative team player with a passion for functional verification. Show more Show less

Alternate Job Titles: Staff SOC Engineer Senior SOC Design Engineer Lead SOC Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and motivated SOC Engineer with a passion for cutting-edge technology and innovation. With a strong background in system-on-chip (SOC) design and verification, you bring a wealth of knowledge and a keen eye for detail. You thrive in a collaborative environment, working seamlessly with cross-functional teams to deliver high-quality solutions. Your problem-solving skills are exceptional, and you have a proven track record of successfully managing complex projects. You are proactive, adaptable, and always eager to learn and grow in a dynamic and fast-paced setting. What You’ll Be Doing: Designing and implementing SOC solutions for various applications, ensuring high performance and reliability. Collaborating with cross-functional teams to define and develop SOC architecture and specifications. Conducting verification and validation of SOC designs to ensure compliance with industry standards and customer requirements. Optimizing SOC designs for power, performance, and area (PPA) to meet project objectives. Debugging and resolving issues in SOC designs, utilizing advanced tools and methodologies. Providing technical guidance and mentorship to junior engineers, fostering a culture of continuous improvement and innovation. Job Description And Requirements The role is for RTL Design and Signoff of IP/Subsystem/SoC Design in the System Solutions Group (SSG). At SSG, we are a team of experts in various Synopsys technologies to deliver architecture, design, verification, implementation, tools, methodology to enable our customers complete their most challenging SoC Design projects. Our work spans from sub-blocks to full turnkey end-to-end SoCs. Our customers range from start-ups to industry leaders, commercial companies, and government agencies. As part of this role, you can expect to develop and deliver your expertise in RTL Signoff and RTL Design Techniques while working on activities such as Lint/CDC/RDC Checks, Timing Constraints Development, Preliminary Synthesis, Formality and RTL Design. The role will expose you to various innovative technologies deployed for RTL Quality Signoff for Semiconductors. Responsibilities Perform RTL Quality Signoff Checks such as LINT, CDC, RDC. Understand the design/architecture and develop timing constraints for synthesis and timing. Run preliminary synthesis to ensure that the design can be synthesized as intended. Run formality to ensure equivalence of RTL and gates. Integrate IPs in SoCs/Subsystems and create RTL design as per need of the customer. Required B.E/B. Tech/M.E/M. Tech in electronics with 4-9 years’ experience in RTL Design and Verification. Hands-on experience on static verification tools such as Spyglass performing LINT, CDC, RDC. Good conceptual understanding of design/architecture pitfalls across clock/reset domain crossing. Good conceptual understanding of RTL rule checks. Hands-on experience on synthesis and timing constraints development. Candidates with experience on ARM based technologies (Coresight Debug, Processor architecture, etc.) will be preferred. The Team You’ll Be A Part Of: You will join a highly skilled and motivated team dedicated to developing advanced SOC solutions. Our team focuses on innovation, collaboration, and excellence, working together to deliver high-quality designs that drive technological advancements. We value diversity and inclusion, fostering a supportive and dynamic environment where every team member can thrive and contribute to our success. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and skilled R&D Engineer with a deep understanding of system verification. You are enthusiastic about developing cutting-edge verification solutions for high-performance computing, data centers, mobile/client devices, automotive systems, and IoT segments. Your experience in architecting and building SystemVerilog UVM-based verification components, coupled with your expertise in cache coherency protocols and functional verification, makes you an ideal candidate for this role. You are a team player with excellent problem-solving abilities, strong analytical skills, and a keen attention to detail. Your background in verification IP development and your programming prowess in languages like Perl, Python, and Shell scripting set you apart as a valuable asset to our team. What You’ll Be Doing: Responsible for functional verification involving coherent and non-coherent IP designs. Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. Developing verification plans and driving functional coverage-driven verification closure of real designs. Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You’ll Need: B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 5-8 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 4-8 years of relevant experience. Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. In-depth understanding of cache coherency protocols such as Protocol experience: Should have experience in any of the protocols, UCIe/PCIe/CXL/Unipro/USB/MIPI/HDMI/Ethernet/DDR/LPDDR/HBM memory protocol Experience in creating verification plans and achieving functional coverage-driven verification closure of real designs. Proficiency in writing scripts using Perl, Python, and Shell scripting. Who You Are: Excellent problem-solving, debugging, and analytical skills. Strong programming skills and familiarity with object-oriented programming concepts. Creative and innovative mindset. Excellent verbal and written communication skills. A collaborative team player with a passion for functional verification. Show more Show less

We are looking for a highly motivated individual, with expertise in IC design and physical implementation for a group with growth opportunities. Responsibilities include complete digital implementation from RTL to GDS including Synthesis, Floor-Planning, Power Planning and Analysis, CTS, Placement and Routing, STA, Formal Verification, EMIR Signoff and physical verification. The individual will contribute both on the implementation side as well as flow development for a variety of advanced high performance interface IPs, Test chips & Subsystems at latest techno nodes. The successful candidate: has solid engineering understanding of the underlying concepts of IC design, implementation flows and sign-off methodologies for deep submicron design. has intimate knowledge of the full design cycle from RTL to GDSII, including development of timing constraints has good scripting & programming skills (Perl, Tcl, Python etc); knowledge of CAD automation methods. Can interface with the larger product team to understand design constraints, deliverable formats, customer requirements Independent, timely decision maker and able to cope with interrupts Knowledge of IP Subsystem implementation & FE flows are added advantages 8+ years of hands-on experience in ASIC physical implementation and EDA tools with recent contribution to project tape-outs. Must demonstrate knowledge of the Synopsys tools, flows and methodologies including Design Compiler, IC Compiler/2, Fusion Compiler, Primetime, Formality, Star-RCXT, Hercules/ICV and other industry tools. Show more Show less

Responsibilities: Build and guide a team of DFT engineers to deliver the architecture and the DFT deliveries towards SOC development. Engage with the RTL & physical design program management to plan and execute the DFT deliveries. Work with cross-functional teams (e.g., design, verification, test engineering) to integrate DFT features effectively. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise : At least 10+ years of experience in DFT implementation / methodology Strong understanding of digital design and test principles. Proficiency in DFT techniques, such as scan insertion, BIST, and Automatic Test Pattern Generation (ATPG), MBIST insertion Experience with EDA tools , Synopsys and Cadence &scripting languages (e.g., Python, TCL). Knowledge of IC design flows, verification tools, and fault models Ability to identify, analyze, and resolve testing challenges. Work effectively within multidisciplinary teams, communicating complex technical details clearly. Ensure thorough testing, comprehensive fault coverage, and alignment with industry standards. Technically lead/managed 10 - 15 DFT engineers to deliver DFT implementation on SOC Preferred technical and professional experience NA

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day. Job Responsibilities BE/BTECH/ME/MTECH Or Equivalent Degree Job Description – Memory Design Engineer ( 15-25 Yrs ) Location : Hyderabad Cadence is recruiting highly motivated Memory Designers to work in the Memory IP team based in Hyderabad. The roles and responsibilities will include the design, simulation and verification of custom memory design blocks. Job role Circuit design & simulation of memory circuits Characterization Functional simulations and statistical analysis Sign off and release the memory IP s Designing circuits for Memory testchip Silicon bring-up and characterization. Required Qualifications Experience in SRAM/ROM/TCAM Memory designs Requires Bachelor/Masters/ PhD in Electrical,VLSI, Microelectronics 15years of experience. Proficient knowledge of and experience with Cadence, Mentor Graphics, Synopsys tools for schematic design & simulations. Experience in timing characterization General concepts around Circuit design, Reliability analysis, Statistical analysis of circuits should be good. Good technical verbal and written communication skills Ability to work with cross functional teams Ability to handle concurrent projects. Preferred Qualifications Knowledge in various technologies like Bulk, CMOS & SOI process is desirable Hands on knowledge of state-of-the-art memory or analog design flows Programming experience applicable to design flow automation tasks Exposure to 2nm, 3nm, 5nm technology nodes is an advantage. Exceptional Spoken and Written Proficiency in English Strong analytical and problem-solving skills. We’re doing work that matters. Help us solve what others can’t. Show more Show less

Are you an expert in Design for Test (DFT) , and we're looking for a talented Principal DFT Engineer to join our dynamic engineering team in Hyderabad. This is a unique opportunity to lead critical DFT implementation for cutting-edge ASIC designs while shaping the future of our DFT practices. As a Principal DFT Engineer , you will take on a leadership role in delivering DFT (including ATPG) implementation at both the chip and block levels. You will lead DFT strategy, manage the implementation of DFT structures, perform formal checks, debug test pattern mismatches, and ensure timing closure in DFT modes. This role may involve acting as an industry-leading expert in a specific area of DFT or leading a team to deliver complete DFT solutions from architecture to pattern generation. Key Responsibilities: DFT Strategy & Implementation: Lead the DFT work in projects, including the definition of DFT strategy, implementation of DFT structures, and verification of the DFT structures to meet the project's testability requirements. DFT Expertise: Serve as an expert in DFT tools and techniques, demonstrating advanced skills in tools from Mentor, Synopsys, or Cadence. Complex Problem Solving: Address and resolve complex issues related to DFT, ATPG, timing closure, and ATE chip bring-up, providing solutions to challenges across multiple projects. Leadership & Mentorship: Lead DFT design projects and mentor junior engineers, providing guidance in technical aspects and helping to manage the team’s workflow and priorities. Customer Interface & Project Management: Act as the main customer interface for DFT aspects of the project, ensuring clear communication and alignment. Take responsibility for managing multiple assignments from different customers and teams. Continuous Improvement: Analyse customer feedback and recognise business opportunities. Collaborate with the Sondrel Business Team to push these opportunities forward. Technical Contributions: Contribute to technical white papers, present at internal and external conferences, and participate in sales support, such as preparing Statements of Work. Team Organisation: Organise and manage teams effectively, setting and adjusting priorities quickly to meet project timelines. Key Relationships: Internal: Reports to: Regional Engineering Head Collaborates with: Engineers, Project Leaders, Sales, Finance, and HR teams Supervises: Engineers, Senior Engineers, and Staff Engineers External: Customers: Minimal technical engineer-to-engineer communication Suppliers: EDA Tool Vendors, Foundries, and Assembly Houses Qualifications: Essential: A Bachelor’s degree, Master’s, or PhD in Engineering or a related field. Typically 10+ years of experience in the microelectronics field, specifically in DFT. Strong Project Management skills. Desirable: A project management qualification. Additional experience in high-level design teams, especially in DFT architecture. Skills & Experience: Essential: Extensive experience with DFT tools (e.g., Mentor, Synopsys, Cadence) and techniques including: IJTAG/Scan/MBIST/BSD/LBIST/Boundary Scan insertion. ATPG/TC improvements and pattern generation. Pattern simulation (Zdel/SDF) and pattern verification (VCS, NC-Verilog, NC-Sim, ModelSim). Diagnosis of ATE failures and silicon bring-up. Deep understanding of DFT architecture design and implementation. Strong problem-solving skills and ability to lead or collaborate in a DFT team. Expertise in managing complex, technical DFT projects. Advanced scripting skills in Python, TCL, Perl, Shell, or similar languages. Proven ability to evaluate issues, define solutions, and make sound judgments in technical environments. Desirable: Ability to apply advanced knowledge in specific areas of physical design or a broad understanding across multiple sub-functions of DFT. Proven capability to contribute to business development and customer engagement. Attributes: Team leader with strong organisational skills and the ability to manage multiple priorities. Active listening skills and the ability to motivate a team to work under pressure. Excellent attention to detail and high level of self-motivation. Strong conflict resolution skills and the ability to quantify risks and estimate engineering effort. Ability to think creatively and "outside the box." Why Aion Silicon? At Aion, we are committed to advancing the boundaries of digital design. You’ll be leading key DFT projects in a collaborative, innovative, and growing team. This is a fantastic opportunity to have a direct impact on both technical and business outcomes while working on cutting-edge ASIC designs in a global environment. If you are a seasoned Principal DFT Engineer with a passion for leading technical teams and projects, we would love to hear from you. Show more Show less

Aion Silicon is seeking an experienced Physical Design Engineers to join our growing team in UK/Barcelona/Morocco or Hyderabad . As part of a dynamic physical implementation design team, you will be responsible for block development and potentially full chip responsibility, taking designs from RTL to GDS. This is an exciting opportunity for an individual who is self-motivated, detail-oriented, and passionate about contributing to the development of high-quality, cutting-edge designs. Key Responsibilities: Independent Work: Contribute to physical design projects with minimal supervision, delivering high-quality results. Problem Solving: Address and resolve moderate complexity design challenges, applying sound judgment to interpret results and conduct quantitative analysis. Physical Design Ownership: Take responsibility for various aspects of the physical design flow, from RTL to GDS, ensuring timely and accurate delivery. Multi-Project Management: Handle multiple assignments from different customers or teams, ensuring that deadlines and quality standards are met. Collaboration: Work closely with more experienced team members to resolve design issues, applying expertise in physical design tools and techniques. Tool Expertise: Demonstrate proficiency in one or more tools such as Synthesis, PnR, Formal verification, Custom layout techniques, Analog simulation, or Chip finishing. Documentation and White Papers: Contribute to the development of technical white papers and presentations. Sales Support: Contribute to sales activities, including Statement of Work preparation. Time Management: Maintain accurate timekeeping and manage your workload effectively. Self-Discipline: Execute design tasks efficiently, adhering to best practices and maintaining a high standard of work. Key Relationships: Internal: Reports to: Engineering Manager/Principal Engineer Collaborates with: Engineers, Senior Engineers, Principal Engineers, Project Managers, Sales, Finance, and HR teams Supervises: Physical Design Team (2-3 engineers) External: Customers: Minimal technical engineer-to-engineer communication Suppliers: EDA Tool Vendors, Foundries, and Assembly Houses Qualifications: Essential: A degree, Master's, or PhD in a relevant subject. Typically, 5+ years of experience in physical design and implementation. Desirable: Master's or PhD in a related subject with 5+ years of practical experience. Skills & Experience: Essential: Good tapeout experience on multiple technologies (e.g., 5nm, 7nm, 12nm, 28nm). Experience with physical verification checks (e.g., DRC, LVS, ANTENNA, ERC). Solid understanding of synthesis, floorplanning, placement, CTS, routing, and STA concepts. Experience with physical design tools such as: PnR tools: Synopsys ICC, Cadence EDI, Mentor Olympus Synthesis tools: Synopsys DC, Cadence RC Formal verification tools: Formality, Formalpro Physical verification tools: Mentor Calibre, Synopsys IC Validator Demonstrated ability to solve problems independently and as part of a team. Strong scripting skills in Tcl, Perl, or Python. Strong capability in managing projects and delivering results on time. Desirable: Broad knowledge across multiple sub-functions within physical design. Proven ability to contribute to multi-disciplinary teams. Attributes: Essential: Excellent self-organisation and adaptability to changing priorities. Strong leadership skills with the ability to manage and guide a small team. Ability to work under pressure and manage multiple projects simultaneously. Excellent organisational and problem-solving skills. Self-motivated with the ability to work independently. Strong attention to detail and commitment to delivering high-quality results. Why Aion? At Aion, we are passionate about pushing the boundaries of digital design. As part of our new office in Barcelona, you’ll be joining an innovative and collaborative team, with opportunities to work on cutting-edge ASIC designs. This role offers significant responsibility and the opportunity to influence the direction of key projects. If you're a skilled Physical Design Engineer with a passion for technology and leadership, we’d love to hear from you! Show more Show less

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. 5+ Year of industry experiences in the following areas: Expertise in Synthesis - Synopsys Design Compiler, DCG/DC_NXT/Fusion Compiler and/or Cadence RC/Genus. o Hands on with multi-voltage, power aware synthesis, UPF flows in synthesis and low power designs. o Expertise in formal verification with Cadence LEC/ Synopsys Formality o Expertise in writing and debugging timing constraints o Perl and/or TCL scripting, makefile flows. Qualcomm's compute sub system engineers will work on next generation low power, machine Learning sub-system for our system-on-chip (SoC) products used in Smartphone, Automotive and other low power devices. Become a key member of the core team developing fastest smartphone SoC devices implemented on the latest cutting-edge process technologies. In this role candidate will be responsible for compute sub system implementation that includes Physically aware Synthesis -DCG/Fusion Compiler/Genus. In addition, he/she will perform tasks toward constraints development, clock definitions, timing analysis, UPF, CLP check, Formal Verification and ECO flow. He/She will be working closely with physical Design team to optimize designs for power, area, and performance. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. IPPD: Physical design engineer Physical Implementation activities for high performance Cores for 16/14/7/5nm or lower technologies, which includes all or some of the below. Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), Low Power verification, PDN, Timing Closure and / or power optimization Exposure to PD implementation of PPA critical cores. Exposure to timing convergence of high frequency data-path intensive Cores and advanced STA concepts. Able to handle Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes. Understanding of clocking architecture. Tcl/Python/Perl Scripting aware for small automation Strong problem-solving skills , good communication skills and good team player Collaborate with design, DFT and PNR teams and support issue resolutions wrt constraints validation, verification, STA, Physical design, etc. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 11861 Date posted 06/03/2025 Description Candidate will be part of TCM Front End team. Design, develop, troubleshoot the core algorithms used in TCM Front End tool Design and develop standard and customized features / checks in TCM FE for seamless consumption of VCS OM. Will be working with other local and global teams of TCM and VC SpyGlass Design and development of state-of-the-art EDA tools involving development of new and innovative algorithms. Create test cases to test the developed feature. Skills Required Strong knowledge of Front-end compilers and their flow Ability to develop new software architecture and good leadership skills. Fluent in C/C++ with extensive work experience in data-structures and algorithms. Good knowledge of Verilog, SystemVerilog & VHDL HDL. Excellent algorithm analysis skills and a good knowledge of data structures. Familiarity with ASIC design flow and the EDA tools and methodologies used therein. Familiarity with multi-threaded and distributed code development. Self-motivation, self- discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. Quality focus - one who believes in quality and wants to make a difference. Experience of production code development on Unix/Linux platforms. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. About the role: We are seeking a highly motivated and detail-oriented Application Support Engineer to join our dynamic, fast paced and growth-mindset team. In this role, you will be focused on supporting the Questa verification products, specifically in Verification IP line of products. In this position, you will be working closely with the product engineering team, field application engineers and customers. As an ASE, you will be solving some of our customers complex design, testbench and environment issues in the domain of functional verification. You will also be working closely on creating knowledge-based content and providing expertise on the Questa platform. You will work with multiple customers to understand their challenges and flow and be involved in technical presentations, training, evaluation and competitive benchmarking. You will part of the larger application support engineering organization and will be interfacing regularly with the North American and PACRIM teams. Minimum Qualifications: BS Electronic/Computer Engineering from an accredited institution Minimum of 2+ years of Digital Design/Verification experience Knowledge of VHDL or Verilog, or SystemVerilog RTL languages for ASIC or FPGA design Experience with ASIC or FPGA hardware design and implementation using RTL tool flows and methodologies Knowledge of Windows and Linux OS Self-motivated, flexible, self-disciplined, and comfortable in a dynamic, quick-moving environment. Strong interpersonal and communications skills with the ability to quickly establish rapport and credibility with our customers, sales, and product teams. Strong oral, and written communication, and presentation skills Excellent organizational and time management skills Preferred qualifications: MS Electronic/Computer Engineering Knowledge of UVM and System Verilog for Verification Clock Domain Crossing (CDC), Static and Formal Verification – Formal Applications Working knowledge of Working knowledge of Questa-Modelsim, VCS (Synopsys), NCSim (Cadence) or Aldec simulators. Knowledge of C/C++ programming languages Demonstrated proficiency with Object-Oriented Programming experience in test bench architecture and design Knowledge of scripting languages (e.g., Shell, Tcl, Perl, Python) Knowledge of CDC, low power and formal methodologies. Location : Noida/ Bangalore Why us? Working at Siemens Software means flexibility - Choosing between working at home and the office at other times is the norm here. We offer great benefits and rewards, as you'd expect from a world leader in industrial software. A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we welcome applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit, and business need. Bring your curiosity and creativity and help us shape tomorrow! Siemens Software. Transform the Everyday Show more Show less