876 Synopsys Jobs - Page 4

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: The ideal candidate for the Project Engineering Management, Staff Engineer role is a seasoned Technical Project Manager with a strong focus on Product Security Compliance. You will leverage your exceptional project management skills to drive complex projects related to Open-source projects and Product Security. You will play a critical role in ensuring the security and integrity of our products while collaborating with cross-functional teams to drive initiatives that enhance our security posture. You will oversee the planning, execution, and delivery of complex security compliance projects. You will work closely with security engineers, product managers, business stakeholders, and IT teams to ensure that projects are delivered on time, within scope, and within budget. This role requires a strong understanding of Open Source, Product Security, and project management principles. In addition, you will coordinate cross-product dependencies, identify and escalate issues, manage risk and change from conception to delivery, and drive problem resolution through fact-based, conscious decision-making while promoting, implementing, and improving team, cross-functional, and cross-departmental business and engineering processes and practices. What You’ll Be Doing: Manage security-focused projects, ensuring alignment with organizational goals and industry standards. Oversee security initiatives related to open-source projects, including assessing vulnerabilities, coordinating remediation efforts, and promoting best practices within the engineering teams. Collaborate closely with stakeholders to define project objectives, scope, and deliverables. Develop and maintain comprehensive project plans. Drive effective communication and collaboration across cross-functional teams. Monitor program progress and implement solutions to keep projects on track. Drive continuous improvement initiatives by evaluating current processes and recommending enhancements to increase efficiency and security effectiveness. Proactively identify challenge areas and risks requiring executive engagement. Identify issues and roadblocks, and escalate with the right level of details and priority. Drive problem resolution through fact-based, conscious, and quality decision-making. The Impact You Will Have: Ensure the security and integrity of Synopsys' products, particularly in open-source environments. Lead the initiatives w.r.t product security. Develop strategic project plans that align with organizational goals and industry standards. Facilitate cross-functional collaboration to enhance communication and project outcomes. Implement solutions to keep projects on track, ensuring timely delivery and high-quality results. Promote best practices and continuous improvement initiatives within the engineering teams. Identify and mitigate risks, ensuring proactive management of potential challenges. Provide valuable insights and recommendations based on data analytics, driving enhancements in product security. Foster a culture of security awareness and compliance within the organization. Contribute to the overall success of Synopsys' security and data engineering initiatives. What You’ll Need: Project Management Experience: 2+ years of experience specifically in technical program management with overall experience of 8 to 12 years. Hands-on working knowledge in Python / Perl. Ability to do code reviews and take part in design discussions. Product Security Knowledge: Strong understanding of product security principles, especially related to open-source projects. Experience with cloud platforms such as AWS, Azure, or Google Cloud. Communication skills: Excellent verbal and written communication abilities for cross-functional collaboration. Stakeholder Management: Ability to define project objectives and collaborate closely with stakeholders. Project Planning: Skills in developing and maintaining comprehensive project plans. Who You Are: A proactive and detail-oriented leader who can manage complex projects and drive them to successful completion. An excellent communicator who can effectively collaborate with cross-functional teams and stakeholders. A strategic thinker with a strong understanding of product security and data engineering principles. A problem solver who can identify challenges and implement effective solutions. A continuous learner who stays updated with the latest industry trends and best practices. The Team You’ll Be A Part Of: This role helps Synopsys build products securely and be compliant with security standards. The EPMO team provides program management support to all the Synopsys Central Engineering programs and initiatives. The main focus of this role would be to ensure product security compliance and provide program management support to Data Engineering initiatives in Synopsys Central Engineering.

Hiring for our esteemed clients who is a tech giant Job Title / Designation: Project Manager to Associate Director (Based on experience & expertise) Department / Business Unit: Embedded Engineering Services (EES) Industry Experience: 10+ years Job Location Preferred: Bangalore Alternate Option: Pune Compensation: Upto 40L Role Summary We are looking for an experienced engineering leader to drive strategic initiatives in embedded software validation and platform enablement for global semiconductor clients. This role involves owning the delivery practice end-to-end while collaborating across functional teams. Key Responsibilities Lead strategic initiatives in Pre-Silicon and Post-Silicon software validation, bring-up, and platform enablement. Build and define competency roadmap in firmware, BSP, and validation across various silicon platforms (MPUs, SoCs, MCUs). Translate SoC platform roadmaps and customer requirements into execution plans. Collaborate with global clients and internal teams for planning, execution, and delivery. Manage stakeholder expectations across silicon design, software, systems, and validation functions. Handle escalations and risks throughout validation and integration cycles. Support presales efforts including proposals, solution design, and estimations. Define hiring plans and lead technical interviews to grow the team. Drive innovation in validation frameworks, debug techniques, and automation infrastructure. Experience Requirements Minimum 10 years in embedded systems and software development. Strong focus on pre-silicon/post-silicon validation , platform bring-up, and hardware-software integration. At least 3 years in a leadership or technical ownership capacity. Prior experience in semiconductor or embedded product engineering services is essential. Technical Expertise Pre-silicon validation (QEMU, emulators, FPGA prototyping) Post-silicon bring-up (BSP, drivers, early diagnostics) Bootloader and OS bring-up (U-Boot, TF-A, Linux, Android, RTOS) SoC microarchitecture, memory hierarchy, interrupt handling Debug/trace tools (JTAG, UART, PCIe, USB, MIPI, Ethernet) Test automation frameworks and HW/SW co-verification High-speed interface validation and compliance testing Programming in C, C++, Python/Perl, Shell scripting Emulation platforms: Cadence Palladium, Synopsys ZeBu, Mentor Veloce Security features: Secure Boot, TEE, power/performance workflows Experience with SoCs from NXP, Intel, AMD, TI, ST, Qualcomm, RISC-V Customer engagement, account management, and presales solutioning Exposure to working with American & European semiconductor clients Desirable / Nice to Have Knowledge of HW/SW co-simulation and virtual platforms Familiarity with lab infrastructure and chipset validation Exposure to ISO/IEC standards and functional safety Experience with AI/ML or DSP accelerators at silicon level Travel Requirements Flexibility to travel globally for client meetings, workshops, and project delivery support alongside sales or delivery teams.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and experienced analog design engineer who thrives on tackling complex technical challenges and is eager to make a tangible impact on next-generation technology. You have an in-depth understanding of mixed-signal and analog circuit design, particularly in high-speed SERDES development. Your background in electrical, electronics, or VLSI engineering has equipped you with a strong foundation in CMOS device physics and nanometer technologies, and you are adept at applying this knowledge to develop innovative solutions. You enjoy collaborating with cross-functional teams, sharing your insights, and learning from peers across geographical boundaries. Your commitment to excellence drives you to ensure your designs not only meet but exceed standards for performance, power, and area optimization. You value clear communication and take pride in documenting your work, presenting your findings, and contributing to a culture of continuous improvement. Whether you are working independently or as part of a global team, you demonstrate initiative, adaptability, and a proactive approach to problem-solving. Your curiosity keeps you at the forefront of industry trends, and you are excited to work in an environment that encourages growth, mentorship, and technical leadership. Above all, you are motivated by the prospect of seeing your designs come to life in products that power the world’s most advanced technologies. What You’ll Be Doing: Designing and developing full-custom analog circuit macros, including analog front-end transceivers, voltage/current-mode drivers, delay-locked loops, phase-locked loops, regulators, equalizers (CTLE, FFE, DFE), impedance calibrators, serializers, deserializers, voltage-controlled oscillators, phase interpolators, bandgap references, and clock data recovery circuits for high-speed PHY IP in advanced CMOS technologies. Ensuring analog sub-block performance adheres to SerDes standards and architectural specifications, with a focus on achieving optimal power, area, and performance targets. Proposing and implementing design and verification strategies using advanced simulation tools to ensure high-quality, robust designs. Overseeing and collaborating on physical layout to minimize the effects of parasitics, device stress, and process variation. Presenting simulation data and design reviews to peers, customers, and cross-functional teams, and incorporating feedback. Documenting design features, test plans, and consulting on electrical characterization for SerDes IP products. Collaborating with diverse teams across different locations, contributing to a culture of technical excellence and innovation. The Impact You Will Have: Accelerate the development of high-performance silicon chips that power tomorrow’s technologies—enabling faster, more efficient data transfer in critical applications. Help Synopsys maintain its leadership in delivering industry-leading SERDES IP for a wide range of protocols (PCIe, Ethernet, SATA, USB, and more). Drive innovation in mixed-signal analog design, directly influencing the capabilities of next-generation SoCs and system solutions. Contribute to reducing customer project schedules by enabling robust, verified IP blocks that integrate seamlessly into customer designs. Enhance the quality, reliability, and performance of Synopsys IP offerings, strengthening our reputation and customer trust. Mentor and uplift peers, sharing knowledge and best practices to foster a high-performing, inclusive engineering culture. What You’ll Need: Bachelor’s (BE) with 3+ years or Master’s (MTech) with 2+ years of relevant experience in mixed-signal/analog custom circuit design, with a degree in Electrical/Electronics/VLSI Engineering or closely related field. Strong expertise in CMOS circuit design fundamentals, device physics, and analog transistor-level circuit design in nanometer technologies. Hands-on experience with multi-Gbps high-speed design and familiarity with electrical specifications of protocols such as PCIe, Ethernet, SATA, and USB. Proficiency in EDA tools for SPICE simulation, static timing analysis (STA), and parasitic extraction, along with a solid understanding of sub-micron design methodologies. Experience in high-speed datapath full-custom design using digital/CMOS logic cells, including clock path optimization and timing verification. Familiarity with ESD/latch-up verification, mixed-signal analog design challenges, and understanding of crosstalk and coupling impacts on timing. Who You Are: Collaborative and open-minded, thriving in a diverse, global team environment. Analytical and detail-oriented, with a strong commitment to quality and continuous improvement. Effective communicator—able to clearly document, present, and discuss complex technical concepts with clarity and confidence. Proactive problem-solver who takes initiative and adapts quickly to new challenges and evolving project requirements. Eager to learn, share knowledge, and mentor others within the team. Passionate about technology and motivated to contribute to industry-defining innovations. The Team You’ll Be A Part Of: You will join our high-performing Analog Design SERDES team, a diverse group of engineers dedicated to developing cutting-edge high-speed analog circuits for SERDES IP. The team is known for its collaborative spirit, technical depth, and commitment to pushing the boundaries of what’s possible in mixed-signal design. You’ll work alongside experienced professionals both locally in Noida and across Synopsys’ global sites, sharing knowledge and driving innovation together. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

You will work in the AMS Verification domain, requiring relevant experience in mixed signal SOCs or subsystems/IPs. Leading a project for AMS requirements is considered a value add. Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools is essential. You should have knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles. Analog circuit basics understanding is necessary, and previous analog design experience would be a plus. You should be familiar with the concepts of behavioral modeling, including digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from a mixed signal perspective is advantageous. Functional knowledge of analog and mixed signal building blocks such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected. Previous experience working on AMS Verification on multiple SOCs or sub-systems is required. Working knowledge of Perl/Skill/Python/Tcl or other scripting relevant languages would be beneficial. You must possess the ability to lead a project team and work collaboratively in a multi-site development environment. Being delivery-oriented, passionate to learn and explore, transparent in communication, and flexible related to project situations is important. A good knowledge of analog and mixed signal electronics, test-plan development, tools, and flows is necessary. You will be responsible for developing and executing top-level test cases, self-checking test benches, and regression suites. Additionally, you will develop and validate high-performance behavior models and verify block-level and chip-level functionality and performance. Being a team player with good communication skills and having previous experience in delivering solutions for a multi-national client is valuable. You should be fluent with Cadence-based flow, creating schematics, Simulator/Netlist options, etc. Ability to extract simulation results, capture them in a document, and present them to the team for peer review is required. Supporting silicon evaluation and comparing measurement results with simulations is part of the role. Having UVM and assertion knowledge would be an advantage.,

As an AMS Verification Engineer, you will be responsible for working on Analog Mixed-Signal (AMS) Verification for SoCs, subsystems, and IPs. Your role will involve hands-on experience with AMS simulation environments using tools such as Cadence, Synopsys, or Mentor. It is essential to have a solid understanding of analog and mixed-signal circuits, including comparators, op-amps, switched-cap circuits, ADCs/DACs, current mirrors, charge pumps, and regulators. Your expertise in Verilog, Verilog-A, Verilog-AMS, and Verilog-D for behavioral modeling will be crucial for block-level and chip-level AMS verification. This includes top-level testbench development, self-checking testbenches, and regression suites. Exposure to SystemVerilog (SV) and UVM from an AMS perspective will be considered a plus. Proficiency in scripting languages such as Python, Perl, TCL, or SKILL for automation is required. You should be fluent with Cadence Virtuoso-based analog design flow, encompassing schematic capture, simulator/netlist configuration, and SPICE simulation. Your ability to extract, analyze, and document simulation results and present findings in technical reviews is highly valued. Furthermore, familiarity with test plan development, AMS modeling, and verification methodologies is essential. You will also be involved in supporting post-silicon validation and correlating measurement data with simulations. As a valued team member, you should be team-oriented, proactive, and able to contribute effectively in a multi-site development environment.,

The role of VLSI Engineer is a full-time on-site position based in Modasa. As a VLSI Engineer, your primary responsibilities will involve the design, development, and testing of VLSI circuits and systems. You will be tasked with creating detailed design specifications, performing schematic capture and layout, conducting simulations, and verifying designs to ensure they meet performance and quality standards. Additionally, you will collaborate with cross-functional teams to ensure the successful integration of VLSI components. To excel in this role, you should possess experience in VLSI design, development, and testing. Proficiency in schematic capture and layout, along with strong skills in simulation and verification of VLSI designs, are essential. Familiarity with VLSI design tools and software such as Cadence and Synopsys is preferred. Excellent problem-solving and analytical abilities will be crucial in successfully carrying out your duties. Moreover, your capacity to work collaboratively with cross-functional teams will be key to achieving project goals. Ideally, you should hold a Bachelor's or Master's degree in Electrical Engineering or a related field. While not mandatory, prior experience in the semiconductor industry would be advantageous in this role. If you are a motivated individual with a passion for VLSI engineering and possess the required qualifications and skills, we encourage you to apply for this exciting opportunity.,

You should possess a B.Tech/M.Tech degree in Electronics and Communication Engineering with 8 to 20 years of experience in physical design of semiconductor chips. The role is based in Hyderabad and follows a general shift schedule with no work from home option. Your responsibilities will include top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks such as timing and functional ECOs, SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. You must have prior experience working on 65nm or lower node designs, implementing advanced low-power techniques like Voltage Islands, Power Gating, and substrate-bias. In this role, you will provide technical guidance and mentorship to physical design engineers, interface with front-end ASIC teams to resolve issues, and focus on low-power design techniques including Voltage Islands, Power Gating, and Substrate-bias. You should have expertise in timing closure on DDR2/DDR3/PCIE interfaces, excellent communication skills, and a strong background in ASIC Physical Design encompassing Floor planning, Place & Route, extraction, IR Drop Analysis, Timing, and Signal Integrity closure. Additionally, you should have extensive experience and detailed knowledge in physical design tools such as Cadence, Synopsys, or Magma, proficiency in scripting languages like PERL and TCL, and a strong skillset in Physical Verification. Familiarity with Static Timing Analysis using Primetime or Primetime-SI is required. Your written and oral communication skills should be excellent, with the ability to clearly document plans and effectively collaborate with cross-functional teams while prioritizing work based on project requirements.,

You are a Senior Physical Design Engineer with at least 6 years of experience, and your primary responsibility will be to lead the physical implementation of advanced semiconductor projects. Your role is crucial in shaping the silicon realization of cutting-edge designs, ensuring successful integration from RTL to tape-out. Your responsibilities include providing technical guidance and mentoring to physical design engineers, interfacing with front-end ASIC teams to resolve issues, and working on low power design techniques such as Voltage Islands, Power Gating, and Substrate-bias. You will also be responsible for timing closure on DDR2/DDR3/PCIE interfaces and have excellent communication skills. Your strong background in ASIC Physical Design, including floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure, will be essential. You should have extensive experience and detailed knowledge in Cadence, Synopsys, or Magma physical Design Tools, as well as expertise in scripting languages like PERL and TCL. Additionally, you should have a strong Physical Verification skill set and experience in Static Timing Analysis using Primetime or Primetime-SI. In terms of required skills, you should be proficient in top-level floor planning, PG Planning, partitioning, placement, timing optimization, SI aware routing, and ECO tasks. Experience with 65nm or lower node designs with advanced low power techniques is necessary. Proficiency in EDA tools for floor planning, place and route, clock tree synthesis, and physical verification is also required. A Bachelors or Masters degree in electronics engineering or a related field is essential. Desired skills include familiarity with EDA tools such as Cadence Innovus, Synopsys ICC, and Mentor Calibre, as well as knowledge of low power design techniques and implementation.,

Requisition #: 16690 Ansys is now a part of Synopsys. Synopsys, Inc. (Nasdaq: SNPS) accelerates technology innovation from silicon to systems. Catalyzing the era of pervasive intelligence, we deliver design solutions, from electronic design automation to silicon IP, to system design and multiphysics simulation and analysis. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. Learn more at www.synopsys.com. Summary / Role Purpose The R&D Engineer II contributes to the development of software products and supporting systems. In this role, the R&D Engineer II will collaborate with a team of expert professionals to understand customer requirements and accomplish development objectives. Key Duties And Responsibilities Performs moderately complex development activities, including the design, implementation, maintenance, testing and documentation of software modules and sub-systems Understands and employs best practices Performs moderately complex bug verification, release testing and beta support for assigned products. Researches problems discovered by QA or product support and develops solutions Understands the marketing requirements for a product, including target environment, performance criteria and competitive issues Works under the general supervision of a development manager Minimum Education/Certification Requirements And Experience BS in Engineering, Computer Science, or related field with 2 years’ experience or MS Working experience with C/C++ coding, data structures and algorithms. Preferred Qualifications And Skills Technical knowledge and experience with computational geometry or mesh generation and. object-oriented design Technical knowledge and experience with scripting languages like Python is a plus. Technical knowledge and experience with parallel programming and GPU is a plus. Experience in a large-scale commercial software development environment Rewards And Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Ansys, part of Synopsys, we want talented people of every background to feel valued and supported to do their best work. We consider all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Category Engineering Hire Type Employee Job ID 12261 Remote Eligible No Date Posted 23/07/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and experienced analog design engineer who thrives on tackling complex technical challenges and is eager to make a tangible impact on next-generation technology. You have an in-depth understanding of mixed-signal and analog circuit design, particularly in high-speed SERDES development. Your background in electrical, electronics, or VLSI engineering has equipped you with a strong foundation in CMOS device physics and nanometer technologies, and you are adept at ing this knowledge to develop innovative solutions. You enjoy collaborating with cross-functional teams, sharing your insights, and learning from peers across geographical boundaries. Your commitment to excellence drives you to ensure your designs not only meet but exceed standards for performance, power, and area optimization. You value clear communication and take pride in documenting your work, presenting your findings, and contributing to a culture of continuous improvement. Whether you are working independently or as part of a global team, you demonstrate initiative, adaptability, and a proactive approach to problem-solving. Your curiosity keeps you at the forefront of industry trends, and you are excited to work in an environment that encourages growth, mentorship, and technical leadership. Above all, you are motivated by the prospect of seeing your designs come to life in products that power the world’s most advanced technologies. What You’ll Be Doing: Designing and developing full-custom analog circuit macros, including analog front-end transceivers, voltage/current-mode drivers, delay-locked loops, phase-locked loops, regulators, equalizers (CTLE, FFE, DFE), impedance calibrators, serializers, deserializers, voltage-controlled oscillators, phase interpolators, bandgap references, and clock data recovery circuits for high-speed PHY IP in advanced CMOS technologies. Ensuring analog sub-block performance adheres to SerDes standards and architectural specifications, with a focus on achieving optimal power, area, and performance targets. Proposing and implementing design and verification strategies using advanced simulation tools to ensure high-quality, robust designs. Overseeing and collaborating on physical layout to minimize the effects of parasitics, device stress, and process variation. Presenting simulation data and design reviews to peers, customers, and cross-functional teams, and incorporating feedback. Documenting design features, test plans, and consulting on electrical characterization for SerDes IP products. Collaborating with diverse teams across different locations, contributing to a culture of technical excellence and innovation. The Impact You Will Have: Accelerate the development of high-performance silicon chips that power tomorrow’s technologies—enabling faster, more efficient data transfer in critical applications. Help Synopsys maintain its leadership in delivering industry-leading SERDES IP for a wide range of protocols (PCIe, Ethernet, SATA, USB, and more). Drive innovation in mixed-signal analog design, directly influencing the capabilities of next-generation SoCs and system solutions. Contribute to reducing customer project schedules by enabling robust, verified IP blocks that integrate seamlessly into customer designs. Enhance the quality, reliability, and performance of Synopsys IP offerings, strengthening our reputation and customer trust. Mentor and uplift peers, sharing knowledge and best practices to foster a high-performing, inclusive engineering culture. What You’ll Need: Bachelor’s (BE) with 3+ years or Master’s (MTech) with 2+ years of relevant experience in mixed-signal/analog custom circuit design, with a degree in Electrical/Electronics/VLSI Engineering or closely related field. Strong expertise in CMOS circuit design fundamentals, device physics, and analog transistor-level circuit design in nanometer technologies. Hands-on experience with multi-Gbps high-speed design and familiarity with electrical specifications of protocols such as PCIe, Ethernet, SATA, and USB. Proficiency in EDA tools for SPICE simulation, static timing analysis (STA), and parasitic extraction, along with a solid understanding of sub-micron design methodologies. Experience in high-speed datapath full-custom design using digital/CMOS logic cells, including clock path optimization and timing verification. Familiarity with ESD/latch-up verification, mixed-signal analog design challenges, and understanding of crosstalk and coupling impacts on timing. Who You Are: Collaborative and open-minded, thriving in a diverse, global team environment. Analytical and detail-oriented, with a strong commitment to quality and continuous improvement. Effective communicator—able to clearly document, present, and discuss complex technical concepts with clarity and confidence. Proactive problem-solver who takes initiative and adapts quickly to new challenges and evolving project requirements. Eager to learn,

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. Our Silicon Design & Verification business leads the industry in enabling customers to design and verify advanced silicon chips—faster and with more reliability. We develop the next-generation processes and models that optimize chips for power, cost, and performance, shaving months off project schedules for our global clientele. We believe in fostering an inclusive and diverse environment where every voice is valued and innovation thrives. You Are: You are a passionate and experienced Analog/Mixed-Signal (A&MS) Circuit Design Engineer with a track record of excellence in high-speed physical interface development. With a deep foundation in CMOS circuit design, device physics, and nanometer technologies, you thrive on solving complex challenges at the intersection of analog and digital domains. You are energized by working on industry-leading projects and are adept at architecting, designing, and validating advanced circuits such as transmitters, receivers, clocking circuits, equalizers, serializers, de-serializers, and analog front ends. Your expertise allows you to optimize for performance, area, and power, and you are comfortable with layout considerations and parasitic optimizations. You value diversity and inclusion, recognizing the strength that comes from varied perspectives and backgrounds. You are ready to contribute to a culture of innovation, respect, and excellence—helping Synopsys remain at the forefront of the smart everything revolution. What You’ll Be Doing: Designing and developing high-speed analog and mixed-signal full-custom circuit macros, including transmitters, receivers, clocking circuits, equalizers, serializers, de-serializers, and analog front ends for PHY IPs in advanced CMOS technologies (planar and finFET). Analyzing and implementing various analog circuit techniques to optimize dynamic/static power, enhance performance, and reduce silicon area. Collaborating with global teams to define micro-architectures from specifications and create robust simulation environments for design verification. Performing transistor-level circuit design, simulation, and troubleshooting in nanometer processes, with a focus on reliability and manufacturability. Working closely with layout engineers to optimize parasitics, ensure design closure, and address layout-dependent effects. Participating in design reviews, providing technical guidance, and mentoring junior engineers within a high-performing, diverse team. Adopting and developing automation and scripting to streamline design and verification flows, leveraging languages such as Verilog-A and others as needed. The Impact You Will Have: Advance the state-of-the-art in high-speed PHY IP development, contributing directly to next-generation technology in AI, IoT, 5G, and automotive industries. Enable Synopsys customers to achieve faster time-to-market with optimized, reliable, and high-performance silicon solutions. Drive innovation in low-power and high-speed circuit design, helping customers meet stringent power and area targets. Enhance Synopsys’ reputation as a global leader in silicon design and verification through technical excellence and customer success. Mentor and elevate the skills of team members, fostering a collaborative and growth-oriented culture. Contribute to a diverse and inclusive workplace, ensuring a wide range of perspectives and ideas inform our solutions. What You’ll Need: BE + 5 years or MTech + 4 years of relevant experience in Electrical/Electronics/VLSI Engineering or closely related field. Strong fundamentals in CMOS circuit design, device physics, and sub-micron/nanometer methodologies. Hands-on experience in analog transistor-level circuit design for high-speed applications (Multi-Gbps, PAM4 SERDES architectures). Proficiency in SPICE simulations, reliability analysis, and optimizing for layout parasitics. Ability to micro-architect circuits from specifications, set up verification environments, and debug complex analog/mixed-signal circuits. Basic proficiency with automation/scripting languages and familiarity with Verilog-A is a plus. Experience collaborating with cross-site, multicultural teams and strong documentation skills. Who You Are: Innovative thinker with a problem-solving mindset and a passion for continuous learning. Collaborative team player who values diversity, inclusion, and open communication. Detail-oriented, quality-focused, and committed to delivering results on time. Strong interpersonal and mentoring skills, able to guide and support less experienced team members. Adaptable and resilient, comfortable working in a fast-paced, dynamic environment. The Team You’ll Be A Part Of: You will join a dynamic, high-performing team dedicated to the design and development of high-speed physical interfaces for advanced semiconductor products. Our team is composed of talented engineers with deep expertise in analog and mixed-signal design, working collaboratively across multiple sites worldwide. We value innovation, knowledge-sharing, and a culture of mutual respect, enabling every team member to grow and contribute to industry-leading solutions. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Job Overview : We are seeking an exceptional Physical Verification Engineer to take a key role in oursemiconductor design team. As a Block/Fullchip/Partition Physical Verification Engineer , you willResponsible for development and implementation of cutting-edge physical verification methodologiesand flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensurethe successful delivery of high-quality designs Responsibilities : Drive physical verification DRC, Antenna, LVS, ERC at cutting edge FinFET technology nodesfor various foundries. Physical verification of a complex SOC/ Cores/ Blocks DRC, LVS, ERC, ESD, DFM, Tape out. Work hands-on to solve critical design and execution issues related to physical verificationand sign-off. Own physical verification and sign-off flows, methodologies and execution of SoC/cores. Good hands on Calibre, Virtuoso etc. Requirements : Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization. Expertise in physical verification of Block/Partition/ Full-chip-level DRC, Experience and understanding of all phases of the IC design process from RTL-GDS2. LVS, ERC, DFM Tape out process on cutting edge nodes, Preferably worked on 3nm/5nm/7nm/12nm/14nm/16nm nodes at the major foundries Experience in debugging LVS issues at chip-level/block level with complex analog-mixed signal IPs Experience with design using low-power implementation (level-shifters, isolation cells, power domain/islands, substrate isolation etc.) Experience in physical verification of I/O Ring, corner cells, seal ring, RDL routing, bumps and other full-chip components Good understanding of CMOS/FinFET process and circuit design, base layer related DRCs, ERC rules, latch-up etc. Experience with ERC rules and ESD rules has an added advantage Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Proven ability to Engineer and mentor junior engineers, fostering their professional growth and development. Preferred qualifications: Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Proven track record with multiple successful final production tape-outs Proven ability to independently deliver results and be able to work hands-on as and guide/help peers to deliver their tasks Be able to work under limited supervision and take complete accountability. Excellent written and verbal communication skills Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration and Physical verification challenges.

We are seeking an experienced and highly skilled Senior SOC Design for Test Engineer with aminimum of 5 years of hands-on experience in SOC Design for Test. As a key member of our team, you will play a pivotal role in ensuring the testability, manufacturability, and quality of our cutting-edge System on Chip designs Key Responsibilities Lead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution coverage, manufacturability, and quality plans. Develop full chip and block level DFT implementation from the DFx Specifications and product coverage, quality, and manufacturability goals. Define and implement Test controllers at top level and block level, fuse controllers, test clocking strategy, chip I/O test strategy and HSIO test strategy. Define JTAG TAP, boundary scan, I/O Test JTAG access, IEEE1687 iJTAG network and instrument design and implementation. Define the Test Interface for each of the P&R IP blocks for Scan, MBIST and other test interfaces. Define hierarchical block isolation, Test clocking and On Chip Clock controllers and reset methodology. Define scan and MBIST timing at the top level and block level timing. Analyse block level RTL or gates to ensure that scalability and coverage is satisfied as per the design goals. Ensure that DFT is provided to fix the DFT violations to ensure that the design goals are meet. Analyse compression requirements for each of the blocks, define Intest and Extest compression requirements and define the requirements for compression engines. Synthesize compression engines for each of the blocks. Create the collaterals for compression for the IPs. Block level scan insertion as well as development of the scan wrappers for the blocks. Do scan insertion on the blocks, analyse scan DRC, implement DFT fixes. Create scan protocol files for designs, create scan inserted netlist, create scan definitions as well as scan definition files for PD. Perform ATPG on the scan inserted netlist, analyse DRC and coverage violations. Deep knowledge of different scan models Stuck-at, transition test, path-delay, bridging, cell aware, small-delay transition, IDDQ test etc. Ability to analyse coverage for each of the model types. Running GLS with or without timing for the scan vectors. Ability to debug the failures and working with timing and PD teams to fix the timing issues. Understanding of pattern delivery to the post-silicon test engineering teams. Delivering to the Test engineering the Test pin muxing and other full chip requirements for the Test Engineering Team. Understanding tester requirements and delivering the patterns in the formats that the tester teams needs. Implement pattern retargeting. Create grey box models for blocks. Coverage analysis of full chip consolidating Intest and Extest patterns. Knowledge of Top level scan architecture and creating flow to create pattern retargeting. Knowledge of Streaming Scan Network and other Top level scan pin sharing and implementing the block to top level pattern generation for this flow. Implementing Memory Testing and MBIST. Knowledge of Memory defect models and test algorithms. Knowledge of memory bit mapping and redundancy analysis. Implementing memory repair and fuse sharing among various memory. Knowledge of LogicBIST with Test point insertion, X-blocking. Full chip DFT delivery for tapeout including but not limited to DFT netlist verification, pattern delivery, Tester requirements. Debug DFT patterns post silicon, ability to analyse chain test patterns for failures, scan pattern failures. Analyse MBIST pattern failures, yield and repair debug. Ability to perform volume diagnostics on the parts to isolate and improve the patterns. Requirements Bachelors degree in computer science, Electrical/Electronics Engineering, or related field. OR masters degree in computer science, Electrical/Electronics Engineering, or related field. OR PhD in Computer Science, Electrical/Electronics Engineering, or related field. 5+ years of hands-on experience in SOC Design for Test. Expertise in DFT tools and flows in scan intertion, ATPG, GLS simulation, diagnosis flows. Prior experience working on IP level and SOC level DFT projects. Proficient in DFT tools from Siemens (Tessent), Synopsys DFTmax, Tetramax, Spyglass DFT advisor, Genius DFT, Modus, VCS, Xcelium etc. Worked in full chip design or complex IP delivery in the area of DFT. Experience in post silicon debug, diagnosis and yield enhancements is a plus.

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill collaborate closely with cross-functional teams to ensure the successful delivery of highquality designs Responsibilities: Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs. Understand Design Architecture and timing requirements Develop timing constraints SDC and validate Work with Physical design to close SDC related timing issues. Analysis of timing from synthesis to verify constraints. Work with architects and logic designers to generate block and full chip timing constraints. Analyse scenarios and margin strategies with Synthesis & Design team. Work on SDC for block, partition, Fullchip such as define constraints, IO budgeting, merging constraints. Work with third party IP, derive timing signoff requirements. Requirements: Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. Total 4+ years of experience in STA, timing closure related work. Hands-on experience in ASIC timing constraints generation and timing closure. Tool Knowledge on Timevision, Fishtail, Genus, Prime Time, Tempus, Tweaker is MUST. Deep understanding and experience in various functional and test modes. Good fundamental on Physical design implementation. Validate timing constraints for Block and Partitions. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization.Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule. Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Ability to work cross-functionally with various teams and be productive under aggressive schedules. Proven ability to lead and mentor junior engineers, fostering their professional growth and development. Preferred Qualifications: Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Has at least worked on full chip STA closure of large size silicon. Tool Knowledge on Fishtail, Timevision and other standard tool for constraint development. Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for STA integration. Familiarity with low-power design techniques and methodologies, such as multivoltage domains and power gating using UPF

We are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs Key Responsibilities Perform Synthesis, floor planning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and area targets. Conduct detailed analysis of timing, power, and area, and drive design optimizations to improve QoR. Block/Partition signoff closure for STA, PV, LEC, IR/EM, CLP very efficiently. Provide technical leadership and guidance to the physical design team, mentoring junior engineers and fostering a culture of excellence. Work closely with RTL design and DFT teams to understand design requirements and constraints, and drive successful tapout of designs. Support and Development of advanced physical design methodologies and flows for complex semiconductor designs. Requirements Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. 4+ years of experience in physical design of ASICs Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics for Synthesis, PnR, Signoff Closure. Extensive experience with timing closure techniques, power optimization. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization. Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule. Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Proven ability to lead and mentor junior engineers, fostering their professional growth and development. Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Expertise in Synthesis that includes details understanding of RTL, Early PnR timing issues, Constraint issue, design issues. Experience in handling Partitions and blocks for size estimation, pin assignment, CTS. Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration. Detailed Knowledge on Clocking methodology and various techniques to improve skew, latency, timing, power. Familiarity with low-power design techniques and methodologies, such as multi-voltage domains and power gating using UPF. Expertise in physical verification, including DRC, Antenna, LVS, PERC, and ERC checks. Expertise in Timing Closure including setup, hold, DRV, SI, Interface issues. Experience with formal verification for RTL to Netlist and Netlist to Netlist. Knowledge of emerging technologies such as machine learning and AI for design automation and optimization.

Job Overview We are seeking an experienced and highly skilled Senior SOC Design Verification Engineer with a minimum of 5 years of hands-on experience in SOC Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System on Chip designs. Job Description Lead and manage SOC Design Verification efforts for complex projects, ensuring the successful execution of verification plans. Develop and implement comprehensive verification strategies, test plans, and test benches for high-speed SOCs, including low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI, and high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR and HBM Conduct Gate-level simulations, and power-aware verification using Xprop and UPF.Collaborate closely with cross-functional teams, architects, designers, and pre/post-silicon verification teams. Analyze and implement System Verilog assertions and coverage (code, toggle, functional). Provide mentorship and technical guidance to junior verification engineers.Manage and lead a dynamic team of verification engineers, fostering a collaborative and innovative work environment. Ensure verification signoff criteria are met and documentation is comprehensive.Demonstrate dedication, hard work, and commitment to achieving project goals and deadlines. Adhere to quality standards, implement good test practices, and contribute to the continuous improvement of verification methodologies. Experience with verification tools from Synopsys and Cadence, including VCS and Xsim. Integration of third-party VIPs (Verification IP) from Synopsys and Cadence. Qualifications Bachelors degree in computer science, Electrical/Electronics Engineering, or related field. ORMasters degree in computer science, Electrical/Electronics Engineering, or related field. ORPhD in Computer Science, Electrical/Electronics Engineering, or related field. 5+ years of hands-on experience in SOC Design Verification. Expertise in UVM (Universal Verification Methodology) and System Verilog. Prior experience working on IP level and SOC level verification projects. Proficient in verification tools such as VCS, Xsim, waveform analyzers, and third-party VIP integration (e.g., Synopsys VIPs and Cadence VIPs). Hands-on experience with UFS (Universal Flash Storage), Ethernet, PCIe, CXL, MIPI protocols.Solid understanding of low-speed peripherals (I2C/I3C, SPI, UART, GPIO, QSPI) and high-speed protocols. Experience in DDR, HBM, Gate-level simulations, and power-aware verification using Xprop and UPF. Proficiency in scripting languages such as shell, Makefile, and Perl. Strong understanding of processor-based SOC verification, including native, Verilog, System Verilog, and UVM mixed environment. C-System Verilog handshake and writing C test cases for bootup verification. Excellent problem-solving, analytical, and debugging skills.

Job Title: RTL Design Engineer Experience: 3–5 Years Company: eInfochips (An Arrow Electronics Company) Location: Ahmedabad/ Noida Job Type: Full-Time Job Description: eInfochips is looking for talented RTL Design Engineers with 3–5 years of experience in digital design. You will be working on IP and SoC-level RTL development for leading semiconductor clients across domains like Automotive, Consumer, Industrial, and AI. Key Responsibilities: RTL design using Verilog/SystemVerilog for IP and SoC subsystems Perform synthesis, linting, CDC/RDC analysis Interface with verification, physical design, and architecture teams Support SoC integration and debug Ensure design quality and timing closure Required Skills: 2+ years of hands-on RTL design experience Strong in digital design concepts (FSMs, pipelining, FIFOs) Proficient with tools like Synopsys Design Compiler, SpyGlass, VCS Experience with standard protocols (AXI, AHB, APB) Basic scripting skills (TCL, Perl, Python) How to Apply: 📩 Send your resume to: Nshalini.singh@einfochips.com

JOB NAME : AMS Verification Engineer (Mandatory to have AMS verification with UVM test : As per market : Hyderabad Please Note : it will be virtual interview, WFO initially later depends on the project and project manager, General Description : The position involves design verification of next generation IPs /SoCs with emphasis on verifying and signing off performance and power along with functionality by developing the needed RNM models . This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies including simulation, GLS . Candidate Will Require Close Interactions With Design, SoC , Validation, Synthesis PD Teams For Design Convergence. Candidate Must Be Able To Take Ownership Of IP/Block/SS To work in AMS Verification domain with UVM test batch relevant experience in mixed signal SOCs or subsystems/IPs. Leading a project for AMS requirements is a value add. Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools. Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. Candidate should be familiar with the concepts of behavioral modeling both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus. Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected. Experience working on AMS Verification on multiple SOCs or sub-systems. Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus. Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment. Delivery oriented, Passionate to learn and explore, Transparent in communication, Flexibility related to project situations. Candidates should have a good knowledge of analog and mixed signal electronics, test-plan development, tools and flows. Develop and execute top-level test cases, self-checking test benches and regressions suites. Developing and validating high-performance behavior models. Verifying of block-level and chip-level functionality and performance. Team player with good communication skills and previous experience in delivering solutions for a multi-national client. Tool suites : Predominantly analog (Cadence Virtuoso). SPICE simulator experience. Fluent with Cadence-based flowCreate schematics, Simulator/Netlist options etc.. Ability to extract simulation results, capture in a document and present to the team for peer review. Supporting silicon evaluation and comparing measurement results with simulations. UVM and assertion knowledge would be an Level : 8-12 years in Industry(3+yrs Requirements : Bachelor or Masters degree in Electrical and/or Computer Qualifications : Proficient in at least one of the following languages : Verilog, System Verilog, Verilog AMS. Strong understanding of analog circuits, digital design processes, and top-level integration. Basic knowledge of PMIC and DC-DC converters. Excellent simulation debugging skills, with the ability to analyze waveforms and identify issues in schematics, models, or RTL. Proficient in Unix environment and shell scripting, with a basic understanding of Qualifications : Mentoring skills. Exceptional problem-solving skills. Good written and oral communication Perks : Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun. Equity Rewards (RSUs). Employee Stock Purchase Plan (ESPP). Insurance plans with Outpatient cover. National Pension Scheme (NPS). Flexible work policy. Childcare support. (ref:hirist.tech)

Greetings from Eximietas Design! We are actively seeking Senior Analog Layout Design Engineers / Leads with a minimum of 5-12 years of experience in the field, preferably with expertise in TSMC 5nm or TSMC 7nm technology nodes. Join our dynamic team at locations in Bengaluru, Vizag, or Hyderabad. As a Senior Analog Layout Design Engineer, you will be responsible for contributing to cutting-edge analog layout design, focusing on aspects such as IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. Your role will involve implementing layouts that adhere to strict design constraints while ensuring high quality and optimal circuit performance. Key Skills & Requirements: - Proficiency in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. - Strong comprehension of how layout impacts circuit performance metrics such as speed and area. - Ability to create layouts that meet rigorous design constraints and uphold quality standards. - Hands-on experience with CADENCE/SYNOPSYS layout tools and workflows. - Familiarity with scripting languages such as PERL/SKILL is considered a plus. - Excellent communication skills with a proven track record of collaborating effectively with cross-functional teams. If this opportunity aligns with your expertise and interests, or if you know someone who would be a suitable fit, please forward your updated resume to maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We are excited to connect with talented engineers who are passionate about pushing the boundaries of analog layout design! Best regards, Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam Email: maruthiprasad.e@eximietas.design Phone: +91 8088969910,

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Developing best-in-class architecture for Analog Mixed Signal IPs and high-speed parallel PHY interface solutions for next generation NAND flash memory controllers in advanced CMOS technology nodes. Interact with cross-functional teams to define requirements/specs, conceive the optimal solution by evaluating architectures, drive implementation, closely work with layout designers in guiding and reviewing the layouts, ensure timely and high-quality deliverables, extend SOC integration support and review and provide support for post-silicon activities from IP characterization to yield improvement and RMA. Provide good technical leadership in problem solving, planning and mentoring junior and senior engineers. Propose innovative design solutions and design methodologies. Fostering innovation culture and developing efficient processes by adopting state-of-the-art technologies. Qualifications Must have Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering Working experience (20+ years) in IO including 5+ years as a project leader Should have architected and lead high speed interface design solutions from specification through Silicon debug and characterization Should have hands-on experience in TX and RX design architectures for high speed applications such as DDR4/DDR5/LPDDR4/LPDDR5 along with timing budget analysis. Should be experienced in high speed design architectures such as SERDES, Equalization schemes Should have hands-on experience in IPs such as SSTL, LVDS, I2C, POD IOs, PVT calibration, HV tolerant and Fail-safe IOs, Crystal oscillator etc. Should have extensive experience in ESD circuits design, Associated ESD guidelines and recommendations in different process nodes, IO and SOC level ESD review and signoff Experience in full custom high speed data path design such as DDR PHY will be of advantage. Conversant with tools such as Cadence Virtuoso/Synopsys custom compiler/Hspice/Spectre/Finesim including statistical simulation methodologies Experience in Mixed-mode simulation and analog/digital co-simulation will be of added advantage. Experience in creating EDA model such as Verilog model, Liberty etc will be of added advantage. Should have deep understanding and working knowledge of CMOS process including FINFET technologies such as 16nm/7nm/5nm and the associated DFM issues. Very analytical in nature and able to work in a multi-disciplinary environment Creative, out-of-the-box thinker with a high level of personal involvement Strong theoretical background with a pragmatic approach. Good verbal and written communication skills and experience working with different geographies. Good mentoring, documentation and presentation skills Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. Our Silicon Design & Verification business leads the industry in enabling customers to design and verify advanced silicon chips—faster and with more reliability. We develop the next-generation processes and models that optimize chips for power, cost, and performance, shaving months off project schedules for our global clientele. We believe in fostering an inclusive and diverse environment where every voice is valued and innovation thrives. You Are: You are a passionate and experienced Analog/Mixed-Signal (A&MS) Circuit Design Engineer with a track record of excellence in high-speed physical interface development. With a deep foundation in CMOS circuit design, device physics, and nanometer technologies, you thrive on solving complex challenges at the intersection of analog and digital domains. You are energized by working on industry-leading projects and are adept at architecting, designing, and validating advanced circuits such as transmitters, receivers, clocking circuits, equalizers, serializers, de-serializers, and analog front ends. Your expertise allows you to optimize for performance, area, and power, and you are comfortable with layout considerations and parasitic optimizations. You value diversity and inclusion, recognizing the strength that comes from varied perspectives and backgrounds. You are ready to contribute to a culture of innovation, respect, and excellence—helping Synopsys remain at the forefront of the smart everything revolution. What You’ll Be Doing: Designing and developing high-speed analog and mixed-signal full-custom circuit macros, including transmitters, receivers, clocking circuits, equalizers, serializers, de-serializers, and analog front ends for PHY IPs in advanced CMOS technologies (planar and finFET). Analyzing and implementing various analog circuit techniques to optimize dynamic/static power, enhance performance, and reduce silicon area. Collaborating with global teams to define micro-architectures from specifications and create robust simulation environments for design verification. Performing transistor-level circuit design, simulation, and troubleshooting in nanometer processes, with a focus on reliability and manufacturability. Working closely with layout engineers to optimize parasitics, ensure design closure, and address layout-dependent effects. Participating in design reviews, providing technical guidance, and mentoring junior engineers within a high-performing, diverse team. Adopting and developing automation and scripting to streamline design and verification flows, leveraging languages such as Verilog-A and others as needed. The Impact You Will Have: Advance the state-of-the-art in high-speed PHY IP development, contributing directly to next-generation technology in AI, IoT, 5G, and automotive industries. Enable Synopsys customers to achieve faster time-to-market with optimized, reliable, and high-performance silicon solutions. Drive innovation in low-power and high-speed circuit design, helping customers meet stringent power and area targets. Enhance Synopsys’ reputation as a global leader in silicon design and verification through technical excellence and customer success. Mentor and elevate the skills of team members, fostering a collaborative and growth-oriented culture. Contribute to a diverse and inclusive workplace, ensuring a wide range of perspectives and ideas inform our solutions. What You’ll Need: BE + 5 years or MTech + 4 years of relevant experience in Electrical/Electronics/VLSI Engineering or closely related field. Strong fundamentals in CMOS circuit design, device physics, and sub-micron/nanometer methodologies. Hands-on experience in analog transistor-level circuit design for high-speed applications (Multi-Gbps, PAM4 SERDES architectures). Proficiency in SPICE simulations, reliability analysis, and optimizing for layout parasitics. Ability to micro-architect circuits from specifications, set up verification environments, and debug complex analog/mixed-signal circuits. Basic proficiency with automation/scripting languages and familiarity with Verilog-A is a plus. Experience collaborating with cross-site, multicultural teams and strong documentation skills. Who You Are: Innovative thinker with a problem-solving mindset and a passion for continuous learning. Collaborative team player who values diversity, inclusion, and open communication. Detail-oriented, quality-focused, and committed to delivering results on time. Strong interpersonal and mentoring skills, able to guide and support less experienced team members. Adaptable and resilient, comfortable working in a fast-paced, dynamic environment. The Team You’ll Be A Part Of: You will join a dynamic, high-performing team dedicated to the design and development of high-speed physical interfaces for advanced semiconductor products. Our team is composed of talented engineers with deep expertise in analog and mixed-signal design, working collaboratively across multiple sites worldwide. We value innovation, knowledge-sharing, and a culture of mutual respect, enabling every team member to grow and contribute to industry-leading solutions. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

We are looking for an experienced Analog Layout Engineer with 8+ years of hands-on experience in full custom layout of analog and mixed-signal blocks. The ideal candidate should have expertise in advanced CMOS technologies and be capable of delivering high-quality layout from specifications to tape-out. Key Responsibilities: Execute full custom layout for analog/mixed-signal blocks (OpAmps, Bandgaps, LDOs, ADCs, etc.) Floorplanning, device matching, parasitic optimization, and electromigration compliance Perform DRC/LVS/ERC checks and work closely with verification teams Collaborate with circuit designers to optimize performance and area Ensure quality layout delivery in accordance with tape-out schedules Support post-layout simulation and debug efforts Requirements: 8+ years of experience in analog/custom layout Strong understanding of matching, shielding, and analog layout best practices Hands-on experience with layout tools (Virtuoso, IC Compiler, Calibre, etc.) Knowledge of various technology nodes (180nm to FinFET) Good communication, teamwork, and problem-solving skills Apply Now! If you meet the above qualifications and are ready to take on this exciting challenge, we would love to hear from you. Share your resumes at info@silcosys.com

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned professional with a deep understanding of Analog and Mixed Signal Circuit Layout. With a minimum of 3 years of experience, you bring a strong background in transistor-level analog and mixed-signal layout design. You possess extensive knowledge in CMOS and FINFET technologies, and your expertise in semiconductor device physics sets you apart. Your problem-solving skills are top-notch, and you are detail-oriented, self-directed, and passionate about learning new techniques. You are adept at communicating effectively with cross-functional teams to ensure successful project execution. You thrive in a dynamic environment and are excited about the opportunity to contribute to cutting-edge technology that drives the future. What You’ll Be Doing: Design and development of transistor-level analog and mixed-signal layout. Device level floorplan, placement, routing, and physical verification. Troubleshoot physical verification issues to achieve clean and desired results. Create and review layout documents to ensure they meet quality standards and are delivered on time. Plan, estimate area/time, schedule, delegate, and execute tasks to meet project milestones in a multi-project environment. Collaborate with cross-functional teams to ensure successful project execution. The Impact You Will Have: You will drive the design and development of high-quality analog and mixed-signal layouts. Your expertise will ensure the successful implementation of CMOS and FINFET technologies. Through effective troubleshooting, you will contribute to achieving clean physical verification results. Your attention to detail will ensure that layout documents meet quality standards and deadlines. By managing project schedules and milestones, you will help deliver projects on time. Your collaboration with cross-functional teams will enhance project success and innovation. What You’ll Need: Bachelor's or Master's degree in Electrical Engineering or a related field. Minimum 3 years of experience in Analog and Mixed Signal Circuit Layout. Proficiency in Analog Layout Flow from device placement to GDS release. Strong knowledge of CMOS and FINFET technologies and semiconductor device physics. Experience with EDA tools for custom mixed-signal layout flows. Understanding of CMOS fabrication technology and deep sub-micron effects on layout. Knowledge of electro-migration, reliability concepts, and ESD/LUP concepts as applied to layout. Passion for learning and exploring new techniques. Who You Are: Detail-oriented and self-directed with excellent problem-solving skills. Strong communication skills for effective collaboration with cross-functional teams. Ability to manage multiple projects and meet deadlines effectively. Innovative thinker with a passion for technological advancement. Team player who thrives in a dynamic and fast-paced environment. The Team You’ll Be A Part Of: You will be part of a highly skilled and dedicated team focused on pushing the boundaries of analog and mixed-signal design. Our team collaborates closely with cross-functional departments to drive innovation and deliver high-performance solutions. We value creativity, teamwork, and a commitment to excellence. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Hyderabad, Telangana, India Category: Engineering Hire Type: Employee Job ID 7482 Date posted 07/23/2025 Alternate Job Titles: Senior Technical Writer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an energetic, experienced, and organized writer passionate about cutting-edge technology. With a keen eye for detail and a knack for making complex topics accessible, you have honed your skills over 3-5 years in the software or hardware industry. Your proficiency with authoring tools like FrameMaker and Oxygen, combined with excellent problem-solving abilities, makes you a standout in your field. You excel in communication, both written and verbal, and thrive in a collaborative environment where you can work independently with minimal supervision. Your dedication to quality and your ability to learn new technologies quickly set you apart. You take pride in your work, care about others, and are committed to doing a good job. Familiarity with semiconductor design flows and tools such as Structured FrameMaker, Oxygen editor, and XML flows is a plus. What You’ll Be Doing: Plan, organize, write, and edit various types of customer documentation. Collaborate with world-class engineers to create essential customer documentation in dynamic formats. Empower customers to design-in and optimize Synopsys products through clear, concise documentation. Translate complex technical information into user-friendly content. Ensure documentation meets industry standards and is easily accessible to global customers. Continuously update and maintain documentation to reflect product updates and new features. The Impact You Will Have: Enhance customer satisfaction by providing clear and comprehensive documentation. Facilitate the adoption and optimization of Synopsys products by global customers. Contribute to the overall success of Synopsys by ensuring high-quality documentation. Support the development of innovative solutions through effective communication. Help maintain Synopsys' reputation as a leader in semiconductor IP and EDA software. Drive continuous improvement in documentation processes and standards. What You’ll Need: Degree or master's in electronics, science, hardware, computing, software, physics, mathematics, or engineering discipline. Other technical disciplines also considered. 3-5 years of technical writing experience in the software or hardware industry. Excellent problem-solving skills and strong logical reasoning. Proficiency with authoring tools such as FrameMaker and Oxygen. Exceptional English writing and speaking skills. Who You Are: Excellent communication and interpersonal skills. Energetic and capable of learning new technologies as necessary. Team player who can work independently with minimal supervision. Detail-oriented and committed to producing high-quality work. Proactive and takes ownership of projects and tasks. The Team You’ll Be A Part Of: You will join a dynamic, inclusive, and diverse team of talented professionals committed to innovation and excellence. Our Technical Publications team works closely with engineers to create documentation that empowers our customers and drives the success of Synopsys products. We value collaboration, creativity, and continuous improvement, and we are dedicated to fostering a supportive and engaging work environment. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Alternate Job Titles: Functional Verification Engineer Pre-Silicon Verification Engineer Digital Design Verification Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a dynamic and enthusiastic individual with a strong drive to learn and excel in the field of digital verification. You have a keen eye for detail and a deep understanding of digital design and hardware description languages (HDL). With your expertise in functional verification, you are eager to contribute to the pre-silicon verification activities for high-speed interface IPs. You possess excellent problem-solving skills and can work effectively in a collaborative environment. Your proactive approach and strong communication skills enable you to work closely with digital designers to achieve desired coverage and ensure the highest quality of IPs. What You’ll Be Doing: Working on functional verification of high-speed serial link PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards. Studying IP/design blocks/firmware specifications and building/updating verification plans and test cases. Building/updating functional verification environments to execute test plans. Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs) as per verification plan needs. Performing simulation, random and direct stimulus development, and coverage review. Working closely with digital designers for debugging and achieving the desired coverage. The Impact You Will Have: Ensuring the accuracy and functionality of high-speed interface IPs, contributing to the development of cutting-edge technology. Enhancing the reliability and performance of Synopsys' products through meticulous verification processes. Driving innovation in the semiconductor industry by verifying complex digital designs. Collaborating with a team of skilled professionals to deliver high-quality IPs that meet industry standards. Improving the efficiency of the verification process through automation and advanced verification methodologies. Contributing to the overall success of Synopsys by ensuring the delivery of robust and reliable IPs to customers. What You’ll Need: B.Tech/M.Tech with 3+ years of relevant experience. Understanding of functional verification flow with awareness of verification tools and methodologies such as VMM, OVM/UVM, and System Verilog. Proficiency in scripting and automation using TCL, PERL, or Python. Strong debug and diagnostic skills. Experience in building and updating functional verification environments. Who You Are: An excellent communicator who can collaborate effectively with cross-functional teams. A proactive problem solver with a keen eye for detail. An enthusiastic learner with a passion for technology and innovation. A team player who thrives in a collaborative environment. A highly organized individual who can manage multiple tasks and priorities effectively. The Team You’ll Be A Part Of: You will be part of a dedicated and innovative team focused on the functional verification of high-speed interface IPs. Our team collaborates closely with digital designers and engineers to ensure the highest quality of IPs. We are committed to continuous learning and development, fostering an environment where creativity and innovation thrive. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.