876 Synopsys Jobs - Page 2

Category Engineering Hire Type Employee Job ID 12379 Remote Eligible No Date Posted 28/07/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and detail-oriented engineer with a drive to deliver high-quality, innovative hardware solutions. You thrive in collaborative, cross-functional environments and are energized by working on world-class microprocessor IP that powers some of the most advanced embedded systems on the planet. With a strong foundation in electronics engineering or computer science, you bring at least five years of hands-on experience in ASIC physical design, particularly in physical verification and IR analysis. Your expertise enables you to navigate complex design flows, and you are keen to expand your knowledge by engaging with the latest industry tools and methodologies. You are comfortable scripting in Unix, Perl, and TCL, and you have a working knowledge of hardware description languages like Verilog or VHDL. You possess excellent written and verbal communication skills, allowing you to work effectively with international teams and assist in customer engagements. Your methodical and analytical mindset helps you troubleshoot and optimize designs for performance, power, and area. Eager to learn, you look forward to being involved in both in-house test chip projects and customer-facing design-ins, gaining exposure to a wide range of applications for Synopsys’ ARC processor IP. You are committed to continuous personal and professional growth, and you value the opportunity to contribute to a team that is shaping the future of microprocessor technology. What You’ll Be Doing: Developing and optimizing physical design implementation flows for ARC family microprocessor IPs, ensuring best-in-class performance and power efficiency. Performing comprehensive physical verification, including LVS, DRC, and IR drop analysis, to ensure first-pass silicon success. Collaborating with cross-functional teams, including logic design, verification, and library development, to drive seamless integration and qualification of IP. Supporting benchmarking, test chip implementation, and qualification activities for new microprocessor IP families. Assisting with customer support, design-ins, and technical sales engagements, providing insights into implementation best practices. Automating and enhancing existing design flows using scripting languages such as Perl and TCL to improve efficiency and reproducibility. Participating in internal knowledge-sharing initiatives and contributing to the continuous improvement of team processes and methodologies. The Impact You Will Have: Enable Synopsys customers to achieve rapid, successful integration of advanced ARC processor IP into their SoC designs. Drive the delivery of highly optimized, silicon-proven IP, reducing time-to-market for embedded and high-performance applications. Enhance the robustness and scalability of Synopsys’ implementation flows, setting industry benchmarks for physical design quality. Support the development and qualification of next-generation microprocessor IP, fueling innovation in diverse application domains. Strengthen customer relationships by providing expert technical guidance and support during pre- and post-sales engagements. Contribute to the continuous improvement of Synopsys’ engineering excellence, maintaining our leadership in silicon design. What You’ll Need: Bachelor’s degree in electronics engineering or computer science (Master’s preferred). Minimum 5 years of hands-on experience in ASIC physical design, with a focus on physical verification and IR analysis. Proficiency in scripting languages such as Unix shell, Perl, and TCL to automate design tasks. Exposure to hardware description languages such as Verilog or VHDL. Strong analytical and troubleshooting skills, with attention to detail in solving complex design challenges. Who You Are: A collaborative team player who communicates effectively with colleagues across the globe. Methodical and analytical, with a passion for continuous learning and improvement. Adaptable and open to new ideas, technologies, and design methodologies. Self-motivated and proactive in identifying and resolving technical issues. Customer-focused, with the ability to translate technical concepts into actionable solutions. The Team You’ll Be A Part Of: You’ll join a diverse, international team of experts dedicated to developing and delivering industry-leading microprocessor IP for the ARC family. The team works at the intersection of hardware design, implementation, and customer enablement, supporting a full suite of Synopsys memory compilers and standard cell libraries. You will collaborate closely with colleagues across logic design, verification, and applications engineering, learning from and contributing to a vibrant culture of innovation, knowledge sharing, and technical excellence. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Job Description HPC is an organization responsible for Renesas' business operations primarily focused on automotive MCUs (Microcontrollers) and SoCs (System-on-Chips). It specializes in high-performance computing technology that supports the evolution of automobiles, providing essential semiconductors for next-generation automotive systems such as advanced driver assistance systems (ADAS), connected cars, EV control, and infotainment. HPC offers diverse roles, including MCU/SoC design and development, marketing, and business management. HPC operates globally, collaborating with locations in Japan, the United States, Europe, China, India, and other countries. We are seeking a highly motivated and experienced Principal SoC/MCU Verification Engineer to join our team. In this role, you will contribute to the verification of complex System-on-Chip (SoC/MCU) designs, ensuring functionality, performance, and quality meet project and customer specifications. This position requires expertise in advanced verification methodologies, formal verification, strong technical leadership, and excellent problem-solving skills. Principal Engineer, DV Job Description We are seeking a highly motivated and experienced Principal SoC/MCU Design Verification Engineer to join our team. In this role, you will contribute to the verification of complex System-on-Chip (SoC/MCU) designs, ensuring functionality, performance, and quality meet project and customer specifications. This position requires expertise in advanced verification methodologies, strong technical leadership, and excellent problem-solving skills. Key Responsibilities Formal Verification Strategy: Define and implement formal verification methodologies for pre-silicon validation. Tool Ownership: Master industry tools (e.g., Cadence JasperGold, Synopsys VC Formal) to prove correctness of RTL designs. Constraint Development: Create assertions (SVA), assumptions, and cover points to model design behavior. Debugging: Root-cause formal failures and collaborate with RTL teams to resolve design flaws. Cross-Team Collaboration: Work with architects, designers, and DV teams to align formal efforts with simulation/emulation. 12+ years of experience required. Soft Skills Demonstrated ability to provide clear and transparent communication within teams and with global customers. Agile mindset to adapt to dynamic project requirements and timelines. Innovative thinker capable of contributing ideas to enhance designs or optimize workflows. Proven ability to manage daily tasks and lead a design team with a sense of ownership and accountability. Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement . Job title Principal Engineer- Design Verification Department Engineering Location Hyderabad Remote No Requisition ID 20021202_2025-06-30

Job Title: Sr. Staff Analog/IO Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned and enthusiastic professional who thrives on solving complex technical challenges and is committed to ongoing learning. You excel in dynamic environments and embrace advanced technologies with curiosity and confidence. With a proven track record in high-speed analog and mixed-signal circuit design, you bring a deep understanding of circuit analysis, semiconductor physics, and signal integrity. As a natural leader, you are adept at guiding and motivating teams, fostering collaboration, and driving projects to successful completion. Your expertise extends to modeling complex, non-linear circuit behavior for stability and jitter analysis, and you are skilled at micro-architecting circuits from initial specifications to final implementation. You are comfortable managing regression analysis and collaborating with design, layout, and ESD teams to resolve challenges and align on requirements. Your approach is detail-oriented and strategic, always seeking ways to optimize power, performance, and area (PPA) in your designs while reducing turnaround times. You value open communication, knowledge sharing, and mentoring, and you are dedicated to staying updated with the latest advancements in analog design. Your passion for technology and innovation inspires those around you, and your commitment to continuous improvement ensures you deliver impactful solutions that shape the future of our industry. What You’ll Be Doing: Collaborating with design, layout, and ESD teams to align requirements and efficiently resolve bottlenecks. Innovating and refining design methodologies to enhance scalability, efficiency, and reliability of analog and mixed-signal circuits. Designing, developing, and verifying high-speed analog and mixed-signal integrated circuits, ensuring they meet stringent performance criteria. Modeling complex and non-linear circuit behaviors to linear models for effective stability and jitter analysis. Performing rigorous circuit simulations and layout verifications to ensure accuracy and optimal performance. Optimizing circuit designs for power, performance, and area (PPA), continuously seeking ways to reduce turnaround time. Contributing to the development and documentation of best practices and methodologies for analog design. The Impact You Will Have: Advance the design and verification of high-speed analog and mixed-signal ICs, enabling next-generation technology solutions. Ensure the accuracy, reliability, and robustness of analog designs through meticulous verification and testing. Collaborate across disciplines to deliver innovative, high-performance products that meet evolving market demands. Continuously improve design methodologies and processes, raising the standard for excellence in analog design. Support the development of industry-leading technologies that power Synopsys’ portfolio and customer success. Drive innovation, efficiency, and quality in all aspects of analog design, reinforcing Synopsys’ leadership in the field. What You’ll Need: Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field. 10+ years of experience in analog circuit design and analysis. Deep expertise in analog circuit design and analysis techniques, including high-speed and mixed-signal environments. Proficiency in modeling complex/non-linear circuit behavior for stability and jitter analysis. Strong understanding of network/transmission line/SI analysis and semiconductor device physics. Demonstrated ability to micro-architect circuits from specifications, focusing on enhancing PPA and reducing turnaround time. Experience with design reliability analysis and modern EDA tools for simulation and verification. Who You Are: A strong leader with excellent communication and mentoring skills. Innovative and committed to continuous improvement. Detail-oriented with a strategic mindset and problem-solving abilities. Collaborative, with the ability to work effectively in a cross-functional team environment. Passionate about technology and eager to work on cutting-edge projects. You are a meticulous and innovative leader who excels in high-speed analog and mixed-signal design. Your ability to communicate effectively and work collaboratively with cross-functional teams makes you an essential team leader. You are passionate about staying current with the latest advancements in analog design and are always looking for ways to improve design methodologies and processes. Your strong technical skills, combined with your problem-solving abilities and attention to detail, enable you to tackle complex challenges and drive innovation at Synopsys. The Team You’ll Be A Part Of: You will join a team of dedicated professionals who are passionate about analog and mixed-signal design. Our team collaborates closely with various business groups to deliver high-performance integrated circuits that meet market demands. We value innovation, collaboration, and continuous learning, and we are committed to making a significant impact on the future of technology. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. If you have the capability to make things happen, drive results, and work with a Yes-if attitude, then Synopsys Inc will provide the right environment for you to prosper.

Work location: Netherlands Sponsorship will be provided. About Us: At Dabster, we specialise in connecting top engineering talent with leading global companies. We are currently seeking an experienced Subsystem/SOC Integration Senior Engineer to join our client's team. Our goal is to deliver world-class recruitment solutions, helping our clients build the future of semiconductor innovation. Who Will You Work With: Our client is a globally recognised leader in semiconductor design and development, with teams based in Sophia Antipolis, France, and Cambridge, UK. You will work alongside industry experts focused on cutting-edge SoC and subsystem integration for next-generation products. About the Role: As a Subsystem/SOC Integration Senior Engineer , you will contribute to IP integration, RTL development, and design reviews as part of complex SoC and subsystem projects. You will support micro-architecture design, manage IP configurations, implement power intent using proprietary flows, and assist with synthesis and verification activities. This is a 6-month B2B contract with strong potential for extension, and the role is fully remote within the EU or UK, with occasional travel required for face-to-face meetings at client sites. Key Responsibilities: Develop and review micro-architecture based on final requirement specifications. Manage and render IP configurations per design requirements. Perform RTL coding and lead design reviews. Integrate IP at subsystem/SoC level in line with micro-architecture specifications. Implement power intent using customer-specific tools and flows. Support trial synthesis, update constraints, and perform LEC (logical equivalency checking). Provide verification and debug support. Preferred Skills: Strong experience in micro-architecture design and RTL coding using SystemVerilog. Proficient with synthesis tools like Design Compiler or Fusion Compiler. Hands-on experience in SDC (Synopsys Design Constraints) development. Ability to debug LEC failures and perform RTL/gate-level debug using tools such as Verdi. Strong analytical and problem-solving skills in IP and SoC design environments.

Sr. Engineer - ASIC Digital Design (Physical Im plementation/D esign/STA, 2+ years of exp) We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performan ce silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled and experienced ASIC Digital Design Engineer passionate about working on the latest processes for STA and physical implementation flows on cutting-edge technology nodes. You thrive in dynamic environments and excel in collaborating with functional teams to optimize and develop IO validation vehicles, Mixed Signal IPs, 3DIO PHYs and UCIe-3D PHY. You have a strong focus on Timing Closure and are adept at defining signoff criteria. Your background includes extensive experience with ASIC design flow, hierarchical physical design strategies, and a deep understanding of sub-micron technology issues. You possess a strong knowledge of timing analysis, constraints management, and various verification strategies, including Primepower-bas ed power analysis. Your scripting skills are excellent, and you are innovative, s elf-motivated, and able to work both independently and as part of a team. Your communication skills, both verbal and written, are outstanding, and you have a desire to understand RTL/Timing signoff criteria. What You’ll Be Doing: Working on new processes for physical implementation flows and cutting-edge technology nodes. Collaborating with functional teams to optimize and develop Qualificaition vehicles and 3D PHYs. Defining signoff criteria with a strong focus on Timing Closure. Maturing the physical implementation guide used for customers and internal hardening teams. Participating in next-generatio n physical design methodology and flow development. Performing physical design i mplementation, including synthesis, floor planning, PG Grid design, PnR, CTS, STA, and power/signal integrity signoff. Evaluating PPA targets (Area/Speed/Po wer) and collaborating with the design team to improve design and constraints. The Impact You Will Have: Ensuring the optimization and successful implementation of cutting-edge technology nodes. Contributing to the development of high-performan ce silicon chips and software content. Enhancing the efficiency and performance of Synopsys’ IPs through rigorous timing closure and signoff criteria. Improving customer satisfaction by maturing physical implementation guides. Supporting the achievement of Synopsys' operational goals through innovative design solutions. What You’ll Need: Extensive experience with ASIC design flow and hierarchical physical design strategies. Strong background in timing analysis, constraints management, and frontend synthesis. Experience with physical-aware synthesis, formality, and various verification strategies. Knowledge of Primepower-bas ed power analysis and clock gating for power reduction. Fair knowledge of FC design planning methodologies, floor planning, and PG Grid creation using Synopsys Tools. Strong physical implementation flow debugging skills and scripting abilities. Who You Are: Innovative, s elf-motivated, and able to work independently or as a team player. Excellent verbal and written communication skills. Strong analytical and problem-solvin g abilities. Passionate about continuous learning and staying updated with the latest technological advancements in ASIC digital design. The Team You’ll Be A Part Of: You will join a highly skilled and collaborative team focused on developing and optimizing physical design flows for cutting-edge technology nodes. The team is dedicated to innovation, continuous improvement, and delivering high-performan ce solutions that meet the evolving needs of our customers. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

The ideal candidate for this role will be an RTL engineer with over 8 years of practical design and verification experience using SystemVerilog UVM and ASIC verification. You should have hands-on experience with Synopsys and/or Cadence simulation tools, as well as proficiency in RTL and possibly Gate level debug. Desirable skills for this position include experience with Synopsys and/or Cadence Synthesis, STA, DFT, Formal Equivalence tools, and familiarity with JIRA. It would be beneficial to have knowledge of scripting languages such as Python or equivalent, understanding of PLLs, and experience with mixed-signal design modelling and debugging. Keywords: UVM, RTL, SystemVerilog, Synthesis, Analog.,

Sr. Engineer - ASIC Digital Design (Physical Implementation/Design/STA, 2+ years of exp) We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled and experienced ASIC Digital Design Engineer passionate about working on the latest processes for STA and physical implementation flows on cutting-edge technology nodes. You thrive in dynamic environments and excel in collaborating with functional teams to optimize and develop IO validation vehicles, Mixed Signal IPs, 3DIO PHYs and UCIe-3D PHY. You have a strong focus on Timing Closure and are adept at defining signoff criteria. Your background includes extensive experience with ASIC design flow, hierarchical physical design strategies, and a deep understanding of sub-micron technology issues. You possess a strong knowledge of timing analysis, constraints management, and various verification strategies, including Primepower-based power analysis. Your scripting skills are excellent, and you are innovative, self-motivated, and able to work both independently and as part of a team. Your communication skills, both verbal and written, are outstanding, and you have a desire to understand RTL/Timing signoff criteria. What You’ll Be Doing: Working on new processes for physical implementation flows and cutting-edge technology nodes. Collaborating with functional teams to optimize and develop Qualificaition vehicles and 3D PHYs. Defining signoff criteria with a strong focus on Timing Closure. Maturing the physical implementation guide used for customers and internal hardening teams. Participating in next-generation physical design methodology and flow development. Performing physical design implementation, including synthesis, floor planning, PG Grid design, PnR, CTS, STA, and power/signal integrity signoff. Evaluating PPA targets (Area/Speed/Power) and collaborating with the design team to improve design and constraints. The Impact You Will Have: Ensuring the optimization and successful implementation of cutting-edge technology nodes. Contributing to the development of high-performance silicon chips and software content. Enhancing the efficiency and performance of Synopsys’ IPs through rigorous timing closure and signoff criteria. Improving customer satisfaction by maturing physical implementation guides. Supporting the achievement of Synopsys' operational goals through innovative design solutions. What You’ll Need: Extensive experience with ASIC design flow and hierarchical physical design strategies. Strong background in timing analysis, constraints management, and frontend synthesis. Experience with physical-aware synthesis, formality, and various verification strategies. Knowledge of Primepower-based power analysis and clock gating for power reduction. Fair knowledge of FC design planning methodologies, floor planning, and PG Grid creation using Synopsys Tools. Strong physical implementation flow debugging skills and scripting abilities. Who You Are: Innovative, self-motivated, and able to work independently or as a team player. Excellent verbal and written communication skills. Strong analytical and problem-solving abilities. Passionate about continuous learning and staying updated with the latest technological advancements in ASIC digital design. The Team You’ll Be A Part Of: You will join a highly skilled and collaborative team focused on developing and optimizing physical design flows for cutting-edge technology nodes. The team is dedicated to innovation, continuous improvement, and delivering high-performance solutions that meet the evolving needs of our customers. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

About Newton School Come be part of a rocket ship that’s creating a massive impact in the world of education! On one side you have over a million college graduates every year with barely 5% employability rates and on the other side, there are thousands of companies struggling to find talent. Newton School aims to bridge this massive gap through its personalized learning platform. We are building an online university and solving the deep problem of the employability of graduates. We have a strong core team consisting of alumni from IITs and IIM, having several years of industry experience in companies like Unacademy, Inmobi, Ola, and Microsoft - among others. On this mission, we are backed by some of the most respected investors around the world, - RTP Global, Nexus Venture Partners, and a slew of angel investors including CRED’s Kunal Shah, Flipkart’s Kalyan Krishnamoorthy, Unacademy and Razorpay founders, Udaan’s Sujeet Kumar among others. About the Role: We are looking for VLSI engineers with a strong foundation in digital systems and computer architecture to take on an academic teaching role. This full-time position is ideal for engineers with hands-on experience in RTL design, processor components, or SoC architecture who are excited to teach how computers are built—from logic gates to microarchitectures. You will lead classroom instruction, mentor student projects, and help shape curriculum at the intersection of digital logic, hardware systems, and architectural design. Key Responsibilities Teach Computer Architecture by drawing from real-world VLSI design experience covering instruction sets, pipelining, memory systems, and microprocessor implementation. Guide students through lab simulations and RTL projects that explore how architectural concepts are implemented in hardware (e.g., datapaths, control units, cache design). Design and evaluate lab work, assessments, and hands-on student projects that simulate industry applications. Mentor and support students in their academic and professional development journeys. Continuously update course content to reflect current industry trends and technologies. Contribute to curriculum development, academic research, and internal learning initiatives. Host technical workshops, design challenges, and guest sessions to extend classroom learning. Collaborate with fellow faculty, industry mentors, and curriculum designers to enrich learning outcomes Must-Have Skills & Qualifications B.Tech / M.Tech / Ph.D. in Computer Engineering, Electronics, Electrical, or a related field. 4 - 7 years of experience working on processor subsystems, SoC integration, RTL for custom compute blocks, or related architecture-level VLSI work. Strong technical command over topics such as: ○ Computer Architecture: Instruction sets, microprocessors, memory hierarchy, pipelining, cache systems. ○ VLSI Design: CMOS circuits, RTL design, ASIC/FPGA flow, timing analysis, layout. Proficiency in tools such as Cadence, ModelSim, Synopsys, Xilinx, Mentor Graphics, etc. Working knowledge of HDL languages (Verilog/VHDL) and scripting (Tcl, Shell, Python). Excellent communication and classroom delivery skills. Demonstrated interest in teaching and mentoring students. Good-to-Have Skills: Prior experience as a faculty member or technical trainer. Familiarity with RISC-V, ARM-based processors, SoC Design, or low-power systems Exposure to DFT, verification methodologies, and EDA flows. Contributions to open-source, academic publications, or online technical content. Comfort with digital tools, LMS platforms, and collaborative teaching formats.

About Newton School Come be part of a rocket ship that’s creating a massive impact in the world of education! On one side you have over a million college graduates every year with barely 5% employability rates and on the other side, there are thousands of companies struggling to find talent. Newton School aims to bridge this massive gap through its personalized learning platform. We are building an online university and solving the deep problem of the employability of graduates.We have a strong core team consisting of alumni from IITs and IIM, having several years of industry experience in companies like Unacademy, Inmobi, Ola, and Microsoft - among others. On this mission, we are backed by some of the most respected investors around the world, - RTP Global, Nexus Venture Partners, and a slew of angel investors including CRED’s Kunal Shah, Flipkart’s Kalyan Krishnamoorthy, Unacademy and Razorpay founders, Udaan’s Sujeet Kumar among others. About the Role: We are looking for VLSI engineers with a strong foundation in digital systems and computer architecture to take on an academic teaching role. This full-time position is ideal for engineers with hands-on experience in RTL design, processor components, or SoC architecture who are excited to teach how computers are built from logic gates to microarchitectures. You will lead classroom instruction, mentor student projects, and help shape curriculum at the intersection of digital logic, hardware systems, and architectural design. Key Responsibilities Teach Computer Architecture by drawing from real-world VLSI design experience covering instruction sets, pipelining, memory systems, and microprocessor implementation. Guide students through lab simulations and RTL projects that explore how architectural concepts are implemented in hardware (e.g., datapaths, control units, cache design). Design and evaluate lab work, assessments, and hands-on student projects that simulate industry applications. Mentor and support students in their academic and professional development journeys. Continuously update course content to reflect current industry trends and technologies. Contribute to curriculum development, academic research, and internal learning initiatives. Host technical workshops, design challenges, and guest sessions to extend classroom learning. Collaborate with fellow faculty, industry mentors, and curriculum designers to enrich learning outcomes Must-Have Skills & Qualifications B.Tech / M.Tech / Ph.D. in Computer Engineering, Electronics, Electrical, or a related field. Experience working on processor subsystems, SoC integration, RTL for custom compute blocks, or related architecture-level VLSI work. Strong technical command over topics such as: ○ Computer Architecture: Instruction sets, microprocessors, memory hierarchy, pipelining, cache systems. ○ VLSI Design: CMOS circuits, RTL design, ASIC/FPGA flow, timing analysis, layout. Proficiency in tools such as Cadence, ModelSim, Synopsys, Xilinx, Mentor Graphics, etc. Working knowledge of HDL languages (Verilog/VHDL) and scripting (Tcl, Shell, Python). Excellent communication and classroom delivery skills. Demonstrated interest in teaching and mentoring students. Good-to-Have Skills: Prior experience as a faculty member or technical trainer. Familiarity with RISC-V, ARM-based processors, SoC Design, or low-power systems Exposure to DFT, verification methodologies, and EDA flows. Contributions to open-source, academic publications, or online technical content. Comfort with digital tools, LMS platforms, and collaborative teaching formats.

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description HPC is an organization responsible for Renesas' business operations primarily focused on automotive MCUs (Microcontrollers) and SoCs (System-on-Chips). It specializes in high-performance computing technology that supports the evolution of automobiles, providing essential semiconductors for next-generation automotive systems such as advanced driver assistance systems (ADAS), connected cars, EV control, and infotainment. HPC offers diverse roles, including MCU/SoC design and development, marketing, and business management. HPC operates globally, collaborating with locations in Japan, the United States, Europe, China, India, and other countries. We are seeking a highly motivated and experienced Staff SoC/MCU Verification Engineer to join our team. In this role, you will contribute to the verification of complex System-on-Chip (SoC/MCU) designs, ensuring functionality, performance, and quality meet project and customer specifications. This position requires expertise in advanced verification methodologies, formal verification, strong technical leadership, and excellent problem-solving skills. Staff Engineer, DV Job Description We are seeking a highly motivated and experienced Staff SoC/MCU Design Verification Engineer to join our team. In this role, you will contribute to the verification of complex System-on-Chip (SoC/MCU) designs, ensuring functionality, performance, and quality meet project and customer specifications. This position requires expertise in advanced verification methodologies, strong technical leadership, and excellent problem-solving skills. Key Responsibilities MCU-Level UVM Verification: Implement modular UVM testbenches for SoC subsystems (e.g., sensor hubs, AI accelerators, communication fabrics). Develop coverage-driven verification plans (functional, code, assertion coverage) aligned with automotive safety and security requirements. Debug complex SoC-level scenarios (e.g., multi-protocol interactions, power-aware verification). Automotive VIP Integration: Integrate and customize 3rd-party VIPs (e.g., Synopsys, Cadence, Mentor) for automotive protocols. Soft Skills Demonstrated ability to provide clear and transparent communication within teams and with global customers. Agile mindset to adapt to dynamic project requirements and timelines. Innovative thinker capable of contributing ideas to enhance designs or optimize workflows. Proven ability to manage daily tasks and lead a design team with a sense of ownership and accountability. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description HPC is an organization responsible for Renesas' business operations primarily focused on automotive MCUs (Microcontrollers) and SoCs (System-on-Chips). It specializes in high-performance computing technology that supports the evolution of automobiles, providing essential semiconductors for next-generation automotive systems such as advanced driver assistance systems (ADAS), connected cars, EV control, and infotainment. HPC offers diverse roles, including MCU/SoC design and development, marketing, and business management. HPC operates globally, collaborating with locations in Japan, the United States, Europe, China, India, and other countries. We are seeking a highly motivated and experienced Principal SoC/MCU Verification Engineer to join our team. In this role, you will contribute to the verification of complex System-on-Chip (SoC/MCU) designs, ensuring functionality, performance, and quality meet project and customer specifications. This position requires expertise in advanced verification methodologies, formal verification, strong technical leadership, and excellent problem-solving skills. Principal Engineer, DV Job Description We are seeking a highly motivated and experienced Principal SoC/MCU Design Verification Engineer to join our team. In this role, you will contribute to the verification of complex System-on-Chip (SoC/MCU) designs, ensuring functionality, performance, and quality meet project and customer specifications. This position requires expertise in advanced verification methodologies, strong technical leadership, and excellent problem-solving skills. Key Responsibilities Formal Verification Strategy: Define and implement formal verification methodologies for pre-silicon validation. Tool Ownership: Master industry tools (e.g., Cadence JasperGold, Synopsys VC Formal) to prove correctness of RTL designs. Constraint Development: Create assertions (SVA), assumptions, and cover points to model design behavior. Debugging: Root-cause formal failures and collaborate with RTL teams to resolve design flaws. Cross-Team Collaboration: Work with architects, designers, and DV teams to align formal efforts with simulation/emulation. 12+ years of experience required. Soft Skills Demonstrated ability to provide clear and transparent communication within teams and with global customers. Agile mindset to adapt to dynamic project requirements and timelines. Innovative thinker capable of contributing ideas to enhance designs or optimize workflows. Proven ability to manage daily tasks and lead a design team with a sense of ownership and accountability. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Category Engineering Hire Type Employee Job ID 12383 Remote Eligible No Date Posted 27/07/2025 Sr. Engineer - ASIC Digital Design (Physical Im plementation/D esign/STA, 2+ years of exp) We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performan ce silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled and experienced ASIC Digital Design Engineer passionate about working on the latest processes for STA and physical implementation flows on cutting-edge technology nodes. You thrive in dynamic environments and excel in collaborating with functional teams to optimize and develop IO validation vehicles, Mixed Signal IPs, 3DIO PHYs and UCIe-3D PHY. You have a strong focus on Timing Closure and are adept at defining signoff criteria. Your background includes extensive experience with ASIC design flow, hierarchical physical design strategies, and a deep understanding of sub-micron technology issues. You possess a strong knowledge of timing analysis, constraints management, and various verification strategies, including Primepower-bas ed power analysis. Your scripting skills are excellent, and you are innovative, s elf-motivated, and able to work both independently and as part of a team. Your communication skills, both verbal and written, are outstanding, and you have a desire to understand RTL/Timing signoff criteria. What You’ll Be Doing: Working on new processes for physical implementation flows and cutting-edge technology nodes. Collaborating with functional teams to optimize and develop Qualificaition vehicles and 3D PHYs. Defining signoff criteria with a strong focus on Timing Closure. Maturing the physical implementation guide used for customers and internal hardening teams. Participating in next-generatio n physical design methodology and flow development. Performing physical design i mplementation, including synthesis, floor planning, PG Grid design, PnR, CTS, STA, and power/signal integrity signoff. Evaluating PPA targets (Area/Speed/Po wer) and collaborating with the design team to improve design and constraints. The Impact You Will Have: Ensuring the optimization and successful implementation of cutting-edge technology nodes. Contributing to the development of high-performan ce silicon chips and software content. Enhancing the efficiency and performance of Synopsys’ IPs through rigorous timing closure and signoff criteria. Improving customer satisfaction by maturing physical implementation guides. Supporting the achievement of Synopsys' operational goals through innovative design solutions. What You’ll Need: Extensive experience with ASIC design flow and hierarchical physical design strategies. Strong background in timing analysis, constraints management, and frontend synthesis. Experience with physical-aware synthesis, formality, and various verification strategies. Knowledge of Primepower-bas ed power analysis and clock gating for power reduction. Fair knowledge of FC design planning methodologies, floor planning, and PG Grid creation using Synopsys Tools. Strong physical implementation flow debugging skills and scripting abilities. Who You Are: Innovative, s elf-motivated, and able to work independently or as a team player. Excellent verbal and written communication skills. Strong analytical and problem-solvin g abilities. Passionate about continuous learning and staying updated with the latest technological advancements in ASIC digital design. The Team You’ll Be A Part Of: You will join a highly skilled and collaborative team focused on developing and optimizing physical design flows for cutting-edge technology nodes. The team is dedicated to innovation, continuous improvement, and delivering high-performan ce solutions that meet the evolving needs of our customers. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Category Information Technology Hire Type Employee Job ID 10130 Remote Eligible No Date Posted 20/07/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a dedicated and enthusiastic individual with a passion for customer support and IT services. With 2-3 years of experience in End-user/Desktop Support within the IT industry, you possess a working knowledge of debugging skills in the Windows environment. Your experience supporting business and connectivity tools, including Microsoft Office, Outlook Exchange email, and Remote Access, has equipped you with the expertise needed to excel in this role. You have a good understanding and experience with Windows Active Directory Services and Exchange email tools, and some knowledge of LAN/WAN, including TCP/IP and DHCP, is preferred. Your ability to communicate clearly in person, in writing, and over the phone, coupled with your patience and politeness in handling customer calls, makes you an ideal candidate. Strong interpersonal skills and attention to detail are among your key strengths. Knowledge of UNIX, technical writing, MAC Operating System, networking, and/or Cisco Unified communications tools is a plus. What You’ll Be Doing: Providing IT support through phone, tickets, and chat to Synopsys workforce around the world. Resolving problems of moderate scope involving laptops/desktops, mobile devices, and applications. Handling common account issues and troubleshooting effectively. Providing ticket status updates to management and end-users. Maintaining effective relationships with end users. Exercising judgment within defined procedures and practices to determine appropriate actions. The Impact You Will Have: Ensuring smooth and efficient IT operations within Synopsys. Enhancing user satisfaction through prompt and effective problem resolution. Contributing to the overall productivity of the workforce by minimizing downtime. Supporting the implementation of IT projects and service delivery initiatives. Maintaining a robust IT knowledge base through content management. Fostering a positive user experience and maintaining high standards of customer service. What You’ll Need: Technical degree or diploma in a related field. 2-3 years of experience in End-user/Desktop Support. Proficiency in debugging within the Windows environment. Experience with Microsoft Office, Outlook Exchange email, and Remote Access. Knowledge of Windows Active Directory Services and Exchange email tools. Who You Are: A strong communicator, both verbally and in writing. Patient and polite in handling customer interactions. Detail-oriented with excellent organizational skills. A team player with strong interpersonal skills. Adaptable and able to exercise sound judgment within defined procedures. The Team You’ll Be A Part Of: Our Global IT Service Desk is the main entry point for all IT Products and Services at Synopsys. The team provides first-level, 24x7 support to some 25,000 employees worldwide via calls, chats, tickets, and walk-ups. With team members located in Mountain View, Shanghai, Hyderabad, Lisbon, Durham, and Bloomington, we participate in projects around service delivery, manage our IT Web knowledge base, and ensure the highest level of customer support. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Hi...! Greetings from Eximietas Design...! We are actively looking to hire Senior Analog Layout Leads/Architects with (TSMC 5nm / TSMC 7nm preferred) 7–15 years of experience to join our growing team. 📍 Locations: Visakhapatnam (Vizag). 📅 Notice Period: 30 days or less preferred. Job Description: We’re seeking highly skilled professionals with a strong background in lower FINFET technology nodes (TSMC 5nm/7nm preferred) to contribute to cutting-edge analog layout design. Key Skills & Requirements: Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. Solid understanding of how layout impacts circuit performance (speed, area, etc.). Ability to implement layouts that meet tight design constraints and deliver high quality. Hands-on experience with CADENCE/SYNOPSYS layout tools and flows. Familiarity with scripting languages (PERL/SKILL) is a plus. Strong communication skills and experience working with cross-functional teams. If this opportunity interests you—or if you know someone suitable—please send your updated resume to: 📧 maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We look forward to connecting with talented engineers passionate about pushing the boundaries of analog layout design! Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam maruthiprasad.e@eximietas.design +91 8088969910.

Hi...! Greetings from Eximietas Design...! We are actively looking to hire Senior Analog Layout Design Engineers / Leads with (TSMC 5nm / TSMC 7nm preferred) 7–15 years of experience to join our growing team. 📍 Locations: Visakhapatnam (Vizag) 📅 Notice Period: 30 days or less preferred. Job Description: We’re seeking highly skilled professionals with a strong background in lower FINFET technology nodes (TSMC 5nm/7nm preferred) to contribute to cutting-edge analog layout design. Key Skills & Requirements: Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. Solid understanding of how layout impacts circuit performance (speed, area, etc.). Ability to implement layouts that meet tight design constraints and deliver high quality. Hands-on experience with CADENCE/SYNOPSYS layout tools and flows. Familiarity with scripting languages (PERL/SKILL) is a plus. Strong communication skills and experience working with cross-functional teams. If this opportunity interests you—or if you know someone suitable—please send your updated resume to: 📧 maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We look forward to connecting with talented engineers passionate about pushing the boundaries of analog layout design! Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam maruthiprasad.e@eximietas.design +91 8088969910.

As a Physical Design Engineer, you will be responsible for top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. You should have experience working on 65nm or lower node designs with advanced low power techniques such as Voltage Islands, Power Gating, and substrate-bias. In this role, you will provide technical guidance and mentoring to Physical Design Engineers and interface with front-end ASIC teams to resolve issues related to low power design techniques. Your responsibilities will also include timing closure on DDR2/DDR3/PCIE interfaces, ensuring excellent communication skills, and possessing a strong background in ASIC Physical Design encompassing Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure. You should have extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools, expertise in scripting languages such as PERL, TCL, strong Physical Verification skill set, and proficiency in Static Timing Analysis in Primetime or Primetime-SI. In addition to technical responsibilities, you should have good written and oral communication skills, the ability to clearly document plans, and the capability to interface with different teams and prioritize work based on project needs. Qualifications: - Experience: 5 to 8 Years Location: - Hyderabad,

Physical Design Engineer (Semiconductor) Role Summary: Responsible for the layout and implementation of digital ICs from RTL to GDSII. Key Responsibilities: Perform floor planning, placement, routing, and timing closure. Optimize power, performance, and area (PPA). Work with verification and DFT teams to ensure design integrity. Use tools like Cadence Innovus , Synopsys ICC2. Generate and validate physical design sign-off reports. Qualifications: Bachelors/ Masters in Electrical or Computer Engineering . Proficiency in physical design flows and EDA tools. Knowledge of STA, IR drop, EM analysis.

Physical Design Engineer (Semiconductor) Role Summary: Responsible for the layout and implementation of digital ICs from RTL to GDSII. Key Responsibilities: Perform floor planning, placement, routing, and timing closure. Optimize power, performance, and area (PPA). Work with verification and DFT teams to ensure design integrity. Use tools like Cadence Innovus, Synopsys ICC2. Generate and validate physical design sign-off reports. Qualifications: Bachelors/Masters in Electrical or Computer Engineering. Proficiency in physical design flows and EDA tools. Knowledge of STA, IR drop, EM analysis.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Job Overview: This position centers on floor-planning expertise at both block and top levels for industry-leading CPU core designs, with a strong emphasis on scalability and achieving aggressive Power, Performance, and Area (PPA) targets. The role involves working on cutting-edge technology nodes and applying advanced physical design techniques to push the boundaries of CPU performance and efficiency. Preferred Qualifications: Masters degree in Electrical/Computer Engineering 8+ years of direct top level floor-planning large and high frequency IP experience In depth end to end experience from RTL2GDS, taping out at least 5 complex designs Direct hands-on experience with bus/pin/repeater planning for entire IP Key responsibilities include: Driving floorplan architecture and optimization in collaboration with PD/RTL teams to maximize PPA Engaging in cross-functional collaboration with Physical design, timing, power, and packaging teams to ensure holistic design convergence Partnering with EDA tool vendors and internal CAD teams to develop and enhance automation flows and methodologies for improved design efficiency Making strategic trade-offs in design decisions to achieve optimal PPA outcomes while maintaining schedule and quality targets End to End Physical verification closure for subsystem. The ideal candidate will have/demonstrate the following: Experience in Physical design which includes floor-planning, placement, clock implementation, routing for complex, big and high speed designs Experience with physical synthesis and implementation tools - Cadence Innovus/Genus and Synopsys Fusion Compiler. Must have good knowledge of static timing analysis, reliability, and power analysis Strong understanding of CMOS circuit design and design techniques to push Power, Performance and Area of complex designs Ability to think outside the box for innovative solutions to improve power and eliminate performance bottlenecks Strong understanding of CPU micro-architecture and collaborate with RTL designers to improve bottlenecks for power and performance Solid working knowledge of scripting skills including tcl, perl or python Excellent communication skills and collaborating in a team environment is a must Excellent understanding of Physical Verification flow with in-depth experience in analyzing and debugging DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck issues. (Mostly Working on Calibre tool) Experience in IO, Bump planning and RDL routing Strategy. Preferred Skills: Clock implementation, power delivery network design choices, process technology, prior experience in flow and methodology development, block closure Close interaction with design and architecture teams to influence scalable floor-plans and optimal bus/pin/repeater planning for entire IP and its sub-blocks Hands on experience with Synthesis, DFT, Place and Route, Timing and Reliability Signoff Hands on experience working with very complex designs that push the envelope of Power, Performance and Area Hands on experience working with sub-micron technology process nodes eg. 5nm, 4nm and below is highly advantageous Hands on experience on Innovus/FC tool based scripting & python/TCL scripting. Prior experience in flow and methodology development is an advantage Excellent debug and analytical skills and demonstrated successes in floor-planning large IP and high frequency designs Ability to drive Physical Implementation teams in Floor-planning and work well in a collaborative environment with multi-disciplined teams Minimum Qualifications: Bachelors degree in Electrical/Computer Engineering 8+ years of direct top level floor-planning large and high frequency IP experience which includes bus/pin/repeater planning at the top level Strong background in VLSI design, physical implementation and scripting Strong background and experience working with industry standard Synthesis and Place and Route tools including Signoff tools Hands on experience taping out designs in sub-micron technology node design Expect strong self-motivation and time management skills Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail or call Qualcomm's toll-free number found . Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact .

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: General Summary: Qualcomm is the world's leading developer of next generation of always on Display technologies and is committed to building a world-class organization that will lead the industry. Be part of the team developing next generation Display subsystems and Display peripherals. The ASIC Systems Architect is responsible for system architecture definition activities supporting a sophisticated multimedia Low Power Display subsystem catering to various market segments like mobile, XR, compute, IOT, Wearables and automotive products. Candidates will be responsible for all aspects of the ASIC hardware architecture definition/validation including the following: Owning end to end system architecture Capturing detailed technology requirements working closely with product, hardware and software engineering teams for deriving subsystem hardware specification. Engage with all stakeholders and collaborate with cross functional teams to define robust architecture Defining architecture validation plans and reviewing development results Optimization and debug via modelling, system simulation and testing across key criteria including power and performance. Collaborating, reviewing and enabling design and system teams to execute independently from the specifications Engage and provide support from Concept to Commercialization, Post-silicon commercialization support and customer engineering documentation Defining and patenting novel architectures that drive industry leadership. Job Function: Oversees hardware architecture for ASIC systems development for a variety of products. Determines architecture design, and validation via system simulation. Defines module interfaces/formats for simulation. Ability to analyze and solve complex problems through various mechanisms. Ability to optimize architecture for Area, Performance and power efficiency. Evaluates all aspects of the HW architecture flow from high-level development to validation and review. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. Uses System tools, such as, MathWorks MATLAB, SIMULINK, VISIO and other toolboxes. Uses language such as HDL, C/C++, System C, Perl, Python. Provides technical expertise for next generation initiatives. Leverages experience in image processing, SoC hardware and computer architecture concepts to develop proposals to address system Display requirements using processor, memory, bus and low-power design techniques. Uses expertise in low-power design methodology, optimization and validation using various CAD tools and design techniques to optimize system power. Leverages experience in digital system performance analysis and systems modelling to ensure performance goals met. Leverages Verilog/VHDL and digital hardware design tools such as Synopsys/Cadence/Mentor ASIC design and simulation tool sets, power analysis and simulation, scripting languages (Python, Perl, TCL, C, etc.) to optimize system. Effectively utilizes advanced problem solving and ASIC engineering practices to resolve complex architecture, design, or verification problems. Writes technical documentation and provides technical expertise for design or project reviews and project meetings. Acts as a tech lead on small to large projects and owns team deliverables of the project Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum Qualifications: Bachelor's degree in, Electronics/Computer Science Engineering, or related field and 7+ years of ASIC design, verification, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, or related work experience. OR PhD in Science, Engineering, or related field. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Synthesis, LEC, Low power checks, Memory BIST insertion, Constraints validation. Development of signoff quality constraints and the development of power intent constraints. May also include running RTL Lint, CLP, MEMBIST, DFT DRC etc. TCL script development in addition to running/analyzing/debugging designs. Hands on with Synopsys DCG/Genus/Fusion Compiler. Hands on with Synopsys Prime Time including constraint development for complex blocks with multiple clock domains. Hands on with Cadence Conformal LEC and Cadence Conformal Low Power including UPF development Experience with either RTL development or Physical Design is also a plus 6+ years experience Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Physical Implementation activities for Sub systems "which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl /Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Bachelor's/ Masters degree in Electrical /Electronic Engineering from reputed institution 2-10 years of experience in Physical Design/Implementation Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Company Description MosChip® Technologies is a publicly traded company specializing in Silicon and Product Engineering solutions with a global presence in Silicon Valley, USA, and India, employing over 1300 engineers. The company offers comprehensive engineering solutions that include silicon design, verification, systems, software, and device engineering, AI/ML solutions, and test automation services. With a strong track record of shipping millions of connectivity ICs and achieving first-time right silicon for over 200+ SoC tape-outs, MosChip® is a reliable partner in the semiconductor industry. Role Description This full-time role is for a Senior Lead STA Engineer specializing in Synthesis, LEC, and CLP. The role is on-site and located in Hyderabad. Daily responsibilities include performing static timing analysis, developing and implementing design constraints, synthesis and timing closure for complex designs, working on logic equivalence checking, and collaborating with cross-functional teams to ensure efficient design implementation and verification processes. Qualifications Expertise in Static Timing Analysis (STA), Synthesis, LEC (Logical Equivalence Checking), and CLP (Clock Power Reduction) Experience with EDA tools such as Synopsys PrimeTime, CADENCE Tempus Proficiency in scripting languages like Perl, TCL, and Shell Strong understanding of digital design fundamentals and VLSI design flow Experience with backend design processes including Physical Design and Signoff flows Excellent communication and teamwork skills Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field Over 5+ years of relevant industry experience is preferred

Job Description We are seeking skilled engineers to join our semiconductor verification and simulation team. This role focuses on functional, gate-level, DFT, and timing simulations, along with validating SoC and IP blocks. Ideal candidates will have hands-on experience with Synopsys EDA tools, and domain-level knowledge of IC packaging and analog layout design will be a strong plus. Roles & Responsibilities Develop and execute RTL test benches using VCS/SystemVerilog/UVM Perform functional and gate-level simulation, debug with Verdi Run DFT pattern simulations, scan insertion validations Conduct Static Timing Analysis (STA) with PrimeTime Execute power-aware and multi-mode multi-corner (MMMC) simulations Validate interfaces considering IC package parasitic (SiP/2.5D/3D-IC understanding is a plus) Collaborate with teams to correlate package- and board-level effects with chip-level behavior Analyze analog layout impact on mixed-signal simulation accuracy (awareness of layout parasitic) Requirements Strong hands-on experience with Synopsys tools: VCS (RTL simulation), Verdi (debug), PrimeTime (timing), TetraMAX/TestMAX (DFT), HSPICE/FineSim (analog simulation exposure is a plus) Familiarity with IC packaging technologies, chip-package co-simulation, and signal/power integrity considerations Understanding of analog layout practices and their influence on simulation/verification Strong scripting skills (TCL, Perl, Python) for automation Excellent debugging, documentation, and communication skills Preferred Qualifications Bachelor’s or Master’s in Electronics, VLSI, or Electrical Engineering & 5-8 Years of Relevant Experience is mandatory Awareness of multi-die, chip let, or 3D IC architectures Basic understanding of EM/IR effects, package substrate modeling, or layout vs schematic (LVS) Strong analytical and collaborative mindset Master in VLSI / Microelectronics Benefits Challenging job within a young and dynamic team. Performance-driven, Career Progression Opportunities. Attractive remuneration package: On par with Industry Standards. Opportunity to join an organization experiencing year on year growth. check(event) ; career-website-detail-template-2 => apply(record.id,meta)" mousedown="lyte-button => check(event)" final-style="background-color:#6875E2;border-color:#6875E2;color:white;" final-class="lyte-button lyteBackgroundColorBtn lyteSuccess" lyte-rendered="">

Job Description We are seeking skilled engineers to join us our semiconductor verification and simulation team. This role focuses on functional, gate-level, DFT, and timing simulations, along with validating SoC and IP blocks. Ideal candidates will have hands-on experience with Synopsys EDA tools, and domain-level knowledge of IC packaging and analog layout design will be a strong plus. Assist in simulation setup and test vector generation Run RTL/gate-level regressions and debug under mentorship Support STA script runs and DFT simulation flows Learn and contribute to interface validation considering package modeling and parasitic Familiarity with analog layout concepts and their impact on verification is a plus Requirements Bachelor’s or Master’s in Electronics, VLSI, or Electrical Engineering Exposure to Synopsys/Cadence tools in academic projects Understanding of RTL simulation, verification methodologies (UVM/OVM), and timing fundamentals Academic knowledge or project experience in IC package modeling or analog layout design is a plus Enthusiastic to learn simulation sign off workflows Preferred Qualifications Awareness of multi-die, chip let, or 3D IC architectures Basic understanding of EM/IR effects, package substrate modeling, or layout vs schematic (LVS) Strong analytical and collaborative mindset Master in VLSI / Microelectronics Benefits Challenging job within a young and dynamic team. Performance-driven, Career Progression Opportunities. Attractive remuneration package: On par with Industry Standards. Opportunity to join an organization experiencing year on year growth. check(event) ; career-website-detail-template-2 => apply(record.id,meta)" mousedown="lyte-button => check(event)" final-style="background-color:#6875E2;border-color:#6875E2;color:white;" final-class="lyte-button lyteBackgroundColorBtn lyteSuccess" lyte-rendered="">