1346 Synopsys Jobs - Page 2

Job Requirements Job Description Job Title: Senior Gate-Level Simulation (GLS) Verification Engineer Location: Bangalore, Karnataka, India Team: SoC Design Verification / Silicon Sign-off Position Summary We are seeking a highly skilled and meticulous Gate-Level Simulation (GLS) Verification Engineer to serve as the last line of defense before silicon tape-out . In this critical role, you will be responsible for verifying the post-synthesis, final netlist of our complex SoCs, ensuring that the design's functionality remains correct after synthesis, placement, and routing. You will hunt down the most subtle and challenging bugs related to timing, power, and reset that are invisible at the RTL...

OUR STORY At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today. When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50,000+, diverse and dedicated creators & makers of technology around the world! Developing technologies takes more than talent: it takes amazing people who understands collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation – whilst unlocking your own ...

OUR STORY At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today. When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50,000+, diverse and dedicated creators & makers of technology around the world! Developing technologies takes more than talent: it takes amazing people who understands collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation – whilst unlocking your own ...

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SOC Verification Lead The Role As a member of the Radeon Technologies Group, you will help ...

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SENIOR SILICON DESIGN ENGINEER The Role The position will involve working with a very exper...

Principal Verification Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: A highly-skilled ASIC Digital Verification Engineer with a passion for developing functional verification solutions for RTL based IP Cores. You are experienced in handling complex protocols and thrive in a collaborative international environment. Wi...

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ The Role We are looking for an experienced engineer to join the SOC Power Modeling team in ...

Physical Design Lead Location: Bangalore We are a consulting company that was founded in 2015 by a group of semiconductor professionals. Since then, the company has provided design services to several companies in the semiconductor industry through continuous service partnerships. We are a fast-growing company with a deep focus on getting excellent talent from the industry as well as picking exceptional talent from the academics. Our unique and transparent work culture has helped us to retain the best talent and we collectively deliver high quality design services. Our team has a vast experience, and we can serve our clients on various services like Physical Design, Full Custom Analog and Di...

Principal IP/RTL Design Engineer for TPU / GPU Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. Position Overview Seeking an IP/RTL Design Engineer with 5+ years of experience to design IP/RTL for TPUs, focusing on high-performance matrix multiplication, low-latency interconnects, and power-efficient AI acceleration. Key Responsibilities Design IP blocks for TPU cores, including systolic arrays, vector units, and memory subsystems. Develop Verilog/SystemVerilog RTL for performance, timing, and...

Baya Systems is seeking an experienced Formal Verification specialist to join the DV team in Bengaluru. This position is full onsite in the Whitefield office. Overall, we are looking for at least 6/7 years of industry experience. Develop detailed formal verification (FV) test plans based on design specifications and collaborate with design teams to refine micro-architecture specifications. Identify key logic components and critical micro-architectural properties essential for ensuring design correctness. Implement formal verification models, abstractions, assertions, and utilize assertion-based model checking to detect corner-case bugs. Apply complexity reduction techniques using industry-st...

IP/RTL Design Architect for GPU Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. Position Overview Seeking an IP/RTL Design Engineer with 8+ years of experience to design IP/RTL for GPUs/TPUs, focusing on high-performance matrix multiplication, low-latency interconnects, and power-efficient AI acceleration. Key Responsibilities Design IP blocks for TPU cores, including systolic arrays, vector units, and memory subsystems. Develop Verilog/SystemVerilog RTL for performance, timing, and area optimization. Im...

Job Description Arm’s Solutions group DFT team implements DFT for test-chips and hard-macros to prove Arm's soft IP power, performance, area, and functionality within the context of a SoC using the latest DFT techniques and process technologies. We closely collaborate with RTL, Verification, Physical Implementation, and Test engineering teams throughout the life cycle of a project, from an early investigation stage all the way through tape-out and silicon test/characterization on ATE. Responsibilities Architect, Implement, and validate innovative DFT techniques on test-chips and hard-macros. Insert DFT logic into SoC-style designs at the RTL level and at the Synthesis gate level, validate al...

Job Description Job Responsibilities Responsible for the Unit verification of AUTOSAR based Simulink, TargetLink models developed as per the MAAB guidelines with good software engineering practices. Responsible for Requirement Analysis. Responsible for Test Specifications, Code Coverage, Model Quality and Model Validation (MIL, SIL) to ensure that developed model is bug-free and adheres to defined Test strategy. Key Skills Good experience in automotive Model Based development activities including model-based testing using tools like Synopsys TPT and auto-code generation using Matlab, Simulink, Stateflow and TargetLink. Good understanding of AUTOSAR architecture and the AUTOSAR based model de...

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled engineer with 6-10 years of experience, passionate about developing cutting-edge emulation solutions for industry-standard protocols such as PCIe, CXL, and UCIe. You possess a strong background in software development using C/C++ and synthesizable RTL deve...

Job Title : DFT Engineer Job Description Responsibilities : Develop and implement DFT architectures including scan insertion, ATPG, memory BIST, and boundary scan. Generate and validate ATPG patterns for stuck-at, transition delay, and other fault models. Perform memory BIST insertion, simulation, and verification. Work with physical design team to resolve DFT-related issues such as routing congestion and timing violations. Develop and maintain DFT scripts and flows. Participate in silicon bring-up and debug. Collaborate with design and verification teams to ensure DFT requirements are met. Document DFT specifications and implementation details. Evaluate and improve DFT methodologies. Mentor...

Role Overview: As a Hardware Engineering Intern at Google, you will be part of a team shaping the future of Google Cloud Silicon, including TPUs, Arm-based servers, and network products. You will collaborate with hardware and software architects and designers to architect, model, analyze, define, and design next-generation Cloud Silicon. Your responsibilities will be dynamic and multi-faceted, focusing on product definition, design, and implementation. You will work closely with Engineering teams to achieve the optimal balance between performance, power, features, schedule, and cost. Key Responsibilities: - Work with hardware and software architects and designers to architect, model, analyze...

He/She should be able to do block level / top-level floor planning, PG Planning, partitioning (for hierarchical designs) , placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks and be able to fix the violations . S hould have worked on 4 5nm , 28nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design eng inee rs. Interface with front-end ASIC teams to resolve issues. Excellent comm...

Senior Engineer — HPC (Semiconductor) Location: Remote Employment Type: Full-time Role Summary We are looking for an experienced HPC Engineer with a strong background in semiconductor design environments . The role involves integrating and optimizing EDA toolchains (Synopsys, Cadence, Mentor Graphics) and OPC flows on cloud and on-prem HPC clusters. You will be responsible for designing, running, and tuning large-scale chip design workloads to achieve maximum performance, scalability, and cost efficiency. Key Responsibilities Integrate and validate EDA tools (Synopsys, Cadence, Mentor Graphics) and OPC pipelines on HPC clusters or cloud environments. Design and implement job scheduling and r...

Senior Engineer — HPC (Semiconductor) Location: Remote Employment Type: Full-time Role Summary We are looking for an experienced HPC Engineer with a strong background in semiconductor design environments . The role involves integrating and optimizing EDA toolchains (Synopsys, Cadence, Mentor Graphics) and OPC flows on cloud and on-prem HPC clusters. You will be responsible for designing, running, and tuning large-scale chip design workloads to achieve maximum performance, scalability, and cost efficiency. Key Responsibilities Integrate and validate EDA tools (Synopsys, Cadence, Mentor Graphics) and OPC pipelines on HPC clusters or cloud environments. Design and implement job scheduling and r...

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and detail-oriented analog/mixed-signal engineer driven by a desire to create world-class solutions that enable the next generation of smart, connected devices. You thrive in fast-paced, collaborative environments and are excited by the challenges of high-spee...

SKILLS AND EXPERIENCE REQUIREMENTS: • Bachelor's degree in Electrical or Computer Engineering and 4+ years STA (Timing, Constrains)/CAD experience or Master's degree and 2+ years' experience • Excellent communication and problem-solving skills • Excellent UNIX and scripting programming skills (Perl, Python and/or TCL) • Strong understanding of digital circuits • Experience with flow automation • Expert knowledge of at least one EDA timing and constraints tool (Cadence Tempus, Synopsys PrimeTime) • Experience with version control software (e.g. perforce, git) • Highly motivated, self-starter with good interpersonal skills

Key Responsibilities Expertise in PDK enablement and library validation/automation. Hands-on experience with LVS/Parasitic extraction/standard cell characterization flows and methodologies Design/System level experience with DTCO and PPA analysis Hands-on expertise in TCL, Python, make and shell scripting Broad understanding of system design (product architecture, packaging, SRAM, DRAM, etc.) is a plus Strong understanding of the RTL2GDS concepts and methodology and experience with Synopsys/Cadence physical design tools (Fusion Compiler/Innovus) Knowledge of standard cell architecture and design tradeoffs with respect to PPA Proactively identify and act on new trends or developments in futur...

Physical Deisgn Lead Location: Bangalore / Hyderabad / Pune Experience - 8+ YoE In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl. Must have hands-on experience on Synopsys/Cadence tools. (Innovus, ICC2, Primetime, PT-PX, Calibre). Well versed with timing constraints, STA and timing closure. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology no...

Role Description: This is a full-time on-site role for a Senior Lead Physical Design Engineer based in Hyderabad. The Senior Physical Design Engineer will be responsible for tasks related to physical design, physical verification, logic design, circuit design, and RTL design in the development of silicon products. Qualifications: He/She should be able to do block level PNR including PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. Minimum of 7-15 years of exper...

About The Role Job Responsibilities Responsible for the Unit verification of AUTOSAR based Simulink, TargetLink models developed as per the MAAB guidelines with good software engineering practices. Responsible for Requirement Analysis. Responsible for Test Specifications, Code Coverage, Model Quality and Model Validation (MIL, SIL) to ensure that developed model is bug-free and adheres to defined Test strategy. Key Skills Good experience in automotive Model Based development activities including model-based testing using tools like Synopsys TPT and auto-code generation using Matlab, Simulink, Stateflow and TargetLink . Good understanding of AUTOSAR architecture and the AUTOSAR based model de...