886 Synopsys Jobs - Page 7

You will be responsible for executing customer projects independently with minimum supervision, guiding team members technically in various fields of VLSI Frontend Backend or Analog design. As an individual contributor, you will take ownership of tasks/modules such as RTL Design, Module Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, Signoff, etc., leading the team to achieve results. Your responsibilities will include completing assigned tasks successfully and on-time within the defined domain(s), anticipating, diagnosing, and resolving problems, coordinating with cross-functional teams as necessary, delivering on-time quality work approved by the project manager and client, automating design tasks flows, writing scripts to generate reports, and coming up with innovative ideas to reduce design cycle time and cost accepted by UST Manager and Client. Additionally, you will be expected to write papers, file patents, and devise new design approaches. Your performance will be measured based on the quality of deliverables, timely delivery, reduction in cycle time and cost, number of papers published, number of patents filed, and number of trainings presented to the team. You will be expected to ensure zero bugs in the design/circuit design, deliver clean design/modules for ease of integration, meet functional specifications/design guidelines without deviation, and document tasks and work performed. Furthermore, you will be responsible for meeting project timelines, facilitating other team members" progress by delivering intermediate tasks on time, and seeking help and support in case of any delays. Your role will also involve active participation in team work, supporting team members as needed, anticipating when support may be required, and being able to explain project tasks and support delivery to junior team members. Your creativity and innovation will be showcased through tasks such as automating processes to save design cycle time, participating in technical discussions, training forums, white paper or patent filings, and contributing to technical discussions. Your skill set should include proficiency in languages and programming skills such as System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, Makefile, Spice, and familiarity with EDA Tools like Cadence, Synopsys, Mentor tool sets, and various simulators. You should have strong technical knowledge in IP Spec Architecture Design, Micro Architecture, Bus Protocols, Physical Design, Circuit Design, Analog Layout, Synthesis, DFT, Floorplan, Clocks, P&R, STA, Extraction, Physical Verification, Soft/Hard/Mixed Signal IP Design, and Processor Hardening. Additionally, you should possess communication skills, analytical reasoning, problem-solving skills, and the ability to interact effectively with team members and clients. Your knowledge and experience should reflect leadership and execution of projects in areas such as RTL Design, Verification, DFT, Physical Design, STA, PV, Circuit Design, Analog Layout, and understanding of design flow and methodologies. Independent ownership of circuit blocks, clear communication, diligent documentation, and being a good team player are essential attributes for this role. Overall, your role will involve circuit design and verification of Analog modules in TSMC FinFet technologies, developing circuit architecture, optimizing designs, verifying functionality, performance, and power, as well as guiding layout engineers. Strong problem-solving skills, results orientation, attention to detail, and effective communication will be key to your success in this position.,

We Are: Drive technology innovations that shape the way we live and connect. Our technology drives the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life. From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world. Apprenticeship Experience: At Synopsys, apprentices dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide—and having fun in the process! You'll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path. Join us and start shaping your future today! Mission Statement: Our mission is to fuel today’s innovations and spark tomorrow’s creativity. Together, we embrace a growth mindset, empower one another, and collaborate to achieve our shared goals. Every day, we live by our values of Integrity, Excellence, Leadership, and Passion, fostering an inclusive culture where everyone can thrive—both at work and beyond. What You’ll Be Doing: Troubleshooting software programs. Managing R&D regressions. Creating validation suites for feature enhancements. Learning and exploring new technologies. Networking with internal and external personnel on assigned tasks. What You’ll Need: Should be a fresh graduate engineer in Computer Science or Electronics (2025). Knowledge of coding (C/C++) and scripting (Perl, Python). Understanding of Data Structures and Basic Operating Systems Concepts. Knowledge of Verilog/VHDL and EDA tools is a plus. Key Program Facts: Program Length: 12 months Location: Noida, India Working Model: In-office Full-Time/Part-Time: Full-time Start Date: Aug/Sep 2025 Equal Opportunity Statement: Synopsys is committed to creating an inclusive workplace and is an equal opportunity employer. We welcome all qualified applicants to apply, regardless of age, color, family or medical leave, gender identity or expression, marital status, disability, race and ethnicity, religion, sexual orientation, or any other characteristic protected by local laws. If you need assistance or a reasonable accommodation during the application process, please reach out to us.

SENIOR PHYSICAL DESIGN ENGINEER SmartSoC is looking for smart and enterprising Physical Designer Engineers to come to join us and get an opportunity to do some cutting-edge work and also work in a great environment where work is Always Fun and Exciting. This role will involve Physical design at the block and chip level of complex designs in the latest technologies. Desired Skills and Experience- 3 – 10 years relevant experience Excellent hands-on P&R skills with expert knowledge in ICC/Innovus Expert knowledge in all aspects of PD from Synthesis to GDSII, Strong background of Floor planning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing and Signal Integrity closure Experience at taping out multiple chips, strong experience at top level at latest technology nodes Job Category VLSI (Silicon engineering) Job Location IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia Singapore

Analog Layout Engineer Experience3 to 5 Years QualificationB.E / B. Tech / M.E / M. Tech ESSENTIAL DUTIES AND RESPONSIBILITIES: Candidate should have a strong knowledge on devices and process/fabrication technology. Should have work experience in 7nm, 10nm, 14nm, 16nm etc Good understating of Deep Submicron issues and layout techniques. Expertise on matching, parasitic reduction, ESD, DFM etc. Proficiency in use of below EDA tools for full custom layout and post-layout verification DRC/LVS/DFM etc. Cadence Virtuoso Layout editor (L/XL/GXL) Verification toolsAssura/PVS/Calibre/ Hercules Preferred Skills: Scripting Knowledge of perl/shell/skill are highly preferred Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas

Lead Analog Layout Engineer Experience8 to 10 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Candidate should have a strong knowledge on devices and process/fabrication technology. Should have work experience in 7nm, 10nm, 14nm, 16nm etc Good understating of Deep Submicron issues and layout techniques. Expertise on matching, parasitic reduction, ESD, DFM etc. Proficiency in use of below EDA tools for full custom layout and post-layout verification DRC/LVS/DFM etc. Cadence Virtuoso Layout editor (L/XL/GXL) Verification toolsAssura/PVS/Calibre/ Hercules Ability to handle a team Preferred Skills: Scripting Knowledge of perl/shell/skill are highly preferred Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas

Physical Design Engineer Experience 4-10 yrs Job Overview: Strong background of ASIC Physical DesignFloor planning, P&R, Extraction, IR Drop Analysis, Static Timing and Signal Integrity.. Hands-on experience on technology nodes like 5nm,7nm, 14nm, 10nm. Good knowledge of EDA tools from Synopsys, Cadence and Mentor Hands-on experience in floor planning, placement optimizations, CTS and routing. Hands-on experience in cadence or Synopsys tool (Encounter, ICC, PT/PTSI, TEMPUS, DC, RC, VOLTAS) Job Category VLSI (Silicon engineering) Job Location IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida

We are seeking a highly skilled and experienced Lead Verification Engineer with expertise in USB/LPDDR and a strong knowledge of Cadence VIP. The ideal candidate will have a deep understanding of low-power design and verification techniques. Responsibilities: Develop and execute comprehensive verification strategies for USB/LPDDR subsystem designs, considering low-power design requirements. Collaborate with cross-functional teams to define verification goals and ensure alignment with project objectives. Design and implement reusable, scalable, and efficient verification testbenches using SystemVerilog/UVM or C based . Leverage Cadence VIP and other verification IPs to accelerate the verification process. Low-Power Design VerificationApply expertise in low-power design and verification techniques to ensure accurate and reliable verification of power management features, including power states, power domains, and power-aware verification methodologies. : Extensive experience (8+ years) in verification. Strong knowledge of Cadence VIP and verification methodologies (SystemVerilog/UVM). Proficiency in low-power design techniques and power-aware verification methodologies. Hands-on experience with industry-standard simulation and verification tools (e.g., Cadence Incisive, Synopsys VCS, Mentor Questa). Solid understanding of verification languages (SystemVerilog, VHDL) and scripting languages (Perl, Python, TCL). Familiarity with industry standards and protocols related to USB (USB 2.0, USB 3.x) and LPDDR (LPDDR4, LPDDR5). Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Job Location: Bengaluru (BLR) and Hyderabad (HYD) Experience: 7 to 20 years : We are seeking a highly skilled and experienced RTL Design Engineer with a strong knowledge of ARM Micro Architecture to join our team. In this role, you will play a key role in the development of complex digital designs and contribute to the success of our cutting-edge projects. The ideal candidate will have a proven track record in RTL design and a deep understanding of ARM Micro Architecture. Key Responsibilities: Collaborate with cross-functional teams to define and develop RTL designs for advanced microprocessor-based projects. Design, implement, and verify digital logic blocks and modules in accordance with project specifications and quality standards. Utilize your expertise in ARM Micro Architecture to optimize and enhance design efficiency. Perform RTL simulations and conduct thorough functional and timing analysis. Identify and resolve design issues, ensuring the delivery of high-quality RTL designs. Stay up-to-date with industry trends and emerging technologies to continually improve design methodologies. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience as an RTL Design Engineer with 7 to 20 years of relevant work experience. Strong knowledge of ARM Micro Architecture and its application in RTL design. Proficiency in RTL design tools and methodologies. Experience with simulation and verification tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS). Excellent problem-solving skills and attention to detail. Effective communication and collaboration skills. Ability to work effectively in a dynamic and fast-paced environment. If you are a highly motivated and experienced RTL Design Engineer with a passion for innovation and a strong background in ARM Micro Architecture, we encourage you to apply for this exciting opportunity. Join our team and contribute to the development of cutting-edge technology solutions. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore IndiaHyderabad

6 - 10 Years 1 Opening Bangalore Role description Job Title: Software Engineer – Data Migration & Configuration Tools Specialist Experience: 7–10 Years (Minimum 5 Years Relevant Experience) Location Preference: Bangalore (First Preference), Hyderabad, Mumbai, Kolkata Work Mode: Hybrid Work Timing: General Shift Employment Type: Full-Time Job Summary: We are hiring a seasoned Software Engineer with 7–10 years of experience, specializing in engineering software tools , data migration , and configuration management . This role involves working with enterprise-grade platforms such as IBM ClearCase , DOORS/DOORS-NG , and Code Collaborator , with additional exposure to software quality and lifecycle management tools. The ideal candidate will have strong experience in software engineering workflows , version control, tooling integration, and migrating or managing legacy engineering data within large, complex environments. Key Responsibilities: Lead and support software tool integration and data migration efforts for engineering applications. Configure and maintain tools supporting version control, requirements management, and code collaboration. Collaborate with engineering, DevOps, and QA teams to ensure smooth toolchain operations and updates. Manage the migration of legacy data into modern systems and ensure tool interoperability. Establish and maintain best practices for software configuration and engineering data lifecycle. Provide end-user support, documentation, and training as needed. Stay up to date on emerging tools and practices in software engineering infrastructure. Primary Skills (At least one required): IBM ClearCase – Configuration management DOORS / DOORS-NG (ELM) – Requirements management Code Collaborator – Peer code review system Unity Hon Standard Instance – Software build and integration tooling Secondary Skills (Preferred/Added Advantage): Familiarity with any of the following tools is a strong plus: JIRA , Miro , Confluence – Project and task management tools Synopsys Coverity , BlackDuck Hub , SonarQube – Static code analysis and security SD Elements , IBM ClearQuest , Octopus Deploy – SDLC tools and deployment JFrog Artifactory , Ansible Tower , Bamboo – DevOps and artifact management GitHub Copilot – AI development assistance Capital Planning System (CPS) , STORES Requisition System , IT PPM – Enterprise resource and project portfolio management AERO TechPubs Publishing – Technical publishing system CEAL – Engineering automation toolset (if applicable) Required Qualifications: Bachelor's or Master's degree in Computer Science , Engineering , or a related technical field. 7–10 years of total experience with minimum 5 years in software engineering and tool integration . Proven experience in data migration , version control systems , and engineering software toolchains . Strong problem-solving, communication, and analytical skills. Experience working in hybrid environments with distributed teams. Skills Software Engineering,Data Migration,Elm,IBM Clearcase About UST UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.

Title: Physical Design Lead (PnR, STA) About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com . Job Summary The individual will reports into the Design Methodology group and will be part of a team that is responsible for the creation of Design Methodology solutions for a wide variety of Technology nodes. Your role is focused on the development of Digital design enablement collateral to help GLOBALFOUNDRIES customers adopt the most advanced silicon technologies (12/14/22/28/40/55). Specific Responsibilities RTL2GDS flow creation and qualification for Synthesis, Place and Route, Extraction, Timing and Physical Verification Will be closely collaborating with EDA vendors and PDK to define, implement, customize, and qualify digital design flows Uses TCL, Python, Pandas and Google APIs to create automation for flow regressions, to collect and compare flow errors, warnings and key design metrics to ensure good quality PDK release and released flow backward compatibility to PDK Use reference flows to perform cross tool and PDK PPA benchmarking Define and generate design testcases to target and measure specific aspects of GLOBALFOUNDRIES PDK and technology changes Work independently in an international team, to drive project definition, execution, and delivery Perform all activities and responsibilities in safe and responsible manner and support all Environmental, Health, Safety, Security requirements and programs Required Qualifications Very good understanding of process technology, digital design, and digital implementation and analysis EDA tools and flows. Deep hands-on experience with digital implementation tools and flows (i.e. Synopsys ICC/ICC2, Cadence EDI/INNOVUS, or Mentor OlympusSoC) including RTL synthesis, Place and Route, parasitic extraction and static timing (Synopsys or Cadence) and physical verification (Mentor, Synopsys, or Cadence) using advanced technologies like 12/14/28 technologies Strong EDA tool scripting using TCL, Make and proficiency in Python programming language, data structures, functions and OOPs Strong communication skills within a global team and the ability to define and execute projects independently Bachelors/Masters degree in electrical or computer engineering fields with required + 15 years of relevant work experience Preferred Qualifications Low power design techniques and UPF (IEEE 1801) Understand liberty (.lib) formats (NLDM, CCS, ECSM, AOCV/POCV/LVF) Hands-on experience using version control software like Perforce. Java, SQL are also preferred. GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency and innovation whilst our employees feel truly respected, valued and heard. As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities. All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations. Information about our benefits you can find here: https://gf.com/about-us/careers/opportunities-asia

Title: Principal Engineer, QSP About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com. Introduction This position is for a QSP Engineer who will act as a point-of-contact for all QSP related topics. The successful candidate needs to be self-driven with a strong solution-oriented approach. Your Job Qualification and signoff IP libraries from FIP, NVM Develop and maintain QSP flows and tool automation. Drive and own initiatives towards timely resolution of issues related to IP Ownership of release and point of contact with QMS team for the IP related issues Work with cross-geo, cross-vertical teams to understand requirements and communicate resolution Work with vendors like Cadence, Synopsys, siemens for resolutions related to tools Required Qualifications : Design Engineer with knowledge of EDA tools and flows – Crosscheck, Schematic, Layout (Virtuoso),FE views, BE views. Requires a Bachelor of Engineering (B.E.) or equivalent degree in a related field from an accredited university. B.E./B.Tech + minimum of 7-8 years of relevant experience M.E./M.Tech +minimum 4-6 years of relevant experience 3+ years of experience in IPQA teams Language Fluency – Fluent in English Language – written & verbal. Must have proficient knowledge of and experience with Unix environment Must have hands-on experience on crosscheck tool Should be fluent with Cadence EDA tools for schematic and physical layout, design rule checking (DRC), layout versus schematic checking (LVS, schematic and layout extraction, methodology checking) Must have good technical verbal and written communication skills and ability to work with cross functional teams is necessary Be able to collaborate with PMO and technical design leads on multiple concurrent projects. Should have excellent problem-solving skills, written & oral communication, teaming & interpersonal skills Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements, and programs Familiarity with standard engineering practices like Version Control systems, Configuration Management and Regression process Preferred Qualifications: Knowledge of scripting languages like Python/Perl Experience with PowerBI, Excel, Powerpoint and other office productivity tools GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency and innovation whilst our employees feel truly respected, valued and heard. As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities. All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations. Information about our benefits you can find here: https://gf.com/about-us/careers/opportunities-asia

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Sandisk's High-Performance Computing environments are key to bringing new storage solutions to market. As a Senior High-Performance Computing (HPC) engineer in the IT Infrastructure team, you will be at the heart of Sandisk’s engineering and product development process, delivering the IT HPC infrastructure and services that empowers engineering teams to develop new storage technologies and deliver high quality products to market quickly. As a member of the HPC as a service team – HPCaaS, you will be responsible for establishing and executing strategic objectives focused on improving the effective utilization of the compute resources while meeting or exceeding customer service level agreements for job prioritization, job concurrency, and job throughput in our EDA compute clusters. This includes leading architectural innovation and path finding efforts to create and implement Sandisk’s next generation Grid computing environment. As a member of the team, you will be expected to not only deliver on technical requirements and solutions but also be able to present your solutions to senior management. Responsibilities include but are not limited to working as an individual contributor, a team member and a technical team lead to explore, define, and pilot new solutions with little supervision. Develop solutions, scripts, and/or processes to automate management of services and tools as required. In this role, you will be collaborating closely with EDA and hardware design team stakeholders to define and deliver workload efficiency improvements in Sandisk’s EDA HPC infrastructure globally. Role Overview: Join our global engineering product development team to support and enhance multi-site, high-performance computing (HPC) infrastructure and services. You will design, implement, and maintain automation solutions while driving continuous improvements in performance and reliability. Key Responsibilities: Manage and support distributed HPC environments across multiple locations, focusing on ASIC and GPU computing clusters. Design, deploy, and maintain Ansible automation for HPC and Unix systems. Troubleshoot complex issues within HPC clusters and file systems, performing root cause analysis and driving corrective actions. Develop and maintain comprehensive documentation for HPC infrastructure. Identify opportunities to automate repetitive tasks and improve system reliability. Recommend and implement performance enhancements for various workloads. Support a broad Engineering Design Automation (EDA) ecosystem including licensing and workflow management. Technical Environment: Workload managers: LSF, Slurm, NC EDA tools such as Cadence, Synopsys, and their workflows Automation of job submissions and workload management Monitoring and observability using Splunk and Grafana Infrastructure: RedHat/CentOS Linux, NFS storage, automounters VDI: Exceed TurboX, VNC Unix/Linux authentication integrated with Active Directory Infrastructure automation through scripting and open-source tools Qualifications Bachelor’s degree in Computer Science or equivalent experience 10+ years of Linux systems administration, with strong expertise in RedHat/CentOS production environments Proven experience with workload managers, especially LSF/Slurm/NC Strong automation skills, proficient in at least two scripting languages (shell/bash, Python) Demonstrated ability to lead technical projects through their full lifecycle Excellent problem-solving, multitasking, and troubleshooting abilities in complex environments Outstanding interpersonal, customer service, and team collaboration skills, with a results-driven mindset Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Sandisk's High-Performance Computing environments are key to bringing new storage solutions to market. As a Senior High-Performance Computing (HPC) engineer in the IT Infrastructure team, you will be at the heart of Sandisk’s engineering and product development process, delivering the IT HPC infrastructure and services that empowers engineering teams to develop new storage technologies and deliver high quality products to market quickly. As a member of the HPC as a service team – HPCaaS, you will be responsible for establishing and executing strategic objectives focused on improving the effective utilization of the compute resources while meeting or exceeding customer service level agreements for job prioritization, job concurrency, and job throughput in our EDA compute clusters. This includes leading architectural innovation and path finding efforts to create and implement Sandisk’s next generation Grid computing environment. As a member of the team, you will be expected to not only deliver on technical requirements and solutions but also be able to present your solutions to senior management. Responsibilities include but are not limited to working as an individual contributor, a team member and a technical team lead to explore, define, and pilot new solutions with little supervision. Develop solutions, scripts, and/or processes to automate management of services and tools as required. In this role, you will be collaborating closely with EDA and hardware design team stakeholders to define and deliver workload efficiency improvements in Sandisk’s EDA HPC infrastructure globally. Role Overview Join our global engineering product development team to support and enhance multi-site, high-performance computing (HPC) infrastructure and services. You will design, implement, and maintain automation solutions while driving continuous improvements in performance and reliability. Key Responsibilities Manage and support distributed HPC environments across multiple locations, focusing on ASIC and GPU computing clusters. Design, deploy, and maintain Ansible automation for HPC and Unix systems. Troubleshoot complex issues within HPC clusters and file systems, performing root cause analysis and driving corrective actions. Develop and maintain comprehensive documentation for HPC infrastructure. Identify opportunities to automate repetitive tasks and improve system reliability. Recommend and implement performance enhancements for various workloads. Support a broad Engineering Design Automation (EDA) ecosystem including licensing and workflow management. Technical Environment Workload managers: LSF, Slurm, NC EDA tools such as Cadence, Synopsys, and their workflows Automation of job submissions and workload management Monitoring and observability using Splunk and Grafana Infrastructure: RedHat/CentOS Linux, NFS storage, automounters VDI: Exceed TurboX, VNC Unix/Linux authentication integrated with Active Directory Infrastructure automation through scripting and open-source tools Qualifications Bachelor’s degree in Computer Science or equivalent experience 10+ years of Linux systems administration, with strong expertise in RedHat/CentOS production environments Proven experience with workload managers, especially LSF/Slurm/NC Strong automation skills, proficient in at least two scripting languages (shell/bash, Python) Demonstrated ability to lead technical projects through their full lifecycle Excellent problem-solving, multitasking, and troubleshooting abilities in complex environments Outstanding interpersonal, customer service, and team collaboration skills, with a results-driven mindset Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

Location: Hybrid Job Type: Full-Time Posted Date: 6/30/2025 About The Role Job Overview: We are seeking a Senior Physical Design Engineer with strong expertise in Netlist-to-GDSII implementation and experience working on advanced submicron technology nodes. The role demands in-depth knowledge of industry-standard EDA tools and a solid grasp of timing closure and physical verification processes. Key Responsibilities:  Drive full Netlist-to-GDSII flow: floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off.  Perform Static Timing Analysis (STA) and ensure timing closure across all design corners.  Execute power integrity and physical verification checks (LVS, DRC).  Collaborate closely with cross-functional teams (RTL, STA, packaging, and DFT).  Handle complex designs on 28nm and below technology nodes. Must-Have Skills  Strong hands-on experience with: o Synopsys/Cadence tools: Innovus, ICC2, Primetime, PT-PX, Calibre o Physical Design Methodologies: Floorplanning, Placement, CTS, Routing, STA  Proficiency in: o Timing constraints and closure o Tcl/Tk/Perl scripting o Submicron nodes (28nm and below) Good to Have  Familiarity with Fusion Compiler  Broader understanding of signal and power integrity  Experience in workflow automation and tool scripting If you are interested in this role, please mail your resume to hemanth@neualto.com or spoorthy@neualto.com.

Company: Eteros Technologies India Private Limited Eteros Technologies, Inc. is a Semiconductor Engineering services startup, head quartered in the heart of the Silicon Valley, San Jose, CA, USA. Eteros Technologies India Pvt Ltd is a wholly owned subsidiary offices in Bangalore, Noida, Hyderabad and Ahmedabad • Our world-wide customers are amongst The Who's who in the semiconductor industry. Eteros works not only with some of the top 20 semiconductor startups in the world but boasts of customers who are among the most respected publicly traded semiconductor companies. • Eteros engineers work on cutting edge technology nodes while working on the state-of-the art designs in the AI/ML, Datacenter, Automotive and 5G domains. Eteros engineers work with some of the brightest, innovative and successful engineers and leaders around the world. A one-of-a-kind opportunity where young Eteros engineers showcase their ability and experience world-wide from day 1 while learning from some of the world's most well-respected companies. • We are not your traditional design services company offering staff augmentation. Eteros engineers are treated as an integral part of the customer team and routinely are responsible for turnkey, end-to-end ownership and delivery, whether it is Implementation, Digital and Mixed Signal Verification, DFT or Analog Design and Layout. Eteros and our engineers work closely with our customers to define and set methodologies and design flows. • Eteros invests in our engineers. Our engineers are continuously learning, on and off the job. They are able to grow the breadth and depth of knowledge. We believe in preparing our employees for the fast-track in career development as well as longevity ----------------------------------------------------------------------------- Job Title/Role: DFT - Senior Engineer/Lead Location : Bangalore/Hyderabad/Ahmedabad Experience Level : 4+ Years Industry : Semiconductors Employment Type : Full-time Job Functions : Engineering ----------------------------------------------------------------------------- Summary Minimum 4 yrs+ experience in DFT implementation Must have worked on Scan Insertion, MBiST, ATPG, Simulations Must have experience with Synopsys DFT tools & Flows Experience in DFT timing closure preferred Experience in multi-die HBM/Memory testing with Synopsys tools preferred Work hands-on on critical tasks of DFT implementation Own the DFT implementation flows, methodologies and execution of SoCs Experience Experience in all phases of the DFT pre and post-Si for large SoCs Implement DFT of SoC/Full-chip-level and/or high-speed cores/blocks Experience in high-speed, low-power, mixed-signal SoC’s is a plus Preferably worked on 5nm/7nm/12nm/14nm/16nm nodes at the major foundries Experience in developing DFT architecture, Test-plan, implementation methodologies Experience in scan insertion, memory-BIST, JTAG/IJTAG, CTL, IEEE 1149.1/1500 wrappers, BSCAN, Compression, ATPG, Simulations, post-Si testing/debug Experience in manual test-point insertion, improve coverage targets, high-compression Experience in hierarchical ATPG, OCC/OPCG, power-aware scan/ATPG methodologies Experience in test-mode constraints generation and test-mode timing closure Experience in patter generation for foundry, post-Si support/debug Thorough understanding of digital design, timing analysis, and physical design process EDA Tools: Cadence (Encounter-Test, Modus-DFT, Tempus, Conformal), Mentor (Tessent tool suite), Synopsys (DFTC, Tetramax, TestMax-DFT, SMS, PTSI) Requirements • BTech/MTech/PhD with in Electrical or Computer engineering • 4-8years of hands-on experience with DFT and test flow with commercial EDA tools for large and complex SOCs • Strong fundamental knowledge of DFT techniques include JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST • Experience with Cadence & Synopsys DFT tools is required. • Strong programming skills in Perl/TCL/C++ and shell scripting is required • Must be able to solve complex problems and independently drive tasks to completion in a timely manner. • Be able to work under limited supervision and take complete accountability. • Excellent written and verbal communication skills What's in it for you • Work on leading edge technologies • An opportunity for career development and growth • Competitive compensation • Medical Benefits and more

Company Description Spandsons Horizon Engineering revolutionises the AEC industry by integrating sustainability, Design & Build of Infrastructures, Structural Engineering, AI, IoT, and innovative technologies into project management, Virtual Design Construction, and training programs. We are at the forefront of blending advanced technological solutions with environmental consciousness to drive progress and innovation. Our mission is to deliver cutting-edge engineering solutions while fostering a culture of continuous learning and development. Role Description This is a contract role for a VLSI Mentor / Guest Faculty specialising in Advanced Digital Systems & Low Power Design. This is an on-site role located in Salem. You will be instrumental in guiding 5th, 6th, and 7th-semester B.E./B.Tech students in advanced VLSI concepts and practical applications. This role offers a unique opportunity to directly impact the academic and career growth of 60 aspiring engineers. Key Responsibilities: Deliver engaging and in-depth sessions on: Advanced Digital System Design with Verilog HDL: Covering topics from Verilog HDL basics, combinational and sequential circuits, FSM design, to simulation and testing. Low Power VLSI Design: Including the need for low power design, power estimation and optimisation, dynamic power reduction techniques, clock/power gating, and leakage reduction techniques. Potentially other VLSI domains such as Digital Design Verification with SystemVerilog & UVM, Introduction to FPGA-Based Digital System Design, ASIC Design and Verification, and Introduction to RISC-V Architecture and FPGA Design, based on program needs. Provide hands-on guidance for lab assignments and projects, utilising tools like Xilinx Vivado, EDA Playground, ModelSim/Vivado, LTspice, Synopsys Design Compiler, ICC2, PrimeTime, VCS, Verdi, and FPGA boards. Facilitate interactive learning and encourage problem-solving among students. Ensure alignment of content with the recommended semester curriculum and prerequisites. Qualifications: Minimum of 4-5 years of verifiable industry experience in VLSI design, with strong expertise in Advanced Digital System Design and Low Power VLSI Design. Proficiency in relevant EDA tools and hardware platforms as listed above. Excellent communication and presentation skills. A passion for teaching, mentoring, and contributing to student development. Program Details: Total Students: Approximately 60. Schedule: Thursdays & Fridays (12 hours per week). Program Start Date: July 24th & 25th. Duration: Program for Semesters 5, 6, and 7. Benefits: Accommodation and food will be provided by the institution. Opportunity to make a significant impact on the next generation of VLSI engineers. Collaborate with a forward-thinking academic institution.

Key Responsibilities: Perform timing, power, and signal integrity characterization of standard cells across different PVT corners. Generate Liberty (.lib), CCS, ECSM, and other timing/power models used by synthesis and place & route tools. Develop and validate models for dynamic power, leakage power, and noise . Set up and run characterization flows using tools such as Synopsys Liberate, Cadence Tempus/Modgen, or equivalent. Automate workflows using scripts in Python, Perl, Tcl, or Shell to improve efficiency and reliability. Work with library development and circuit design teams to ensure the quality and completeness of characterized views. Debug and resolve modeling discrepancies, setup issues, or tool-related bugs . Participate in library QA and validation across different design flows and EDA environments. Ensure consistency between layout, schematic, and extracted views for accurate modeling. Contribute to documentation, release management, and customer support as needed. Required Skills & Experience: Bachelor’s or Master’s degree in Electrical, Electronics, or Computer Engineering. 3–10 years of hands-on experience in standard cell characterization . Strong understanding of CMOS device physics, STA fundamentals, and signal integrity . Proficiency in Liberty format, characterization tools , and SPICE simulation . Experience with EDA tools such as Synopsys Liberate, PrimeTime, Cadence Tempus, HSPICE, Spectre, etc. Familiarity with advanced nodes (7nm, 5nm, 3nm, etc.) and FinFET technologies. Solid scripting experience in Python, Tcl, Perl, or Shell for automation. Good understanding of PVT variations, voltage scaling, and multi-corner modeling .

Key Responsibilities: Design and develop standard cells for advanced CMOS technology nodes (e.g., 7nm, 5nm, 3nm). Optimize cells for PPA metrics in coordination with layout and circuit teams. Perform circuit-level simulations (e.g., SPICE) to ensure functionality and robustness. Drive layout implementation with an understanding of design rules, parasitics, and manufacturability. Run and debug various verification flows including DRC, LVS, ERC, and EM/IR checks. Perform characterization and validation of standard cells using industry-standard tools (e.g., Liberate, SiliconSmart, etc.). Interface with physical design, RTL, EDA, and process technology teams to ensure seamless integration. Contribute to automation scripts to improve cell development workflows (Python, TCL, Perl, etc.). Document design methodologies and maintain library QA and release processes. Required Skills & Experience: B.E./B.Tech or M.E./M.Tech in Electrical Engineering, Electronics, or a related discipline. 3 to 10 years of hands-on experience in standard cell circuit design and validation. Strong understanding of CMOS fundamentals and transistor-level design. Experience with industry EDA tools from Synopsys, Cadence, or Siemens. Knowledge of characterization methodologies and tools. Familiarity with technology file setup and design rule constraints. Proficiency in scripting (Python, TCL, Shell, etc.) for design automation.

Key Responsibilities: Define and implement DFT architecture for SoCs and IPs. Develop and integrate scan chains, ATPG, MBIST, LBIST, and boundary scan (JTAG). Work with RTL designers to insert DFT logic and resolve DRC violations. Generate and validate test patterns using tools such as TetraMAX , FastScan , DFT Advisor , etc. Analyze and improve fault coverage and test time reduction. Support silicon bring-up and post-silicon validation of test features. Debug and resolve DFT-related issues during synthesis, simulation, and verification. Collaborate with physical design and verification teams to ensure DFT compliance throughout the flow. Required Skills: 3–10 years of hands-on experience in DFT implementation. Strong knowledge of scan insertion, ATPG, MBIST, LBIST, and boundary scan. Experience with DFT tools: Synopsys DFT Compiler , TetraMAX , Mentor Tessent , FastScan , DFTMAX , etc. Proficient in scripting (TCL, Perl, Python, Shell) for automation. Familiar with RTL coding (Verilog/SystemVerilog) and synthesis flow. Good understanding of timing constraints, STA, and low-power design considerations in DFT. Experience in handling gate-level simulations and testbench development.

Key Responsibilities: Drive block-level and/or full-chip physical design from RTL to GDSII. Floorplanning, placement, clock tree synthesis (CTS), and routing. Work on static timing analysis (STA) and timing closure. Run and debug physical verification (LVS/DRC/ERC) and power integrity checks (IR Drop/EM). Collaborate with RTL, DFT, synthesis, verification, and packaging teams. Ownership of PPA (Power, Performance, Area) targets and meeting timing goals. Participate in multiple tape-outs and manage block-level signoff closure. Automate and optimize flows using Tcl, Perl, Python, or shell scripting. Keep up-to-date with the latest EDA tools and technology trends. Required Skills & Experience: B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or related field. 4–10 years of experience in physical design with successful tape-outs. Strong expertise in Synopsys/Cadence tools (ICC2, Fusion Compiler, Innovus, PrimeTime, etc.). Deep understanding of digital design concepts, timing, and power trade-offs. Hands-on experience in advanced technology nodes (16nm and below preferred). Experience with scripting languages (Tcl, Python, Perl, Shell). Familiarity with ECO flows, DFT insertion, and low-power design techniques (UPF/CPF). Knowledge of signal and power integrity issues (IR/EM) is a plus.

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: MTS SILICON DESIGN ENGINEER (AECG ASIC TFM Lead) THE ROLE: As a Silicon Design Engineer in the AMD AECG ASIC TFM (Tools Flows Methodology) team, you will work with design experts to come up with the best implementation methodologies/flows and work on development and support of the BE flows. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. KEY RESPONSIBILITIES: Define and drive key Beckend/Physical Design methodologies. Partner with AMD CAD Teams, Design team, physical design teams to ensure seamless end to end design flows. Work with existing development teams to define roadmaps for existing flows and assist in difficult technical debug. Work closely with design teams to gather requirements and develop strategies to tackle key technical problems. Work on Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 8+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Excellent physical design and timing background. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Job Titles: ASIC Emulation Sr. Architect We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a visionary and accomplished ASIC emulation expert with a passion for leading teams and solving complex challenges in digital design. Your career has been marked by a commitment to innovation, technical excellence, and driving results in fast-paced, collaborative environments. You have a proven track record of architecting and optimizing emulation solutions for high-performance, mixed-signal IPs, and thrive on guiding teams to deliver robust, scalable verification environments. Your leadership style fosters trust, encourages open communication, and empowers engineers to achieve their best. You are adept at bridging the gap between design and verification, and you excel at translating technical requirements into actionable plans. Your expertise extends to regression management, test coverage analysis, and the development of emulation-friendly models, ensuring projects are delivered on time and to the highest quality standards. You are customer-focused, comfortable representing your work to both internal stakeholders and external partners, and committed to continuous learning and professional development. Your ability to mentor, inspire, and innovate makes you an invaluable asset to any organization. If you are excited by the prospect of shaping the future of emulation at the forefront of semiconductor technology, you belong at Synopsys. What You’ll Be Doing: Lead the integration of verification environments and RTL into the Zebu emulation platform for seamless operation. Execute emulation tests, debug issues, and optimize environments for improved performance and reliability. Manage and analyze regression results to identify issues and ensure comprehensive test coverage. Collaborate with design and verification teams to align requirements and resolve bottlenecks effectively. Innovate and refine emulation methodologies to enhance scalability, efficiency, and reliability. Define requirements on simulation environments to enable mapping to emulation environments. Define emulation targets and test plans to be prioritized for emulation. Develop emulation-friendly Real Number Models (RNM) for mixed-signal IPs to expedite digital and firmware verification. Define emulation planning across the IP titles, report status, risks, and mitigations to emulation plan. Standardize emulation flows across PHY and controller IPs, working closely with Synopsys’ Zebu team. Represent Synopsys on customer calls regarding emulation validation strategy, plans, and progress. Lead a team of emulation engineers, providing direction, mentorship, and technical leadership. The Impact You Will Have: Drive the integration of cutting-edge verification environments into emulation platforms, ensuring high performance and reliability. Enhance the efficiency of the emulation process, leading to faster and more reliable verification of complex designs. Ensure comprehensive test coverage through meticulous regression analysis and issue identification. Collaborate effectively with design and verification teams to optimize emulation strategies and resolve bottlenecks. Innovate emulation methodologies, contributing to the scalability and efficiency of verification processes. Develop and implement emulation models that accelerate the verification of mixed-signal IPs. Standardize emulation processes across various IPs, promoting consistency and best practices. Represent Synopsys in customer interactions, showcasing expertise in emulation validation. Lead and mentor a team of emulation engineers, fostering a collaborative and innovative environment. What You’ll Need: 20+ years of hands-on emulation experience on platforms such as Palladium, Veloce, or Zebu. Extensive knowledge of design mapping, testbench mapping, and transactor development for emulation environments. Expertise in hardware/software debug solutions tailored to emulation, with excellent debugging skills in functional and gate-level simulations. Strong programming skills in object-oriented languages such as C++, Java, or Python, and scripting languages like PERL, TCL, and Shell scripts. Hands-on experience with verification metrics, including functional, code, and assertion coverage. Comprehensive knowledge of protocols, including PCIe, I2C, and Ethernet packet headers. Familiarity with multi-domain verification environments, SystemVerilog DPI, and collaborative workflows using Git, Jenkins, or CI/CD pipelines. Strong analytical and problem-solving skills, with a proven ability to mentor junior engineers and collaborate effectively. Who You Are: A strong leader with excellent communication and mentoring skills. Innovative and committed to continuous improvement. Detail-oriented with a strategic mindset. Collaborative, with the ability to work effectively in a team environment. Passionate about technology and eager to work on cutting-edge projects. The Team You’ll Be A Part Of: You will be part of a dynamic team focused on driving innovation and excellence in the emulation of state-of-the-art protocol IPs. The team collaborates closely with design and verification teams to ensure the successful integration and optimization of verification environments. As a key member of this team, you will lead and mentor a group of talented engineers, fostering a culture of collaboration and innovation. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Job Titles: Senior Staff Emulation Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a driven and insightful Emulation Expert, passionate about pushing the boundaries of what’s possible in ASIC digital design. With a deep understanding of IP interfaces—especially PCIe and DDR—you are skilled in leveraging advanced emulation platforms like Zebu to accelerate verification and product development. Your career is marked by a proven ability to deliver robust, production-ready IP through rigorous emulation and verification cycles. You thrive in highly collaborative, matrixed, and international environments, bringing together diverse teams and perspectives to solve complex challenges. Your hands-on approach and proactive attitude make you a go-to resource for bridging gaps between Emulation IP and Design IP, ensuring seamless integration and verification of both Controller and PHY components. You have a keen eye for detail and are committed to right-first-time development, always ensuring traceability and completeness across verification requirements. You stay ahead of industry trends, standards, and evolving technologies, and are adept at translating these into actionable insights for your teams. As an excellent communicator and natural collaborator, you are comfortable working with multiple stakeholders and driving change within the organization. Your adaptability, resilience, and commitment to continuous learning set you apart as a leader in your field. What You’ll Be Doing: Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification for all functions, spanning both Controller and PHY domains. Reporting key metrics and driving continuous improvement initiatives in Emulation IP quality and performance. Providing technical leadership and expertise to define requirements for Emulation IP, ensuring its correct implementation and deployment within verification strategies. Staying ahead of evolving industry standards, interpreting future changes, ECNs, and specification errata, and integrating this knowledge into Emulation and Design IP teams. Reviewing and validating test plans for both Emulation IP and Design IP, guaranteeing best-in-class function, feature coverage, and product quality. Collaborating cross-functionally to optimize workflows, standardize methodologies, and ensure compliance with organizational goals. Mentoring and guiding junior engineers, fostering a culture of innovation and continuous improvement. The Impact You Will Have: Enhancing cross-functional collaboration to elevate product quality and end-customer satisfaction. Transforming the approach to Emulation IP usage in validating cutting-edge digital designs and system architectures. Driving innovation by defining and refining requirements for IP product development, particularly in emulation contexts. Championing the adoption of best-in-class verification methodologies across the organization. Standardizing and optimizing verification workflows to boost efficiency, traceability, and compliance. Influencing the next generation of emulation and verification solutions, positioning Synopsys as an industry leader. Accelerating time-to-market for high-performance silicon solutions through advanced emulation strategies. What You’ll Need: 8+ years of relevant experience in emulation, verification, or IP product development. Expert-level knowledge of PCIe and DDR interfaces, including protocol and verification strategies. Extensive hands-on experience with Zebu or similar emulation platforms, particularly for IP verification. Demonstrated track record in leading IP product development initiatives with a focus on emulation. Strong background in cross-functional collaboration, with an ability to drive consensus and deliver results. Outstanding communication skills, with the ability to influence and inspire change across diverse teams. Adaptability and comfort working in a fast-paced, matrixed, and international environment. Who You Are: A proactive and collaborative problem-solver with a passion for excellence. Innovative thinker who embraces change and seeks out opportunities for continuous improvement. Strong communicator, able to articulate complex technical concepts to diverse audiences. Resilient and adaptable, thriving in dynamic environments and embracing new challenges. Committed to mentoring others and fostering an inclusive, team-oriented culture. The Team You’ll Be a Part Of: You will join a dynamic, high-performing engineering team focused on IP development, emulation, and verification at the forefront of semiconductor innovation. Our team is collaborative, cross-functional, and globally distributed, working together to solve complex challenges and deliver industry-leading solutions. You will have the opportunity to collaborate with experts across multiple domains, drive impactful initiatives, and shape the future of digital design and verification at Synopsys. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Alternate Job Titles: Software Engineer, Staff We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned software engineer with a passion for innovation and problem-solving. With a BE/B.Tech degree in programming, computer/electronics, IT, or a related engineering field, you bring 5-8 years of hands-on experience in software development. Your proficiency in Python or C/C++, coupled with a strong understanding of algorithms and data structures, sets you apart. You thrive in UNIX/Linux and Windows OS environments and have a keen interest in exploring new technologies. Your ability to design and implement sophisticated algorithms, along with your prior knowledge of EDA tools and schematic/layout design, makes you an ideal candidate. Excellent English communication skills and the ability to compile functional and design specifications are essential for this role. What You’ll Be Doing: Designing, developing, troubleshooting, and maintaining software programs for std. cells development automations Involving in all phases of software development, including project planning, problem identification, design specification, development, testing, and product support Exercising judgment within broadly defined practices and policies in selecting methods, techniques, and evaluation criteria for obtaining results Developing state-of-the-art solutions through technical contributions that lead to significant product differentiation Designing and implementing sophisticated algorithms to solve complex problems Collaborating with cross-functional teams to ensure seamless integration and delivery of software solutions The Impact You Will Have: Driving innovation in software solutions for std. cells development automations Enhancing the efficiency and effectiveness of our software development lifecycle Contributing to the development of cutting-edge technology that sets Synopsys apart in the industry Ensuring high-quality software delivery through rigorous testing and problem-solving Influencing the design and implementation of future software projects Supporting the continuous improvement of our software development processes What You’ll Need: Proficiency in Python or C/C++ Knowledge of algorithms and data structures Working experience on UNIX/Linux and Windows OS Knowledge in OOP programming Strong desire to learn and explore new technologies Ability to demonstrate good analysis and problem-solving skills Prior knowledge and experience of EDA tools and schematic/layout design Excellent English language communication skills Ability to compile functional and design specifications Who You Are: Innovative thinker with a passion for technology Excellent communicator and collaborator Detail-oriented and highly organized Adept at problem-solving and critical thinking Proactive and self-motivated The Team You’ll Be A Part Of: You will be part of a dynamic and innovative team focused on developing and maintaining software solutions for std. cells development automations. Our team values collaboration, creativity, and continuous improvement, and we are dedicated to pushing the boundaries of technology to deliver exceptional products. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

If you are passionate towards crafting customer success and interested to build exciting career working in cutting edge technology with world’s largest EDA company, then this role meets your requirement. You will get an opportunity to work on latest Synopsys implementation technologies (Machine Learning, Physical Synthesis , Multi-Source CTS, etc.) to solve complex PPA challenges faced by Synopsys customers. Working on benchmarks to displace competition implementation solutions. Working on developing and debugging RTL-GDS implementation methodologies and flows. Providing technical solutions by identifying the design and/or EDA tool issues and provide an appropriate solution for customers. Effectively translate the findings into requirements for R&D to improve both tool behavior with enhancements as adaptive long-term solutions. Involved in deployment of new technologies on latest EDA versions and enable customers to migrate to newer versions achieving best PPA. Coming up with a proactive understanding of customers' pain point and coming up with innovative solutions to address the same. Closely interacting with Synopsys R&D team and product development team to develop future technologies. This role requires you to act as customers advocate while talking to inhouse R&D and be a product brand ambassador while engaging with customers. The candidate must have good exposure to methodology changes to achieve targeted PPA metrics for complex designs. At least 2 years of experience in Physical Implementation RTL-GDS. Experience in autonomously debugging and resolving synth & PnR implementation challenges. Proficiency in Synopsys implementation tools is an advantage. The individual must be self-motivated and dedicated with strong debugging skills. Requires proficiency in scripting (tcl / unix / perl). Excellent communication skills including the ability to interface with customers and business unit personnel are essential.