886 Synopsys Jobs - Page 9

SE NIOR SILICON DESIGN ENGINEER THE ROLE : We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor , you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The V erification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ time zone s . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Job Description: The verification team is looking for a Senior Design Verification Engineer to contribute on the verification of Network on Chip IPs, Subsystems having adequate knowledgeble on the boot flow. The individual will help architect, develop and use simulation and/or formal based verification environments, at block, subystem , Fulchip level, to prove the functional correctness of Network-On-Chip (NOC) IPs, subsystem and SOC designs. Responsibilities: Plan verification of complex digital design blocks by fully understanding the architecture and design specification Interact with architects and design engineers to create a comprehensive verification testplan Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools Debug tests with design engineers to deliver functionally correct design blocks Identify and write coverage measures for stimulus quality improvements Perform coverage analysis to identify verification holes and achieve closure on coverage metrics General requirements: Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs Strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification Strong understanding of different phases of ASIC and/or full custom chip development is required Experience in block level NOC (Network on Chip) verification is a plus Verification Experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance FPGAs, SOCs and/or VLSI designs is a plus Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC-Formal, Magellan) is a plus Special Requirements : Architect and implement verification environment using advanced verification methodology such as UVM or SystemVerilog; Test plan development and test writing; Analyzing and debugging failures using simulation tools such as Synopsys VCS or DVE to verify hard IPs, FPGA fabric or System-on-Chip; Functional coverage writing, coverage collection and analysis, coverage closure; Writing System Verilog assertions and assertion based verification; and, Running regressions, automation using scripting languages such as PERL and verification closure Education Requirements: Masters / B.Tech / M.Tech Years of Experience : 5+ Years #LI-SG

In the TD Advanced Modeling Group in Hyderabad you will work in a multi-functional team of engineers highly skilled in the modeling of materials, process, structure, and reactor, who are responsible for deploying modeling solutions towards advanced node development in TD and HVM. You will be responsible for developing predictive structure modeling simulations across multiple DRAM and NAND nodes. You will collaborate extensively with product design and process/integration teams for 3D structure model development, deployment, and providing solutions to be implemented on Silicon wafer. You will interact with process integration engineers and development teams to identify questions and issues hindering the node development milestones. Additionally, you will create programs, algorithms, and computational modeling solutions to extract concrete insights from modeling and data. You will interpret and convey these insights and findings from models and experiments to engineering teams and leaders. You are expected to work in a dynamic and fast-paced team environment developing and deploying models, communicating results to the team members, and collaborating with them on next steps. Qualifications: Master's or PhD degree in Applied Mechanics, Materials Science, Mechanical Engineering, or any related fields of engineering and physics. Possess 5+ years of strong Semiconductor process integration experience, driving structure specs, yield pareto issues for a product with hands-on (beginner level) experience in 3D semiconductor structure model building tools like Synopsys, Cadence, Mentor, and Silvaco. Understanding of analysis techniques like TEM/SEM/TDS and metrology techniques like Ellipsometry/ WIS/Image based defect analysis. Experience with data analysis tools and machine learning frameworks (e.g., Python, MATLAB, TensorFlow). Experience with HPC on Linux environment Experience with computational geometry and mesh generation techniques is an added advantage. Excellent problem-solving skills and attention to detail. Ability to work independently and collaboratively in a fast-paced environment. Excellent written and verbal communication Experience with reports and presentations customized for users, managers and leaders Outstanding teamwork and experience with remote collaboration tools.

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SE NIOR SILICON DESIGN ENGINEER THE ROLE : We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Job Description: The verification team is looking for a Senior Design Verification Engineer to contribute on the verification of Network on Chip IPs, Subsystems having adequate knowledgeble on the boot flow. The individual will help architect, develop and use simulation and/or formal based verification environments, at block, subystem , Fulchip level, to prove the functional correctness of Network-On-Chip (NOC) IPs, subsystem and SOC designs. Responsibilities: Plan verification of complex digital design blocks by fully understanding the architecture and design specification Interact with architects and design engineers to create a comprehensive verification testplan Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools Debug tests with design engineers to deliver functionally correct design blocks Identify and write coverage measures for stimulus quality improvements Perform coverage analysis to identify verification holes and achieve closure on coverage metrics General requirements: Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs Strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification Strong understanding of different phases of ASIC and/or full custom chip development is required Experience in block level NOC (Network on Chip) verification is a plus Verification Experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance FPGAs, SOCs and/or VLSI designs is a plus Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC-Formal, Magellan) is a plus Special Requirements : Architect and implement verification environment using advanced verification methodology such as UVM or SystemVerilog; Test plan development and test writing; Analyzing and debugging failures using simulation tools such as Synopsys VCS or DVE to verify hard IPs, FPGA fabric or System-on-Chip; Functional coverage writing, coverage collection and analysis, coverage closure; Writing System Verilog assertions and assertion based verification; and, Running regressions, automation using scripting languages such as PERL and verification closure Education Requirements: Masters / B.Tech / M.Tech Years of Experience : 5+ Years #LI-SG Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and highly skilled engineer committed to advancing the field of high-speed analog design. You bring a wealth of experience in designing critical analog and mixed-signal blocks, particularly for cutting-edge PCIe 6 and PCIe 7 or SerDes PHY solutions. Your technical expertise encompasses transistor-level design, deep knowledge of CMOS (including finFET and SOI processes), and a proven ability to create robust high-speed building blocks—such as LDOs, Bandgap references, ADC/DACs, PLLs, and DLLs—that consistently meet rigorous performance, power, and area targets. You thrive in collaborative, multidisciplinary environments, where your clear communication and mentoring skills empower both peers and junior engineers to excel. Your proactive approach to problem-solving and your dedication to continuous improvement ensure that you stay at the forefront of technology trends. You are adept at analyzing and mitigating jitter, maintaining signal integrity, and ensuring compliance with demanding industry standards. Your experience with porting PHY designs across technology nodes demonstrates your adaptability and commitment to delivering high-quality, innovative solutions. You value documentation, knowledge sharing, and actively contribute to a culture of learning and technical excellence. Most importantly, you are excited to join a team that values diversity, encourages bold ideas, and is committed to shaping the future of high-speed connectivity. You see challenges as opportunities and bring a growth mindset to every project you undertake. What You’ll Be Doing: Designing and developing advanced analog/mixed-signal blocks for PCIe 6 and PCIe 7 PHY architectures under the guidance of senior technical leaders. Ensuring that all designs strictly adhere to PCIe protocol standards, optimizing for performance, power, and area efficiency. Porting high-speed PHY designs to various technology nodes while maintaining signal integrity and maximizing performance. Collaborating with cross-functional teams—including digital, verification, and layout groups—to successfully integrate analog circuits into complex SerDes PHY systems. Implementing innovative verification strategies for high-speed analog/mixed-signal circuits using state-of-the-art simulation and modeling tools. Working closely with layout teams to minimize parasitics, device stress, and process variation impacts on overall circuit performance. Analyzing simulation and silicon measurement data to validate designs and ensure compliance with PCIe standards. Mentoring junior engineers and promoting best practices in analog/mixed-signal design and verification. Documenting design features, specifications, and test methodologies for future reference and team knowledge sharing. Partnering with characterization teams to validate electrical performance of circuits in silicon and resolve technical challenges. The Impact You Will Have: Drive the development of next-generation PCIe 6 and PCIe 7 PHY designs, advancing high-speed interface technologies that power tomorrow’s data-driven world. Ensure Synopsys’ analog/mixed-signal circuits exceed industry standards, reinforcing our reputation for technical excellence and innovation. Facilitate seamless integration of analog circuits into sophisticated SerDes PHY systems, enhancing overall performance and reliability. Mentor and develop junior engineers, fostering a collaborative and innovative team environment. Lead successful porting of PHY designs across multiple technology nodes, delivering versatile and scalable solutions for diverse customer needs. Strengthen verification and validation processes, resulting in robust, reliable, and high-performing analog/mixed-signal circuits. What You’ll Need: PhD with 3+ years, or MTech/MS with 7+ years of experience in analog/mixed-signal circuit design focused on high-speed interfaces such as PCIe 6/7 or SerDes PHY designs. Proven expertise in transistor-level design of high-speed analog building blocks (e.g., LDOs, Bandgap references, ADC/DACs, PLLs, DLLs). Demonstrated silicon experience in developing PHY circuits compliant with PCIe standards. Strong background in high-speed SerDes AFE development, including CTLE and CDR design. Experience designing high-speed SerDes transmitters and deep knowledge of equalization techniques (e.g., DFE, FIR filters, TX pre-emphasis). Solid foundation in jitter budgeting analysis and expertise in minimizing jitter impact on signal integrity. Experience porting PHY designs across different technology nodes and deep knowledge of CMOS, finFET, and gate-all-around processes. Comprehensive understanding of the PCIe protocol, signal integrity, jitter performance, and high-speed clocking. Ability to collaborate with layout teams to minimize parasitics, process variations, and electromigration effects. Proven track record of effective teamwork and successful project outcomes across multidisciplinary teams. Who You Are: Innovative thinker with a passion for high-speed analog design and technology advancement. Collaborative team player who values diversity and inclusion. Effective communicator, able to translate complex technical concepts to a variety of audiences. Mentor and coach, eager to support the development of junior engineers. Detail-oriented problem solver with a commitment to quality and continuous improvement. Adaptable and resourceful, thriving in fast-paced, changing environments. The Team You’ll Be A Part Of: You will join a world-class analog/mixed-signal design team at Synopsys, focused on developing high-speed interface IP for next-generation semiconductor products. The team is composed of passionate engineers from diverse backgrounds, collaborating closely to deliver innovative solutions that drive the future of connectivity. Our culture emphasizes technical excellence, knowledge sharing, and continuous learning, providing an environment where your skills and ideas are valued and your career can thrive. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Alternate Job Titles: Senior R&D Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and driven engineering professional with a strong foundation in VLSI concepts, CMOS circuit design, and EDA tools. With2-3 years of hands-on experience in the semiconductor industry, you thrive in dynamic environments where innovation, collaboration, and continuous learning are valued. Your curiosity drives you to explore emerging technologies such as AI/ML, and you have developed proficiency in scripting languages like TCL and Python to solve complex engineering challenges. You have a keen eye for detail and a solid grasp of timing, power, and noise analysis, enabling you to deliver robust and reliable design solutions. Your exposure to industry-standard tools such as VCS, Design Compiler, Primetime, and HSPICE/Primesim has honed your technical expertise, and you are comfortable navigating various stages of the design flow, from synthesis to signoff. As a team player, you communicate effectively, share knowledge openly, and support your peers in achieving shared goals. You value diversity, equity, and inclusion, and are eager to contribute to a culture that fosters creativity and personal growth. If you are ready to challenge yourself, make an impact, and be part of a world-class engineering team, Synopsys is the place for you. What You’ll Be Doing: Developing and maintaining scripts and automation flows using TCL, Python, and Make to streamline EDA tool operations and design processes. Performing advanced timing, power, and noise analysis on CMOS circuits, leveraging your understanding of setup/hold constraints and leakage concepts. Contributing to the characterization of standard cell libraries, including NLDM/CCSN and LVF methodologies, and ensuring accurate modeling for signoff. Collaborating with design, verification, and methodology teams to optimize PPA (Power, Performance, Area) and address STA (Static Timing Analysis) challenges. Utilizing tools such as VCS, Design Compiler, Primetime, and HSPICE/Primesim to support verification, synthesis, and signoff activities. Participating in root cause analysis of timing and power issues, implementing innovative solutions, and documenting best practices for future projects. Staying abreast of the latest trends in AI/ML and exploring their application in EDA tool flows and design optimization. The Impact You Will Have: Accelerate the delivery and quality of Synopsys' IP and design solutions through automation and process innovation. Enhance product reliability by ensuring precise timing and power characterization, directly influencing customer satisfaction. Drive cross-functional collaboration, sharing insights and solutions that elevate team performance and project outcomes. Contribute to the adoption of cutting-edge AI/ML techniques, positioning Synopsys as a leader in intelligent EDA workflows. Reduce design cycle times and resource bottlenecks through effective scripting and workflow optimization. Mentor and support junior engineers, fostering a culture of knowledge sharing and continuous improvement. What You’ll Need: 2-3 years of experience in VLSI design, EDA tool flows, or related semiconductor engineering roles. Proficiency in TCL, Python, and Make for scripting and automation. Strong understanding of CMOS circuit fundamentals, including timing (setup/hold), power (leakage/dynamic), and noise analysis. Experience with cell library characterization methodologies (NLDM/CCSN, LVF) and familiarity with library constructs and syntax. Working knowledge of STA analysis, PPA trends, and basic understanding of PNR (Place & Route). Hands-on experience with EDA tools: VCS, Design Compiler, Primetime, HSPICE/Primesim. Who You Are: Analytical thinker with strong problem-solving skills and a passion for innovation. Effective communicator, able to collaborate across disciplines and share complex ideas clearly. Self-motivated and adaptable, eager to learn new technologies and methods. Detail-oriented with a commitment to delivering high-quality results under tight deadlines. Team player who values diversity, equity, and inclusion in the workplace. The Team You’ll Be A Part Of: You will join a vibrant team of R&D engineers focused on advancing the state of the art in chip characterization, timing, and power analysis. Our team collaborates closely with cross-functional partners in design, verification, and methodology to deliver next-generation semiconductor solutions. We foster a culture of innovation, mentorship, and continuous improvement, ensuring every member has an opportunity to grow and make a meaningful impact. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SILICON DESIGN ENGINEER 2 THE ROLE: As a Silicon Design Engineer, you will work with formal experts and designers to verify formal properties and drive convergence. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Run spice simulations and capture that data using script written using a programing language Perform task of debugging design timing related issues both in Spice simulations and STA reports Std cell characterization using Synopsys Silicon smart tool Run internal scripts for timing capture and update scripts when necessary PREFERRED EXPERIENCE: Basic STA knowledge CMOS Technology fundamentals Transistor level understanding of the circuit Digital hardware designing using Verilog H-Spice simulations, exposure to STA tools like Primetime Experience in scripting language like perl, python and tcl Ability to work individually and in a team ACADEMIC CREDENTIALS: Bachelors or Masters degree in ECE with 3+ years of relevant experience #LI-SR4 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Senior Standard Cell Layout Engineer Standard Cell Layout Designer Digital Layout Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and highly motivated professional with a robust technical background in standard cells layout design. Your passion for excellence and precision drives you to create layouts that set the standard for quality and manufacturability. You thrive in collaborative, cross-functional environments, seamlessly working with circuit designers, verification engineers, and other stakeholders to deliver optimized layout solutions. Your expertise in industry-leading EDA tools—such as Cadence Virtuoso or Synopsys Custom Compiler—enables you to tackle complex digital circuit layouts with efficiency and accuracy. Your systematic approach and strong problem-solving skills allow you to navigate technical challenges with ease, always seeking innovative ways to enhance design methodologies and best practices. You are deeply familiar with physical verification processes and design rule checks, ensuring that every layout you deliver meets stringent quality and manufacturability standards. Your curiosity and commitment to lifelong learning keep you updated on the latest advancements in standard cell layout design, making you an invaluable resource for your team. You communicate effectively, embrace feedback, and are eager to contribute to a culture of continuous improvement and shared success. What You’ll Be Doing: Collaborate with cross-functional teams to develop and implement layout designs for digital circuits, ensuring alignment with project goals and timelines. Create and optimize complex standard cell layouts using industry-standard EDA tools such as Cadence Virtuoso or Synopsys Custom Compiler. Perform thorough physical verification and design rule checks (DRC/LVS) to guarantee design integrity and manufacturability. Work closely with circuit designers to understand design specifications, constraints, and performance targets, translating them into robust layouts. Contribute to the development, documentation, and refinement of layout design methodologies, flows, and best practices within the team. Remain up to date with industry trends, emerging technologies, and advancements in standard cell layout design, sharing knowledge with peers. The Impact You Will Have: Deliver high-quality layout designs that form the foundation of Logic Libraries IP development, essential for advanced SOC subsystems. Drive innovation in layout design methodologies, contributing to Synopsys’ leadership in the industry. Ensure that all designs meet or exceed manufacturability and reliability standards, reducing risk and time-to-market for key products. Collaborate effectively with circuit designers and verification teams to meet challenging design specifications and project milestones. Contribute to the overall success and reputation of the Logic Libraries IP group through your technical excellence and teamwork. Mentor and support junior team members, fostering a culture of knowledge-sharing and continuous improvement. What You’ll Need: Bachelor’s or master’s degree in electronics engineering or a related field. Minimum2 years of hands-on experience in standard cells layout design for digital circuits. Proficiency with industry-standard EDA tools, including Cadence Virtuoso or Synopsys Custom Compiler. Deep knowledge of layout design methods, techniques, and methodologies for high-performance and robust standard cells. Experience with physical verification tools such as ICC2, including DRC and LVS checks. Strong analytical and systematic problem-solving skills, with a detail-oriented mindset. Ability to work effectively in a collaborative, team-driven environment. Excellent communication and interpersonal skills, with a willingness to learn and share knowledge. Who You Are: A collaborative team player who values open communication and shared goals. Detail-oriented, with a commitment to delivering high-quality and reliable work. Curious and proactive, embracing continuous learning and professional development. Adaptable and resilient in the face of technical challenges and evolving requirements. Passionate about innovation, with a drive to improve processes and methodologies. Self-motivated, organized, and able to manage multiple priorities in a fast-paced environment. The Team You’ll Be A Part Of: You’ll join a dynamic and supportive Logic Libraries IP group focused on developing state-of-the-art standard cell libraries for advanced SOC subsystems. Our team thrives on collaboration, innovation, and technical excellence. We value diverse perspectives and foster an inclusive environment where every member’s contributions are recognized and celebrated. Together, we drive the success of Synopsys’ IP solutions, setting industry benchmarks and enabling our customers to achieve next-generation performance. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Category Engineering Hire Type Employee Job ID 12207 Remote Eligible No Date Posted 15/07/2025 Alternate Job Titles: Functional Verification Engineer Pre-Silicon Verification Engineer Digital Design Verification Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a dynamic and enthusiastic individual with a strong drive to learn and excel in the field of digital verification. You have a keen eye for detail and a deep understanding of digital design and hardware description languages (HDL). With your expertise in functional verification, you are eager to contribute to the pre-silicon verification activities for high-speed interface IPs. You possess excellent problem-solving skills and can work effectively in a collaborative environment. Your proactive approach and strong communication skills enable you to work closely with digital designers to achieve desired coverage and ensure the highest quality of IPs. What You’ll Be Doing: Working on functional verification of high-speed serial link PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards. Studying IP/design blocks/firmware specifications and building/updating verification plans and test cases. Building/updating functional verification environments to execute test plans. Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs) as per verification plan needs. Performing simulation, random and direct stimulus development, and coverage review. Working closely with digital designers for debugging and achieving the desired coverage. The Impact You Will Have: Ensuring the accuracy and functionality of high-speed interface IPs, contributing to the development of cutting-edge technology. Enhancing the reliability and performance of Synopsys' products through meticulous verification processes. Driving innovation in the semiconductor industry by verifying complex digital designs. Collaborating with a team of skilled professionals to deliver high-quality IPs that meet industry standards. Improving the efficiency of the verification process through automation and advanced verification methodologies. Contributing to the overall success of Synopsys by ensuring the delivery of robust and reliable IPs to customers. What You’ll Need: B.Tech/M.Tech with 3+ years of relevant experience. Understanding of functional verification flow with awareness of verification tools and methodologies such as VMM, OVM/UVM, and System Verilog. Proficiency in scripting and automation using TCL, PERL, or Python. Strong debug and diagnostic skills. Experience in building and updating functional verification environments. Who You Are: An excellent communicator who can collaborate effectively with cross-functional teams. A proactive problem solver with a keen eye for detail. An enthusiastic learner with a passion for technology and innovation. A team player who thrives in a collaborative environment. A highly organized individual who can manage multiple tasks and priorities effectively. The Team You’ll Be A Part Of: You will be part of a dedicated and innovative team focused on the functional verification of high-speed interface IPs. Our team collaborates closely with digital designers and engineers to ensure the highest quality of IPs. We are committed to continuous learning and development, fostering an environment where creativity and innovation thrive. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performan ce silicon chips and software content. Join us to transform the future through continuous technological innovation.You Are: You are a passionate and experienced engineer eager to make a significant impact in the world of embedded memory development. With a strong academic background in Electrical & Electronics Engineering and at least 2 years of hands-on experience in VLSI design, you thrive in collaborative, innovative environments. You possess a deep understanding of SRAM and Register File architectures, and you are well-versed in the nuances of advanced custom circuit i mplementation, especially at the most advanced technology nodes such as FinFET and submicron processes. Your expertise in scripting and automation, combined with a solid grasp of both digital and analog fundamentals, empowers you to tackle complex challenges and deliver high-quality, efficient solutions. You are a creative problem-solver who welcomes technical challenges and approaches them with curiosity and determination. Your communication skills, adaptability, and ability to work seamlessly across teams make you a valued collaborator. You are committed to continuous learning and excited by the prospect of working at the intersection of technology and innovation. As an advocate for best practices and a mentor to junior engineers, you foster an environment of growth and inclusion. Your commitment to excellence, quality, and customer focus ensures that you deliver solutions that exceed expectations and contribute meaningfully to Synopsys' leadership in the semiconductor industry. What You'll Be Doing: Developing innovative multiport SRAM and register file architectures and implementing advanced circuit design techniques. Performing schematic entry, simulation of major blocks, layout planning, and supervising the layout process while interfacing with the CAD team for full verification and model generation. Designing and implementing low-power, area-efficient embedded memory circuits and architectures, including SRAM and register files. Learning and applying advanced skills in memory compilers, focusing on transistor-lev el circuit design and automation. Resolving a wide range of design and implementation challenges through creative, resourceful methods and collaborating closely with internal and external stakeholders. Networking with senior engineers across disciplines and locations to ensure optimal solutions and knowledge sharing. Driving projects from conception through to completion, ensuring timely delivery and high quality. The Impact You Will Have: Contribute to the development of cutting-edge embedded memory IP that powers the next generation of integrated circuits. Enhance the performance, efficiency, and scalability of Synopsys' memory solutions, directly impacting customers' product capabilities. Enable faster, more reliable, and lower-power system-on-chip (SoC) designs for a wide range of applications, from consumer electronics to automotive and AI. Support cross-function al teams by providing technical expertise and driving best practices in memory architecture and design. Foster innovation within the team, championing new ideas and approaches to complex design challenges. Uphold Synopsys' reputation for delivering high-quality, reliable, and innovative semiconductor IP to global customers. What You'll Need: BE /B.Tech/ME/M.T ech/MS in Electrical & Electronics Engineering from a recognized institute or university. Minimum of 2+ years of experience in VLSI design, with a strong focus on embedded memory (SRAM/Register File) architectures. Expertise in advanced custom circuit design and a deep understanding of full embedded memory design flow, including architecture, physical i mplementation, and compiler automation. Hands-on experience with FinFET and deep submicron technology nodes, including variation-awar e design techniques. Mastery in scripting languages such as Perl and Python for design automation and optimization. Solid understanding of CMOS fundamentals, digital design, transfer functions, and RC circuit analysis. Familiarity with both digital and analog fundamentals, as well as CMOS fabrication processes. Who You Are: Analytical thinker with strong problem-solvin g skills and attention to detail. Effective communicator who thrives in cross-function al, multicultural teams. Proactive and self-driven, with a strong sense of ownership and a ccountability. Flexible, adaptable, and eager to learn new technologies and methodologies. Collaborative team player who values diversity and inclusion. Customer-focus ed, with a commitment to delivering high-quality solutions on time. The Team You'll Be A Part Of: You will join the Embedded Memory and Logic Team in Noida, a dynamic group within the Solutions Group at Synopsys. The team is dedicated to the development of standard and custom embedded SRAMs and ROMs, providing both functional and physical memory views through cutting-edge memory compilers. With end-to-end responsibility for bit cell analysis, architecture design, characterizati on, and verification, the team thrives on innovation, collaboration, and technical excellence. You'll work alongside talented engineers who are passionate about advancing semiconductor technology and delivering world-class IP solutions to global customers. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process

Category Engineering Hire Type Employee Job ID 12208 Remote Eligible No Date Posted 15/07/2025 Alternate Job Titles: Functional Verification Engineer Pre-Silicon Verification Engineer Digital Design Verification Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a dynamic and enthusiastic individual with a strong drive to learn and excel in the field of digital verification. You have a keen eye for detail and a deep understanding of digital design and hardware description languages (HDL). With your expertise in functional verification, you are eager to contribute to the pre-silicon verification activities for high-speed interface IPs. You possess excellent problem-solving skills and can work effectively in a collaborative environment. Your proactive approach and strong communication skills enable you to work closely with digital designers to achieve desired coverage and ensure the highest quality of IPs. What You’ll Be Doing: Working on functional verification of high-speed serial link PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards. Studying IP/design blocks/firmware specifications and building/updating verification plans and test cases. Building/updating functional verification environments to execute test plans. Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs) as per verification plan needs. Performing simulation, random and direct stimulus development, and coverage review. Working closely with digital designers for debugging and achieving the desired coverage. The Impact You Will Have: Ensuring the accuracy and functionality of high-speed interface IPs, contributing to the development of cutting-edge technology. Enhancing the reliability and performance of Synopsys' products through meticulous verification processes. Driving innovation in the semiconductor industry by verifying complex digital designs. Collaborating with a team of skilled professionals to deliver high-quality IPs that meet industry standards. Improving the efficiency of the verification process through automation and advanced verification methodologies. Contributing to the overall success of Synopsys by ensuring the delivery of robust and reliable IPs to customers. What You’ll Need: B.Tech/M.Tech with 3+ years of relevant experience. Understanding of functional verification flow with awareness of verification tools and methodologies such as VMM, OVM/UVM, and System Verilog. Proficiency in scripting and automation using TCL, PERL, or Python. Strong debug and diagnostic skills. Experience in building and updating functional verification environments. Who You Are: An excellent communicator who can collaborate effectively with cross-functional teams. A proactive problem solver with a keen eye for detail. An enthusiastic learner with a passion for technology and innovation. A team player who thrives in a collaborative environment. A highly organized individual who can manage multiple tasks and priorities effectively. The Team You’ll Be A Part Of: You will be part of a dedicated and innovative team focused on the functional verification of high-speed interface IPs. Our team collaborates closely with digital designers and engineers to ensure the highest quality of IPs. We are committed to continuous learning and development, fostering an environment where creativity and innovation thrive. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 10849 Date posted 07/16/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are passionate about solving complex problems at the intersection of software engineering and semiconductor technology. Your curiosity drives you to explore new solutions and approaches, especially in high-impact areas such as memory characterization and automation. With a strong foundation in computer science, electronics, or a related discipline, you thrive in environments where collaboration, innovation, and technical excellence are valued. You are detail-oriented, analytical, and always eager to learn and adapt as technology evolves. You take pride in building robust, maintainable code and are committed to delivering quality solutions that make a tangible difference. As a team player, you communicate clearly, seek feedback, and contribute to a culture of openness and continuous improvement. Whether working independently or in cross-functional teams, you bring a sense of accountability and ownership to your work. You are excited by the prospect of impacting the next generation of semiconductor products and motivated by the opportunity to drive productivity and efficiency through automation. If you are ready to challenge yourself, innovate, and help shape the future of memory IP development, Synopsys is the place for you. What You’ll Be Doing: Designing and developing robust software tools for automating memory characterization workflows, including simulation setup, data extraction, and report generation. Collaborating closely with memory design, CAD, and validation teams to understand requirements and implement solutions that enhance accuracy, scalability, and performance of characterization flows. Integrating EDA tools such as SPICE simulators, Liberty format analyzers, and waveform viewers into advanced automation flows. Optimizing simulation execution on large compute clusters and efficiently managing the vast data sets generated during memory characterization. Building modular, maintainable, and high-performance codebases using C++, Python, Shell/TCL scripts, and industry-standard software engineering tools. Contributing to the development of test infrastructure, debugging tools, and validation methodologies to ensure the correctness and consistency of characterization results. Participating in code reviews, providing innovative ideas, and driving improvements in productivity and tool efficiency across the team. The Impact You Will Have: Accelerate the delivery of high-performance memory compilers for advanced technology nodes (e.g.,5nm,3nm, and beyond), enabling cutting-edge products. Streamline and automate engineering flows, reducing manual effort and enhancing productivity for multidisciplinary teams. Enhance the quality and reliability of characterization data, directly contributing to Process Design Kits (PDKs), EDA tools, and customer deliverables. Drive innovations that improve cost-efficiency, scalability, and competitiveness of Synopsys’ global IP portfolio. Contribute to the continuous improvement of internal infrastructure, processes, and best practices, fostering a culture of technical excellence. Empower internal and external customers through robust, user-friendly tools that enable faster, more reliable delivery of semiconductor solutions. What You’ll Need: B.Tech/MTech in Computer Science, Electronics, or a related field. At least 2 years of experience in software development or EDA tool development, preferably within the semiconductor industry. Proficiency in C/C++, TCL, Python, SQL, and scripting languages such as Shell. Experience with debugging tools such as GDB, and memory debugging tools like Valgrind or Purify. Strong understanding of machine learning algorithms (supervised, unsupervised, reinforcement learning). Hands-on experience with Python ML libraries such as scikit-learn, TensorFlow, or PyTorch. Who You Are: Detail-oriented with excellent analytical and problem-solving abilities. Possess strong verbal and written communication skills, able to articulate complex technical concepts clearly. A collaborative team player who thrives in cross-functional and multicultural environments. Demonstrates accountability and ownership in delivering high-quality work. An innovative thinker passionate about technology, automation, and continuous learning. The Team You’ll Be A Part Of: You’ll be joining a dynamic and forward-thinking team dedicated to developing and maintaining advanced memory characterization tools for next-generation semiconductor technologies. The team is known for its strong collaboration across domains such as software, CAD, and design, and for fostering a culture of inclusivity and openness. Committed to continuous improvement, the team values innovation and feedback while delivering high-quality, impactful solutions that empower both internal teams and external customers. Together, you will be driving the future of memory IP development by solving complex challenges and pushing the boundaries of performance, scalability, and automation. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performan ce silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and innovative engineer dedicated to pushing the boundaries of semiconductor technology. You thrive in a collaborative environment where your expertise in embedded memory architectures and deep submicron technologies is highly valued. With a strong foundation in VLSI design, you are adept at developing advanced SRAM, Register File, and ROM solutions that balance high performance, low power, and area efficiency. Your keen analytical abilities enable you to resolve complex challenges creatively, and you are comfortable working both independently and as part of a cross-function al team. You excel at managing multiple priorities and are proactive in identifying and addressing issues that may impact project timelines. Your leadership skills empower you to coordinate and motivate teams, ensuring the successful completion of challenging projects in record time. With a customer-focus ed mindset, you communicate effectively with both internal and external stakeholders, leveraging your technical expertise to deliver innovative solutions. Your commitment to continuous learning keeps you at the forefront of industry trends, and your mastery of scripting and automation streamlines development processes. Above all, you are motivated by the opportunity to shape the future of silicon technology and make a tangible impact on the world. What You'll Be Doing: Developing multiport SRAM/Register file architectures and implementing cutting-edge circuit design techniques. Leading schematic entry, simulation of major blocks, layout planning, and collaborating with CAD teams for verification and model generation. Designing and optimizing low-power, area-efficient embedded memory circuits, including SRAM and register files. Learning and applying advanced skills in transistor-lev el memory compiler design and automation. Driving resolution of complex technical issues with creative problem-solvin g and cross-function al collaboration. Interacting with senior technical personnel, customers, and cross-site teams to deliver high-quality memory IP solutions. Coordinating and facilitating the daily activities of project teams, ensuring alignment with project goals and schedules. Prioritizing workloads and proactively communicating issues impacting productivity to stakeholders. The Impact You Will Have: Accelerate the development of industry-leadi ng embedded memory IP, enabling next-generatio n integrated circuits. Enhance the performance, power efficiency, and area optimization of Synopsys' memory compiler offerings. Drive successful project execution by providing technical leadership and fostering a culture of innovation. Strengthen Synopsys' position as a trusted partner for semiconductor companies worldwide. Contribute to the continuous improvement of design methodologies and automation flows. Mentor and guide junior engineers, cultivating technical excellence within the team. Promote customer satisfaction by delivering reliable, high-quality memory solutions on time. What You'll Need: BE /B.Tech/ME/M.T ech/MS in Electrical & Electronics Engineering from a premier institute/univ ersity. Minimum 4 years of hands-on experience in VLSI Design, with a focus on embedded memory architecture and circuit design. Deep understanding of SRAM/Register File architectures and advanced custom circuit implementation s. Experience working with advanced technology nodes, including FinFET and deep submicron processes. Proficiency in scripting languages such as Perl and Python for design automation. Expertise in full embedded memory design flow: from architecture, circuit design, and physical implementation to compiler automation, characterizati on, timing, and model generation. Solid knowledge of CMOS fundamentals, fabrication processes, and digital/analog circuit fundamentals. Understanding of RC circuits, Boolean function realization, transfer function analysis, and stability. Who You Are: An innovative thinker with strong analytical and problem-solvin g skills. Self-driven, able to manage multiple tasks with minimal supervision. Effective communicator, adept at networking and collaborating with diverse teams and stakeholders. Customer-focus ed, with a commitment to delivering high-quality solutions. Leadership qualities with the ability to guide, motivate, and mentor team members. Adaptable and eager to learn new technologies and methodologies. Detail-oriente d and proactive in addressing project challenges and risks. The Team You'll Be A Part Of: You'll join the Embedded Memory and Logic Team in Noida, a key part of Synopsys' Solutions Group. This dynamic team is responsible for the end-to-end development of standard and custom embedded SRAMs/ROMs, delivering both functional and physical memory views through innovative compiler IP for complex integrated circuits. The group values technical excellence, collaboration, and continuous learning, working closely with global teams to drive memory innovation and deliver world-class solutions to our customers. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Category Interns/Temp Hire Type Intern Job ID 9215 Date Posted 15/07/2025 We Are: Drive technology innovations that shape the way we live and connect. Our technology drives the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life. From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world. Apprenticeship Experience: At Synopsys, apprentices dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide—and having fun in the process! You'll have the freedom to

Mandatory Skills: ASIC Design Primary Skills:RTL, Coding, Design, IP Design, SOC Development, Lint, CDC, Micro Architecture Experience in: PCIe/DDR/Ethernet Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium Make flow, Perl, Shell, Python I2C, UART/SPI

Primary Skills; Physical Design Methodologies / submicron technology of 28nm and lower Mandatory Skills: VLSI Physical Place and Route Must have: Synopsys/Cadence tools (Innovus, ICC2, Primetime, PT-PX, Calibre) Programming in Tcl/Tk/Perl

Bangalore,Karnataka,India Job ID 768648 Grow with us About this opportunity We are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrow's mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport – to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we don't just follow industry trends—we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, you'll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. As part of our global R&D organization, you'll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. What you will do Leadership Opportunity: Take charge of delivering high-impact ASIC IP solutions, ensuring alignment with broader project goals and requirements. Creative Freedom: Engage in an environment that champions innovation and critical thinking. You'll have the autonomy to explore advanced verification technologies alongside skilled experts. Global Influence: Contribute to projects that transform industries, advance digital economies, and enhance global communication, bridging gaps between people, systems, and information worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you perform at your best without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. An international work environment with opportunities for professional growth and development. A collaborative and inclusive culture that values diversity and innovation. A competitive compensation and benefits package. You will bring Key Responsibilities: Driving Execution Be responsible for IP (Intellectual Property) development section, including design and verification at the subsystem, block, and/or sub-block levels. Act as an interface towards stakeholders and vendors. Ensure good collaboration with other teams both on-site and cross-site Team Recruiting and Development Recruit and develop team designers and verifiers Manage individual and team performance Develop a motivating, customer oriented and exciting work environment Broader Responsibilities Be an active contributor to the leadership teams of that global functional department that you collaborate with as well as the local IP development department Act as the chair and participate in steering groups inside organization or towards external suppliers Drive internal efficiency, cost effectiveness via new or alignment of existing ways of working, across all other design sections continuous improvements and automation Set goals, follow-up and strategically evolving section towards vison Required Qualification Bachelor’s degree in electrical or computer engineering Proven leadership experience in all the following areas IP development team management (at least 3 years) building a motivated, innovative, empowered team coaching and mentoring written and verbal communications and presentations ability to build on cultural diversity and collaborate across teams, organizations and sites working with external suppliers agile ways of working and project management 8+ years’ experience as an individual contributor designer or verifier Additional Requirements: Experience with Cadence and Synopsys design and verification suites. Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality. Strong focus on meeting project deadlines and deliverables. Proficient in English, with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). Experience designing one or more of the following hardware domains: AMBA-based designs especially AXI and CHI. ARM-based real-time microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols. Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.) Why join Ericsson? At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next. What happens once you apply?

As a digital chip designer and customer support specialist, you will collaborate closely with customers to understand their design requirements and provide technical support throughout the implementation phase. Your responsibilities will include identifying, troubleshooting, and resolving design issues such as DRC, LVS, and other verification checks to ensure successful tapeout. You will be hands-on in utilizing relevant EDA tools like Innovus, IC compiler, Calibre, PrimeTime, etc. Additionally, you will assist in the tapeout process, ensuring that all design files are correctly prepared and submitted for manufacturing. To excel in this role, you must hold a Bachelor's or Master's degree in Electrical Engineering or a related field. A minimum of 8 years of proven experience as a digital chip designer and customer support professional is required. Strong problem-solving skills and the ability to work effectively under pressure are crucial attributes for success in this position. Excellent communication and interpersonal skills will be essential in engaging with customers and collaborating effectively. Proficiency in EDA tools such as Cadence, Synopsys, and Mentor Graphics is a must to meet the demands of this role.,

Greetings from Eximietas Design! We are actively seeking to hire Senior Analog Layout Design Engineers / Leads with 7-15 years of experience in lower FINFET technology nodes, preferably TSMC 5nm, to join our team in Bangalore, Hyderabad, or Visakhapatnam. A notice period of 30 days or less is preferred for this position. As a Senior Analog Layout Design Engineer/Lead at Eximietas Design, you will be responsible for contributing to cutting-edge analog layout design. Your expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization will be essential. You should have a solid understanding of how layout impacts circuit performance, such as speed and area, and the ability to implement layouts that meet tight design constraints while delivering high quality results. Hands-on experience with CADENCE/SYNOPSYS layout tools and flows is required, and familiarity with scripting languages (PERL/SKILL) is a plus. Strong communication skills and experience collaborating with cross-functional teams are also key to success in this role. If you are interested in this opportunity or know someone suitable, please send your updated resume to maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We are looking forward to connecting with talented engineers who are passionate about pushing the boundaries of analog layout design. Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam maruthiprasad.e@eximietas.design +91 8088969910.,

As a Senior Digital Design Verification Engineer at Micron Technology, you will play a crucial role in ensuring the correctness and robustness of various digital designs through thorough testing and verification processes. Your responsibilities will encompass a wide range of tasks, including understanding design specifications, developing verification plans, creating testbenches, test cases, and verification environments, as well as performing functional, regression, and performance testing. You will collaborate closely with the digital design team to debug test cases, deliver accurate designs, and identify verification holes to progress towards tape-out. In this role, you will be expected to have a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, along with at least 10 years of experience in digital design verification. Proficiency in verification languages such as SystemVerilog, UVM, and VHDL is essential, as well as a strong understanding of digital design principles and methodologies. Experience with industry-standard verification tools and formal verification techniques, along with knowledge of scripting languages like Python, Perl, or TCL, will be beneficial for success in this position. As part of the Micron Technology team, you will have the opportunity to work on cutting-edge memory and storage solutions that drive advancements in artificial intelligence and 5G applications. The company's relentless focus on technology leadership and operational excellence ensures a rich portfolio of high-performance memory and storage products delivered through the Micron and Crucial brands. If you are looking to be part of an innovative and dynamic organization that values continuous improvement and collaboration, Micron Technology is the place for you. To explore career opportunities at Micron Technology and learn more about how our innovations are shaping the future of information technology, please visit micron.com/careers. For any assistance with the application process or to request reasonable accommodations, you can reach out to hrsupport_india@micron.com. Micron Technology is committed to upholding international labor standards and prohibits the use of child labor in compliance with all applicable laws and regulations.,

About Us: At Dabster, we specialize in connecting top talent with leading global companies. We are currently seeking a " Design Verification Engineer " to join one of our key clients on a Fixed term tract with strong potential for extension. Our mission is to be the foremost recruitment specialist in securing exceptional talent for a diverse range of global clients. This is a UK/EU-based role, and visa sponsorship will be provided for eligible candidates. Who Will You Work With: A leading semiconductor and software design company specializing in energy-efficient microprocessor architectures. Its processor designs power the vast majority of smartphones, tablets, embedded systems, and IoT devices worldwide. By licensing its technology to global tech giants, the company plays a pivotal role in the modern computing and electronics ecosystem. About the Role: As a Design Verification Engineer , you should be expertise in SystemVerilog and UVM to develop and execute comprehensive verification plans, build UVM testbenches, and perform block to SoC-level verification. Proficiency in simulation tools, scripting for automation, and advanced debug techniques is essential. Key Responsibilities: Define and execute comprehensive verification plans based on design specifications and architecture. Develop and maintain UVM-based testbenches and environments. Write, simulate, and debug testcases using SystemVerilog. Perform block-level and subsystem-level verification, ensuring alignment with functional and performance targets. Run regression tests, analyse coverage reports, and identify design bugs. Collaborate with RTL designers, integration engineers, and system architects to ensure high-quality deliverables. Support gate-level simulations, formal verification, and other advanced verification methodologies. Preferred Skills: Proven experience with SystemVerilog and UVM methodology. Strong understanding of digital design concepts and verification principles. Experience with tools such as Synopsys VCS, Cadence Xcelium , or Mentor Questa . Familiarity with scripting languages like Python, Perl, or Tcl for automation. Solid grasp of coverage-driven verification and assertion-based verification techniques. Experience with regression management , debug tools like Verdi , and waveform analysis . Exposure to IP/subsystem/SoC-level verification is a plus. What We Offer: Contract Type: 6-months contract with possible extension Remote Flexibility: Fully remote Collaborative Environment: Work closely with industry-leading teams and contribute to cutting-edge projects. This is a UK/EU-based role, and visa sponsorship will be provided for eligible candidates. How to apply: Please submit your CV with relevant experience via LinkedIn Easy Apply or directly to Sushma.gungi@dabster.net. Interview Process: The process typically includes one or two rounds of technical interviews followed by a business alignment discussion.

We Are: Drive technology innovations that shape the way we live and connect. Our technology drives the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life. From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world. Apprenticeship Experience: At Synopsys, Apprentices dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide—and having fun in the process! You'll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path. Join us and start shaping your future today! Mission Statement: Our mission is to fuel today’s innovations and spark tomorrow’s creativity. Together, we embrace a growth mindset, empower one another, and collaborate to achieve our shared goals. Every day, we live by our values of Integrity, Excellence, Leadership, and Passion, fostering an inclusive culture where everyone can thrive—both at work and beyond. What You’ll Be Doing: Designing, developing, and troubleshooting the core VC-Static engine. Collaborating closely with other teams both locally and globally. Designing and developing state-of-the-art EDA tools, involving the development of new and innovative algorithms in the area of electronic design automation. What You’ll Need: Should be a graduate engineer in Computer Science or Electronics Strong analytical and problem-solving skills. Proficiency in programming languages such as C/C++. Familiarity with ASIC design flow and the EDA tools and methodologies used therein is a plus. Excellent communication and teamwork abilities. Self-motivation, self-discipline, and the ability to set personal goals and work consistently towards them in a dynamic environment. Key Program Facts: Program Length: 12 months Location: Noida, India Working Model: On-Site Full-Time/Part-Time: Full-Time. Type of Internship: Apprenticeship Start Date: July/August 2025 Equal Opportunity Statement: Synopsys is committed to creating an inclusive workplace and is an equal opportunity employer. We welcome all qualified applicants to apply, regardless of age, color, family or medical leave, gender identity or expression, marital status, disability, race and ethnicity, religion, sexual orientation, or any other characteristic protected by local laws. If you need assistance or a reasonable accommodation during the application process, please reach out to us.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and innovative engineer dedicated to pushing the boundaries of semiconductor technology. You thrive in a collaborative environment where your expertise in embedded memory architectures and deep submicron technologies is highly valued. With a strong foundation in VLSI design, you are adept at developing advanced SRAM, Register File, and ROM solutions that balance high performance, low power, and area efficiency. Your keen analytical abilities enable you to resolve complex challenges creatively, and you are comfortable working both independently and as part of a cross-functional team. You excel at managing multiple priorities and are proactive in identifying and addressing issues that may impact project timelines. Your leadership skills empower you to coordinate and motivate teams, ensuring the successful completion of challenging projects in record time. With a customer-focused mindset, you communicate effectively with both internal and external stakeholders, leveraging your technical expertise to deliver innovative solutions. Your commitment to continuous learning keeps you at the forefront of industry trends, and your mastery of scripting and automation streamlines development processes. Above all, you are motivated by the opportunity to shape the future of silicon technology and make a tangible impact on the world. What You'll Be Doing: Developing multiport SRAM/Register file architectures and implementing cutting-edge circuit design techniques. Leading schematic entry, simulation of major blocks, layout planning, and collaborating with CAD teams for verification and model generation. Designing and optimizing low-power, area-efficient embedded memory circuits, including SRAM and register files. Learning and applying advanced skills in transistor-level memory compiler design and automation. Driving resolution of complex technical issues with creative problem-solving and cross-functional collaboration. Interacting with senior technical personnel, customers, and cross-site teams to deliver high-quality memory IP solutions. Coordinating and facilitating the daily activities of project teams, ensuring alignment with project goals and schedules. Prioritizing workloads and proactively communicating issues impacting productivity to stakeholders. The Impact You Will Have: Accelerate the development of industry-leading embedded memory IP, enabling next-generation integrated circuits. Enhance the performance, power efficiency, and area optimization of Synopsys' memory compiler offerings. Drive successful project execution by providing technical leadership and fostering a culture of innovation. Strengthen Synopsys' position as a trusted partner for semiconductor companies worldwide. Contribute to the continuous improvement of design methodologies and automation flows. Mentor and guide junior engineers, cultivating technical excellence within the team. Promote customer satisfaction by delivering reliable, high-quality memory solutions on time. What You'll Need: BE/B.Tech/ME/M.Tech/MS in Electrical & Electronics Engineering from a premier institute/university. Minimum 4 years of hands-on experience in VLSI Design, with a focus on embedded memory architecture and circuit design. Deep understanding of SRAM/Register File architectures and advanced custom circuit implementations. Experience working with advanced technology nodes, including FinFET and deep submicron processes. Proficiency in scripting languages such as Perl and Python for design automation. Expertise in full embedded memory design flow: from architecture, circuit design, and physical implementation to compiler automation, characterization, timing, and model generation. Solid knowledge of CMOS fundamentals, fabrication processes, and digital/analog circuit fundamentals. Understanding of RC circuits, Boolean function realization, transfer function analysis, and stability. Who You Are: An innovative thinker with strong analytical and problem-solving skills. Self-driven, able to manage multiple tasks with minimal supervision. Effective communicator, adept at networking and collaborating with diverse teams and stakeholders. Customer-focused, with a commitment to delivering high-quality solutions. Leadership qualities with the ability to guide, motivate, and mentor team members. Adaptable and eager to learn new technologies and methodologies. Detail-oriented and proactive in addressing project challenges and risks. The Team You'll Be A Part Of: You'll join the Embedded Memory and Logic Team in Noida, a key part of Synopsys' Solutions Group. This dynamic team is responsible for the end-to-end development of standard and custom embedded SRAMs/ROMs, delivering both functional and physical memory views through innovative compiler IP for complex integrated circuits. The group values technical excellence, collaboration, and continuous learning, working closely with global teams to drive memory innovation and deliver world-class solutions to our customers. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Senior Standard Cell Layout Engineer Standard Cell Layout Designer Digital Layout Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and highly motivated professional with a robust technical background in standard cells layout design. Your passion for excellence and precision drives you to create layouts that set the standard for quality and manufacturability. You thrive in collaborative, cross-functional environments, seamlessly working with circuit designers, verification engineers, and other stakeholders to deliver optimized layout solutions. Your expertise in industry-leading EDA tools—such as Cadence Virtuoso or Synopsys Custom Compiler—enables you to tackle complex digital circuit layouts with efficiency and accuracy. Your systematic approach and strong problem-solving skills allow you to navigate technical challenges with ease, always seeking innovative ways to enhance design methodologies and best practices. You are deeply familiar with physical verification processes and design rule checks, ensuring that every layout you deliver meets stringent quality and manufacturability standards. Your curiosity and commitment to lifelong learning keep you updated on the latest advancements in standard cell layout design, making you an invaluable resource for your team. You communicate effectively, embrace feedback, and are eager to contribute to a culture of continuous improvement and shared success. What You’ll Be Doing: Collaborate with cross-functional teams to develop and implement layout designs for digital circuits, ensuring alignment with project goals and timelines. Create and optimize complex standard cell layouts using industry-standard EDA tools such as Cadence Virtuoso or Synopsys Custom Compiler. Perform thorough physical verification and design rule checks (DRC/LVS) to guarantee design integrity and manufacturability. Work closely with circuit designers to understand design specifications, constraints, and performance targets, translating them into robust layouts. Contribute to the development, documentation, and refinement of layout design methodologies, flows, and best practices within the team. Remain up to date with industry trends, emerging technologies, and advancements in standard cell layout design, sharing knowledge with peers. The Impact You Will Have: Deliver high-quality layout designs that form the foundation of Logic Libraries IP development, essential for advanced SOC subsystems. Drive innovation in layout design methodologies, contributing to Synopsys’ leadership in the industry. Ensure that all designs meet or exceed manufacturability and reliability standards, reducing risk and time-to-market for key products. Collaborate effectively with circuit designers and verification teams to meet challenging design specifications and project milestones. Contribute to the overall success and reputation of the Logic Libraries IP group through your technical excellence and teamwork. Mentor and support junior team members, fostering a culture of knowledge-sharing and continuous improvement. What You’ll Need: Bachelor’s or master’s degree in electronics engineering or a related field. Minimum2 years of hands-on experience in standard cells layout design for digital circuits. Proficiency with industry-standard EDA tools, including Cadence Virtuoso or Synopsys Custom Compiler. Deep knowledge of layout design methods, techniques, and methodologies for high-performance and robust standard cells. Experience with physical verification tools such as ICC2, including DRC and LVS checks. Strong analytical and systematic problem-solving skills, with a detail-oriented mindset. Ability to work effectively in a collaborative, team-driven environment. Excellent communication and interpersonal skills, with a willingness to learn and share knowledge. Who You Are: A collaborative team player who values open communication and shared goals. Detail-oriented, with a commitment to delivering high-quality and reliable work. Curious and proactive, embracing continuous learning and professional development. Adaptable and resilient in the face of technical challenges and evolving requirements. Passionate about innovation, with a drive to improve processes and methodologies. Self-motivated, organized, and able to manage multiple priorities in a fast-paced environment. The Team You’ll Be A Part Of: You’ll join a dynamic and supportive Logic Libraries IP group focused on developing state-of-the-art standard cell libraries for advanced SOC subsystems. Our team thrives on collaboration, innovation, and technical excellence. We value diverse perspectives and foster an inclusive environment where every member’s contributions are recognized and celebrated. Together, we drive the success of Synopsys’ IP solutions, setting industry benchmarks and enabling our customers to achieve next-generation performance. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

We Are: Drive technology innovations that shape the way we live and connect. Our technology drives the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life. From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world. Apprenticeship Experience: At Synopsys, apprentices dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide—and having fun in the process! You'll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path. Join us and start shaping your future today! Mission Statement: Our mission is to fuel today's innovations and spark tomorrow's creativity. Together, we embrace a growth mindset, empower one another, and collaborate to achieve our shared goals. Every day, we live by our values of Integrity, Excellence, Leadership, and Passion, fostering an inclusive culture where everyone can thrive—both at work and beyond. What You’ll Be Doing: Developing simulation models and platforms in SystemC for early software development and validation. Providing technical support to customers and participating in the development of flows and methodologies in Synopsys’ Virtualizer tools. Working directly with leading customers in the areas of AI, Automobile, Cloud, Networking, etc. Maintain the Jenkins and nightly test flows for VDK quality assesment and management. What You’ll Need: Graduate in BE/BTech or equivalent in Computer Science, Electrical or Electronics Engineering, or related fields. Proficiency in C/C++. Knowledge of Linux environment and scripting in Shell, Tcl, Python. Knowledge of computer architecture. Understanding of SystemC and TLM (Preferred). Knowledge of Embedded Software design (Preferred). Strong written and verbal communication skills. Strong problem-solving abilities. Good interpersonal skills. Key Program Facts: Program Length: 12 months Location: Noida, India Working Model: Onsite Full-Time/Part-Time: Full-time Start Date: August/ September 2025 Equal Opportunity Statement: Synopsys is committed to creating an inclusive workplace and is an equal opportunity employer. We welcome all qualified applicants to apply, regardless of age, color, family or medical leave, gender identity or expression, marital status, disability, race and ethnicity, religion, sexual orientation, or any other characteristic protected by local laws. If you need assistance or a reasonable accommodation during the application process, please reach out to us.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are passionate about solving complex problems at the intersection of software engineering and semiconductor technology. Your curiosity drives you to explore new solutions and approaches, especially in high-impact areas such as memory characterization and automation. With a strong foundation in computer science, electronics, or a related discipline, you thrive in environments where collaboration, innovation, and technical excellence are valued. You are detail-oriented, analytical, and always eager to learn and adapt as technology evolves. You take pride in building robust, maintainable code and are committed to delivering quality solutions that make a tangible difference. As a team player, you communicate clearly, seek feedback, and contribute to a culture of openness and continuous improvement. Whether working independently or in cross-functional teams, you bring a sense of accountability and ownership to your work. You are excited by the prospect of impacting the next generation of semiconductor products and motivated by the opportunity to drive productivity and efficiency through automation. If you are ready to challenge yourself, innovate, and help shape the future of memory IP development, Synopsys is the place for you. What You’ll Be Doing: Designing and developing robust software tools for automating memory characterization workflows, including simulation setup, data extraction, and report generation. Collaborating closely with memory design, CAD, and validation teams to understand requirements and implement solutions that enhance accuracy, scalability, and performance of characterization flows. Integrating EDA tools such as SPICE simulators, Liberty format analyzers, and waveform viewers into advanced automation flows. Optimizing simulation execution on large compute clusters and efficiently managing the vast data sets generated during memory characterization. Building modular, maintainable, and high-performance codebases using C++, Python, Shell/TCL scripts, and industry-standard software engineering tools. Contributing to the development of test infrastructure, debugging tools, and validation methodologies to ensure the correctness and consistency of characterization results. Participating in code reviews, providing innovative ideas, and driving improvements in productivity and tool efficiency across the team. The Impact You Will Have: Accelerate the delivery of high-performance memory compilers for advanced technology nodes (e.g.,5nm,3nm, and beyond), enabling cutting-edge products. Streamline and automate engineering flows, reducing manual effort and enhancing productivity for multidisciplinary teams. Enhance the quality and reliability of characterization data, directly contributing to Process Design Kits (PDKs), EDA tools, and customer deliverables. Drive innovations that improve cost-efficiency, scalability, and competitiveness of Synopsys’ global IP portfolio. Contribute to the continuous improvement of internal infrastructure, processes, and best practices, fostering a culture of technical excellence. Empower internal and external customers through robust, user-friendly tools that enable faster, more reliable delivery of semiconductor solutions. What You’ll Need: B.Tech/MTech in Computer Science, Electronics, or a related field. At least 2 years of experience in software development or EDA tool development, preferably within the semiconductor industry. Proficiency in C/C++, TCL, Python, SQL, and scripting languages such as Shell. Experience with debugging tools such as GDB, and memory debugging tools like Valgrind or Purify. Strong understanding of machine learning algorithms (supervised, unsupervised, reinforcement learning). Hands-on experience with Python ML libraries such as scikit-learn, TensorFlow, or PyTorch. Who You Are: Detail-oriented with excellent analytical and problem-solving abilities. Possess strong verbal and written communication skills, able to articulate complex technical concepts clearly. A collaborative team player who thrives in cross-functional and multicultural environments. Demonstrates accountability and ownership in delivering high-quality work. An innovative thinker passionate about technology, automation, and continuous learning. The Team You’ll Be A Part Of: You’ll be joining a dynamic and forward-thinking team dedicated to developing and maintaining advanced memory characterization tools for next-generation semiconductor technologies. The team is known for its strong collaboration across domains such as software, CAD, and design, and for fostering a culture of inclusivity and openness. Committed to continuous improvement, the team values innovation and feedback while delivering high-quality, impactful solutions that empower both internal teams and external customers. Together, you will be driving the future of memory IP development by solving complex challenges and pushing the boundaries of performance, scalability, and automation. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.