Category Engineering Hire Type Employee Job ID 9280 Remote Eligible No Date Posted 16/02/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: An experienced and visionary ASIC Verification Engineer, Architect who is passionate about driving the future of semiconductor technology. You possess deep functional knowledge and expertise in verification methodologies, and you thrive in an environment where you can influence and implement strategic goals. Your background includes a comprehensive understanding of serial protocols such as PCIe/CXL, UCIe etc. You can define and execute Testbench architecture for protocols such as PCIe/CXL. You are a proactive problem solver, capable of working with minimal oversight, and you excel in communicating complex technical concepts to a diverse audience. Your leadership skills enable you to guide and mentor teams, fostering innovation and excellence in all your projects. What You’ll Be Doing: Defining and developing ASIC RTL verification at both chip and block levels. Creating and executing verification plans for complex digital designs, particularly focusing on PCIe/CXL protocols. Collaborating with cross-functional teams to ensure seamless integration and functionality of designs. Utilizing advanced verification methodologies and tools to achieve high-quality results. Mentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement. Communicating with internal and external stakeholders to align on project goals and deliverables. The Impact You Will Have: Enhancing the reliability and performance of Synopsys’ digital verification processes. Improving time-to-market for robust Synopsys Interface IP controller through efficient verification methodologies. Mentoring and nurturing a highly skilled verification team, elevating overall project quality. Influencing strategic decisions that shape the future of Synopsys’ capabilities. Ensuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements. What You’ll Need: Extensive experience in ASIC RTL verification. In-depth knowledge of PCIe, CXL , UCIe and similar IO protocols. Proficiency in advanced digital design verification tools and methodologies. Strong problem-solving skills and the ability to work independently. Excellent communication skills for effective collaboration with diverse teams. Experience of 15+ years in relevant domain. Who You Are: A mentor who fosters talent and encourages innovation. A proactive problem solver who thrives in complex environments. An effective communicator with the ability to convey technical concepts to a broad audience. A team player who values collaboration and diversity. Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Category Engineering Hire Type Employee Job ID 10482 Remote Eligible No Date Posted 13/04/2025 Sr, Staff ASIC Verification Engineer, Noida Location: Key responsibilities: Identify verification environment requirements from its various sources (Specifications, Design functionality, Interfaces, etc …) Generate verification test plan, verification environment documentation and test environment usage documentation Define, develop, and verify complex UVM verification environments Evaluates and exercises various aspects of the development flow. May include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modelling, and verification coverage metrics (functional coverage and code coverage) Collaborate with architect, designers , VIP team to accomplish tasks. Identify design problems, possible corrective actions and/or inconsistencies on documented functionality Work with peers to improve methodologies and improve execution efficiency. Adhere to quality standards and good test and verification practices. Work as a lead, mentor junior engineers, and help them in debugging complex problems. Able to Support Customer issues, by their reproduction and analysis. Should be able multitask between different activities. Key Qualifications Proven desire to learn and explore new state of the art technologies Demonstrate good written and spoken English communication skills Demonstrate good review and problem-solving skills Knowledgeable with Verilog, VHDL and/or SystemVerilog Knowledgeable with scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plus Understanding of verification methodology such as UVM . Good organization and communication skills Be a solution provider. 8+ years of relevant experience At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Category Engineering Hire Type Employee Job ID 10677 Remote Eligible No Date Posted 16/04/2025 Alternate Job Titles: Sr. Application Engineer Senior Technical Support Engineer Senior Customer Success Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled professional with a passion for technology and customer success. You have a solid background in Physical Implementation RTL-GDS and are experienced in debugging and resolving Synth & PnR implementation challenges. You thrive on solving critical design challenges and are dedicated to enhancing QOR metrics to achieve best-in-class PPA and TAT targets. Your excellent communication skills enable you to effectively interface with customers and business unit personnel. You are self-motivated, detail-oriented, and committed to continuous learning and improvement. What You’ll Be Doing: Working on the latest Synopsys implementation technologies (Machine Learning, Physical Synthesis, Multi Source CTS) to solve complex PPA challenges faced by Synopsys customers. Developing and debugging RTL-GDS implementation methodologies and flows. Providing technical solutions by identifying design and/or EDA tool issues and offering appropriate resolutions for customers. Translating findings into requirements for R&D to improve tool behaviors with enhancements as adaptive long-term solutions. Deploying new technologies on the latest EDA versions and enabling customers to migrate to newer versions to achieve the best PPA. Proactively identifying customers' pain points and developing innovative solutions to address them. Collaborating closely with Synopsys R&D and product development teams to develop future technologies. Acting as a customer advocate while communicating with in-house R&D and serving as a product brand ambassador when engaging with customers. The Impact You Will Have: Driving customer satisfaction and success through exceptional technical support and solutions. Enhancing product quality by providing valuable feedback to the R&D team. Contributing to the continuous improvement of Synopsys tools and methodologies. Supporting the migration of customers to newer EDA versions, achieving optimal PPA. Strengthening relationships with customers and understanding their technical needs. Helping to displace competing implementation solutions through effective benchmarks. What You’ll Need: At least 2+ years of experience in Physical Implementation RTL-GDS. Experience in debugging and resolving Synth & PnR implementation challenges. Good exposure to methodology changes to achieve targeted PPA metrics for complex designs. Proficiency in Synopsys implementation tools is an advantage. Proficiency in scripting (Tcl, Unix, Perl). Excellent communication skills, including the ability to interface with customers and business unit personnel. Who You Are: Self-motivated and dedicated with excellent debugging skills. Customer-focused with a passion for delivering exceptional service. Analytical thinker with strong problem-solving abilities. Adaptable and able to work in a fast-paced, dynamic environment. Team player who collaborates effectively with colleagues and customers. The Team You’ll Be A Part Of: You will be part of a dynamic and innovative team focused on providing world-class technical support to our customers. Our team is dedicated to ensuring the successful adoption and implementation of Synopsys products, driving customer satisfaction, and contributing to the continuous improvement of our solutions. We work closely with the R&D and product development teams to deliver comprehensive support and technical expertise. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 10019 Date posted 03/17/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled R&D Staff Engineer passionate about pushing the boundaries of static low power verification products. With 5 to 8 years of experience in software engineering, you have honed your expertise in C/C++ and possess a robust understanding of data structures and algorithms. Your background in Electronic Design Automation (EDA) tools and methodologies, coupled with your knowledge of Verilog, SystemVerilog, and VHDL, positions you as a leader in your field. You are a proactive problem-solver with a keen eye for detail, and you thrive in collaborative environments where you can lead and inspire a team. Your self-motivation and discipline drive you to set and achieve personal goals consistently, and your commitment to quality ensures that your contributions make a significant impact. Based in Noida or Bangalore, you are ready to take on new challenges and help shape the future of technology. What You’ll Be Doing: Designing and developing state-of-the-art EDA tools with innovative algorithms. Collaborating with local and remote teams to ensure seamless integration and execution. Working directly with customers to understand requirements, provide online debugging, and track delivery and execution. Leading a small team of 2-3 members, guiding them through technical challenges and project milestones. Contributing to the continuous improvement of our static low power verification product. Exploring new architectures and leading the charge in developing cutting-edge solutions. The Impact You Will Have: Driving the development of advanced EDA tools, contributing to the efficiency and effectiveness of chip design. Enhancing the quality and reliability of our static low power verification product. Providing critical support to customers, ensuring their needs are met and fostering long-term relationships. Leading and mentoring junior engineers, fostering a culture of innovation and excellence within the team. Contributing to Synopsys' reputation as a leader in the semiconductor and EDA industries. Playing a pivotal role in the successful execution of projects, meeting deadlines, and exceeding expectations. What You’ll Need: Fluency in C/C++ with a strong background in data structures and algorithms. Experience with UPF and familiarity with Tcl and Python-based development on Unix (preferred). Knowledge of Verilog, SystemVerilog, and VHDL HDL (preferred). Experience with production code development on Unix/Linux platforms. Ability to develop new architectures and demonstrate strong leadership skills. Who You Are: You are a dynamic and innovative engineer with a passion for technology and a commitment to quality. You possess excellent problem-solving skills and the ability to think critically and creatively. As a self-motivated individual, you set personal goals and work diligently to achieve them. Your leadership skills enable you to guide and inspire your team, fostering a collaborative and productive work environment. You are detail-oriented, ensuring that your work meets the highest standards of quality and reliability. Your experience in EDA tools and methodologies, coupled with your knowledge of hardware description languages, positions you as a valuable asset to our team. The Team You’ll Be A Part Of: You will be part of the Static Verification team, a group of talented engineers dedicated to developing and enhancing our static low power verification products. This team collaborates closely with other departments, including design, development, and customer support, to ensure seamless integration and execution. Together, you will work on cutting-edge projects that push the boundaries of technology and contribute to the success of Synopsys and its customers. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Category Engineering Hire Type Employee Job ID 6624 Remote Eligible No Date Posted 09/03/2025 Alternate Job Titles: Functional Verification Engineer Pre-Silicon Verification Engineer Digital Design Verification Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a dynamic and enthusiastic individual with a strong drive to learn and excel in the field of digital verification. You have a keen eye for detail and a deep understanding of digital design and hardware description languages (HDL). With your expertise in functional verification, you are eager to contribute to the pre-silicon verification activities for high-speed interface IPs. You possess excellent problem-solving skills and can work effectively in a collaborative environment. Your proactive approach and strong communication skills enable you to work closely with digital designers to achieve desired coverage and ensure the highest quality of IPs. What You’ll Be Doing: Working on functional verification of high-speed serial link PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards. Studying IP/design blocks/firmware specifications and building/updating verification plans and test cases. Building/updating functional verification environments to execute test plans. Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs) as per verification plan needs. Performing simulation, random and direct stimulus development, and coverage review. Working closely with digital designers for debugging and achieving the desired coverage. The Impact You Will Have: Ensuring the accuracy and functionality of high-speed interface IPs, contributing to the development of cutting-edge technology. Enhancing the reliability and performance of Synopsys' products through meticulous verification processes. Driving innovation in the semiconductor industry by verifying complex digital designs. Collaborating with a team of skilled professionals to deliver high-quality IPs that meet industry standards. Improving the efficiency of the verification process through automation and advanced verification methodologies. Contributing to the overall success of Synopsys by ensuring the delivery of robust and reliable IPs to customers. What You’ll Need: B.Tech/M.Tech with 3+ years of relevant experience. Understanding of functional verification flow with awareness of verification tools and methodologies such as VMM, OVM/UVM, and System Verilog. Proficiency in scripting and automation using TCL, PERL, or Python. Strong debug and diagnostic skills. Experience in building and updating functional verification environments. Who You Are: An excellent communicator who can collaborate effectively with cross-functional teams. A proactive problem solver with a keen eye for detail. An enthusiastic learner with a passion for technology and innovation. A team player who thrives in a collaborative environment. A highly organized individual who can manage multiple tasks and priorities effectively. The Team You’ll Be A Part Of: You will be part of a dedicated and innovative team focused on the functional verification of high-speed interface IPs. Our team collaborates closely with digital designers and engineers to ensure the highest quality of IPs. We are committed to continuous learning and development, fostering an environment where creativity and innovation thrive. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 10769 Date posted 04/18/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a motivated and skilled engineer with 3-7 years of experience in emulation solutions development. You bring a strong foundation in programming concepts using C/C++ and an understanding of digital design. Your expertise includes HDL languages such as System Verilog and Verilog, and you are familiar with protocols like AXI, AMBA, JTAG, AVB, CAN, and TSN. You thrive in collaborative environments and have excellent communication skills. Your educational background includes a B.E, B.Tech, or M.Tech in Electronic & Communication or Computer Science Engineering. You are passionate about developing cutting-edge emulation solutions for semiconductor customers and are eager to engage in both software development and synthesizable RTL development. What You’ll Be Doing: Developing emulation solutions for industry-standard protocols such as AXI, AMBA, JTAG, AVB, CAN, and TSN. Engaging in software development using C/C++ and synthesizable RTL development using Verilog. Verifying emulation solutions to ensure they meet the highest standards of quality and performance. Interacting with customers during the deployment and debugging phases to provide technical support and ensure successful implementation. Collaborating with cross-functional teams to integrate emulation solutions with other Synopsys products and technologies. Continuously improving and optimizing emulation solutions to meet evolving industry needs and standards. The Impact You Will Have: Enhancing the efficiency and performance of semiconductor design processes through advanced emulation solutions. Contributing to the development of high-performance silicon chips and software content that drive technological innovation. Supporting semiconductor customers in overcoming design and verification challenges, leading to successful product launches. Improving the reliability and functionality of emulation solutions, thereby increasing customer satisfaction and trust in Synopsys products. Driving continuous improvement and innovation within the emulation solutions domain. Facilitating seamless integration of emulation solutions with other Synopsys technologies, enhancing overall product offerings. What You’ll Need: Strong programming skills in C/C++ and understanding of OOPS concepts. Good understanding of digital design concepts. Knowledge of HDL languages such as System Verilog and Verilog. Experience with scripting languages like Perl or TCL is a plus. Understanding of ARM architecture is an added advantage. Knowledge of UVM and functional verification will be a plus. Who You Are: A team player with excellent communication skills. Detail-oriented and capable of working independently. Adaptable and eager to learn new technologies and methodologies. Proactive in identifying and solving problems. Passionate about delivering high-quality solutions. The Team You’ll Be A Part Of: You will be part of a dynamic and innovative team focused on developing state-of-the-art emulation solutions for semiconductor customers. The team collaborates closely with other engineering groups within Synopsys to ensure seamless integration and optimal performance of our products. We value creativity, continuous learning, and a commitment to excellence. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 10470 Date posted 04/04/2025 The candidate will be part of the Static Verification team, a group of talented engineers dedicated to developing and enhancing platform for our static verification products. This team collaborates closely with other departments, including design, development, and customer support, to ensure seamless integration and execution. Together, the candidate will work on cutting-edge projects that push the boundaries of technology and contribute to the success of Synopsys and its customers. Person will work in platform team of static verification. Platform team provides support to various apps which are part of static verification. The hired candidate will provide features and support needed for successful deployment and ongoing business for apps of static verification. He might also work in developing GenAI application related to static platform. Technical competencies required for the role Strong hands-on experience in C/C++ based Object Oriented large and complex enterprise software development. Strong background in Design Patterns, Data Structure, Algorithms , and programming concepts. Well versed with Software Engineering and development processes. Experience with popular AI/ML frameworks (e.g., TensorFlow, PyTorch) is desirable. Experience with production code development on Unix/Linux platforms. Ability to develop new architectures and demonstrate strong leadership skills. Ability to troubleshoot, debug, and support software applications. Good analysis and problem-solving skills. 4+ years of software development experience. Preferable skills Experience in EDA/AI/ML research and development Exposure to Tcl, Python, Shell scripting and/or Vim Exposure to developer tools such as gdb, Valgrind, Visual Studio and Eclipse. Exposure with source code control tool like Perforce, Clearmake, CVS or Git . At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Category Engineering Hire Type Employee Job ID 9020 Remote Eligible No Date Posted 25/03/2025 ASIC Verification- Principal Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned verification engineer with a passion for cutting-edge technology. With a BSEE in Electrical Engineering and over 10 years of relevant experience, or an MSEE with over 8 years, you bring a wealth of knowledge in developing System Verilog based test environments, implementing test plans, and extracting verification metrics. You possess strong HVL coding skills and hands-on experience with industry-standard simulators such as VCS, NC, or MTI, and waveform-based debugging tools. Your familiarity with verification methodologies like VMM, OVM, or UVM is solid, and you have a deep understanding of protocols such as AMBA, SD/eMMC, MIPI-I3C/UFS/Unipro, Ethernet, DDR, PCIe, and USB. Your experience with Scatter Gather DMA and exposure to serial protocols like SPI/I2C/I2S/UART are highly valued. Additionally, you are proficient in scripting languages such as Perl, TCL, or Python, and have knowledge of HDLs like Verilog. Your exposure to VC Formal and IP design and verification processes, including VIP development, is an added advantage. You exhibit excellent written and oral communication skills, demonstrate strong analytical and problem-solving abilities, and show high levels of initiative. This role is not open for college fresh grads and requires prior industry experience. What You’ll Be Doing: Specify, design/architect, and implement state-of-the-art verification environments for the Synopsys family of synthesizable cores. Perform verification tasks for IP cores, ensuring they meet the highest standards of quality. Collaborate closely with RTL designers and be part of a global team of expert verification engineers. Work on next-generation AMBA protocols and serial protocols for commercial, enterprise, and automotive applications. Engage in test planning, test environment coding at both unit and system levels, test case coding and debugging, and FC coding and analysis. Manage regression and meet quality metric goals. The Impact You Will Have: Ensure the reliability and performance of Synopsys IP cores, contributing to the success of our cutting-edge products. Drive innovations in verification methodologies, enhancing the efficiency and effectiveness of our processes. Collaborate with a global team to deliver high-quality solutions that meet the needs of our customers. Support the development of next-generation technologies that will shape the future of various industries. Contribute to the continuous improvement of verification practices and standards within the organization. Play a key role in the successful delivery of IP cores for commercial, enterprise, and automotive applications. What You’ll Need: BSEE in Electrical Engineering with 10+ years of relevant experience or MSEE with 8+ years of relevant experience. Experience in developing System Verilog based test environments and implementing test plans. Strong HVL coding skills and hands-on experience with industry-standard simulators and waveform-based debugging tools. Familiarity with verification methodologies such as VMM, OVM, or UVM. Knowledge of protocols such as AMBA, SD/eMMC, MIPI-I3C/UFS/Unipro, Ethernet, DDR, PCIe, and USB. Who You Are: Excellent written and oral communication skills. Strong analytical and problem-solving abilities. High levels of initiative and the ability to work independently. Collaborative mindset with the ability to work effectively in a global team environment. Detail-oriented with a focus on quality and continuous improvement. The Team You’ll Be A Part Of: You will be part of the R&D in Solutions Group at our Bangalore Design Center, India. This dynamic team focuses on IP verification and works on technically challenging IP cores using the latest verification methodologies and flows. You will collaborate with RTL designers and verification engineers across multiple sites, contributing to the development of next-generation technologies. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 8857 Date posted 02/24/2025 Staff Embedded Memory Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an innovative and dedicated engineer with a passion for embedded memory compilers. With 2-5 years of experience in Embedded SRAM compilers, you possess a robust understanding of CMOS digital circuits, and any knowledge of FinFET technology is a plus. Your expertise in transistor-level circuit design allows you to navigate the complexities of read/write margins and timing races. You thrive in a collaborative environment, often engaging with senior internal and external personnel to achieve the best possible outcomes. You are a problem-solver who can work independently, taking ownership of tasks while effectively coordinating with the layout team to resolve design and layout issues. Your ability to comprehensive knowledge creatively makes you an invaluable asset to our team. What You’ll Be Doing: Designing, developing, and troubleshooting embedded memory compilers. ing skills in memory compilers, focusing on transistor-level circuit design. Understanding various memory design aspects such as read/write margins and timing races to find effective solutions. Interacting with the layout team to address and resolve issues from both design and layout standpoints. Working independently on tasks, ensuring ownership and collaboration to achieve optimal results. Engaging frequently with senior personnel to leverage expertise and enhance project outcomes. The Impact You Will Have: Enhancing the performance and reliability of embedded memory compilers. Driving innovation in memory design, contributing to the development of high-performance silicon chips. Collaborating with cross-functional teams to optimize design and layout processes. Ensuring timely delivery of robust and efficient memory solutions. Contributing to the continuous improvement of design methodologies and practices. Supporting the advancement of Synopsys' technology leadership in the semiconductor industry. What You’ll Need: 2-5 years of experience in Embedded SRAM compilers. Strong understanding of CMOS digital circuits. Knowledge of FinFET technology (preferred). Proficiency in transistor-level circuit design. Ability to analyze and resolve design and layout issues effectively. Who You Are: Innovative and detail-oriented. Collaborative team player. Effective communicator with strong interpersonal skills. Problem-solver with a proactive approach. Self-motivated and able to work independently. The Team You’ll Be A Part Of: You will join a dynamic and dedicated team focused on the design and development of embedded memory compilers. Our team prides itself on fostering an environment of collaboration and innovation, working together to push the boundaries of technology and deliver cutting-edge solutions. As part of this team, you will have the opportunity to engage with experienced professionals and contribute to projects that shape the future of the semiconductor industry. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Role: Physical Design Engineer Experience Required: 5-15 years Location: Noida only Minimum Experience required is 4 Years in Physical Design Strong fundamentals on Physical design including Floorplan, power grid analysis, placement, cts, routing, DRC-LVS closure, timing closure, antenna fixing, signal integrity on 65nm, 45nm, 28nm, 16nm geometry. Sound expertise in Tcl, Perl, Shell scripting. Technically sound & good team player Hands-on experience with Place and Route tools (Synopsys - ICC, Cadence – Innovus / Encounter) is a must. Experience on latest technology (28nm,16nm,7 nm) Job Types: Full-time, Permanent Benefits: Commuter assistance Food provided Health insurance Provident Fund Schedule: Monday to Friday Supplemental Pay: Performance bonus Yearly bonus Work Location: In person

Category Engineering Hire Type Employee Job ID 8601 Remote Eligible No Date Posted 22/04/2025 Alternate Job Titles: Staff SOC Engineer Senior SOC Design Engineer Lead SOC Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and motivated SOC Engineer with a passion for cutting-edge technology and innovation. With a strong background in system-on-chip (SOC) design and verification, you bring a wealth of knowledge and a keen eye for detail. You thrive in a collaborative environment, working seamlessly with cross-functional teams to deliver high-quality solutions. Your problem-solving skills are exceptional, and you have a proven track record of successfully managing complex projects. You are proactive, adaptable, and always eager to learn and grow in a dynamic and fast-paced setting. What You’ll Be Doing: Designing and implementing SOC solutions for various applications, ensuring high performance and reliability. Collaborating with cross-functional teams to define and develop SOC architecture and specifications. Conducting verification and validation of SOC designs to ensure compliance with industry standards and customer requirements. Optimizing SOC designs for power, performance, and area (PPA) to meet project objectives. Debugging and resolving issues in SOC designs, utilizing advanced tools and methodologies. Providing technical guidance and mentorship to junior engineers, fostering a culture of continuous improvement and innovation. Job Description and Requirements The role is for RTL Design and Signoff of IP/Subsystem/SoC Design in the System Solutions Group (SSG). At SSG, we are a team of experts in various Synopsys technologies to deliver architecture, design, verification, implementation, tools, methodology to enable our customers complete their most challenging SoC Design projects. Our work spans from sub-blocks to full turnkey end-to-end SoCs. Our customers range from start-ups to industry leaders, commercial companies, and government agencies. As part of this role, you can expect to develop and deliver your expertise in RTL Signoff and RTL Design Techniques while working on activities such as Lint/CDC/RDC Checks, Timing Constraints Development, Preliminary Synthesis, Formality and RTL Design. The role will expose you to various innovative technologies deployed for RTL Quality Signoff for Semiconductors. Responsibilities Perform RTL Quality Signoff Checks such as LINT, CDC, RDC. Understand the design/architecture and develop timing constraints for synthesis and timing. Run preliminary synthesis to ensure that the design can be synthesized as intended. Run formality to ensure equivalence of RTL and gates. Integrate IPs in SoCs/Subsystems and create RTL design as per need of the customer. Required B.E/B. Tech/M.E/M. Tech in electronics with 4-9 years’ experience in RTL Design and Verification. Hands-on experience on static verification tools such as Spyglass performing LINT, CDC, RDC. Good conceptual understanding of design/architecture pitfalls across clock/reset domain crossing. Good conceptual understanding of RTL rule checks. Hands-on experience on synthesis and timing constraints development. Candidates with experience on ARM based technologies (Coresight Debug, Processor architecture, etc.) will be preferred. The Team You’ll Be A Part Of: You will join a highly skilled and motivated team dedicated to developing advanced SOC solutions. Our team focuses on innovation, collaboration, and excellence, working together to deliver high-quality designs that drive technological advancements. We value diversity and inclusion, fostering a supportive and dynamic environment where every team member can thrive and contribute to our success. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Category Engineering Hire Type Employee Job ID 9277 Remote Eligible No Date Posted 16/02/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. Our group develops Controller IPs (PCIe/CXL) which help customers in integrating more capabilities into an SoC faster. Plus meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk. You Are: An experienced and visionary ASIC Design Architect Engineer with a proven track record in delivering Controller IP products. You possess deep functional knowledge and expertise in digital design/development methodologies, and you thrive in an environment where you can influence and implement strategic goals. Your background includes a comprehensive understanding of serial protocols such as PCIe/CXL/AXI/CHI etc. You can define and execute design/architecture for protocols such as PCIe/CXL. You are a proactive problem solver, capable of working with minimal oversight, and you excel in communicating complex technical concepts to a diverse audience. Your leadership skills enable you to guide and mentor teams, fostering innovation and excellence in all your projects. What You’ll Be Doing Responsible for PCIe/CXL next-gen Controller IP features Customer pre/post sales PCIe/CXL protocol related communication Utilizing advanced design methodologies and tools to achieve high-quality results Mentoring and guiding other engineers, promoting best practices, and fostering a culture of continuous improvement Communicating with internal and external stakeholders to align on project goals and deliverables. What You’ll Need: Extensive experience in digital ASIC design and physical aware synthesis. In-depth knowledge of PCIe, CXL , AXI, CHI and similar IO protocols. Proficiency in advanced digital design tools and methodologies. Strong problem-solving skills and the ability to work independently. Excellent communication skills for effective collaboration with diverse teams. Experience of 20+ years in relevant domain. Who You Are: A mentor who fosters talent and encourages innovation. A proactive problem solver who thrives in complex environments. An effective communicator with the ability to convey technical concepts to a broad audience. A team player who values collaboration and diversity. Synopsys values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 10754 Date posted 04/17/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an innovative and analytical thinker with a passion for technology and a drive to solve complex engineering challenges. You thrive in a collaborative environment, working alongside a high-caliber team of engineers to develop technical solutions that push the boundaries of AI-driven optimization. You possess a strong foundation in computer science or electronics, with a deep understanding of C/C++ and Linux. Your excellent communication skills enable you to effectively convey ideas and work seamlessly with product engineers to define and solve problems. You are committed to continuous improvement, always seeking ways to enhance performance and quality in your work. Your ability to debug issues, optimize algorithms, and develop new features makes you an invaluable asset to any engineering team. What You’ll Be Doing: Developing SignOff ECO optimization algorithms and heuristics. Debugging issues related to design loading and timing/power optimization. Striving for continuous improvements in QoR to achieve faster timing convergence with optimal power overhead. Collaborating with a team of engineers to develop technical solutions to complex problems. Communicating with product engineers to understand and define problem scope. Ensuring strict performance and quality requirements are met. The Impact You Will Have: Enhancing the performance and efficiency of PrimeClosure, the industry's first AI-driven signoff ECO solution. Contributing to the development of cutting-edge algorithms that optimize timing and power in chip design. Improving the overall quality and reliability of our products through rigorous debugging and testing. Driving innovation and continuous improvement in our engineering processes. Supporting customer success by resolving issues and implementing new features based on their feedback. Helping shape the future of AI-driven optimization in the semiconductor industry. What You’ll Need: 5+ years off relevant experience A degree in Computer Science or Electronics. Strong analytical and problem-solving skills. Proficiency in C/C++ and Linux. Excellent communication and teamwork abilities. A passion for technology and innovation. Who You Are: A collaborative team player who thrives in a dynamic and innovative environment. A proactive and self-motivated individual with a strong attention to detail. An excellent communicator who can articulate complex ideas clearly and effectively. A creative thinker who is always looking for new ways to solve problems and improve processes. A dedicated professional committed to delivering high-quality work. The Team You’ll Be A Part Of: You will be part of the PrimeClosure R&D team, responsible for developing and maintaining the industry's first AI-driven signoff ECO solution, PrimeClosure. This team is dedicated to pushing the boundaries of technology and innovation, working collaboratively to develop cutting-edge solutions that address complex engineering challenges. Together, you will strive for continuous improvements in performance and quality, ultimately shaping the future of AI-driven optimization in the semiconductor industry. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 9901 Date posted 03/18/2025 Alternate Job Titles: Senior Verification Engineer, IP Verification Specialist, RTL Design Verification Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled and motivated professional with a passion for design verification in the semiconductor industry. With a solid foundation in Electrical/Electronic Engineering, Computer Engineering, or Computer Science, you possess 4 to 8 years of hands-on experience in IP/SOC verification domains. Your expertise in industry-standard EDA tools, fault injection methods, and diagnostic coverage techniques sets you apart. You excel in creating test environments from functional specifications using methodologies like UVM/VMM/OVM and are proficient in advanced languages such as Verilog and System Verilog. Your strong analytical skills enable you to identify safety gaps in designs, ensuring robust and reliable IP cores. As an excellent communicator, you collaborate effectively with international teams, driving innovation and achieving project milestones. Your ability to work independently, precisely, and generate quality documentation makes you a valuable asset to our team. Experience with ISO26262 developments, fault injection, and scripting languages like Perl, TCL, or Python would be highly advantageous. What You’ll Be Doing: Developing design verification solutions for RTL-based IP Cores implementing complex protocols. Collaborating with architects, designers, and verification team members across multiple international sites. Performing fault injection on IP/SOC RTL designs to identify and address safety gaps using FMEDA data. Creating and running test environments from functional specifications using UVM/VMM/OVM methodologies. Analyzing fault lists and developing test cases for fault injection to achieve diagnostic coverage. Debugging designs in simulation and providing verification solutions for productivity, performance, and throughput improvement. The Impact You Will Have: Ensuring the reliability and safety of IP Cores used in automotive end-customer applications. Contributing to the development of high-performance silicon chips that drive innovation in the semiconductor industry. Enhancing the diagnostic coverage and safety standards of our IP designs. Improving the overall efficiency and performance of our verification processes. Collaborating with global teams to achieve project milestones and deliver high-quality IP solutions. Driving continuous technological innovation in the verification domain. What You’ll Need: Degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science. 4 to 8 years of experience in IP/SOC verification domains. Hands-on knowledge of fault injection methods and diagnostic coverage techniques. Proficiency in Verilog, System Verilog, and debugging designs in simulation. Experience with UVM/VMM/OVM methodologies and creating test environments from functional specifications. Who You Are: An independent and precise worker with a drive for innovation. An excellent communicator with strong documentation skills. A collaborative team player who excels in problem-solving. Ideally experienced in ISO26262 developments and fault injection. Knowledgeable in C/C++, Shell, and scripting languages like Perl, TCL, or Python. The Team You’ll Be A Part Of: You will be part of the IP Group at Synopsys, working with a talented team of architects, designers, and verification engineers across multiple international sites. Our team focuses on developing robust and reliable IP Cores for automotive applications, driving innovation and ensuring the highest standards of safety and performance. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 10738 Date posted 04/23/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned engineer with a passion for pushing the boundaries of technology. With 5 -8 years of experience, you bring a wealth of knowledge in software architecture and leadership. You excel in C/C++ software development, and your strong background in design patterns, data structures, and algorithms sets you apart. You thrive in multi-threaded and distributed code environments, and your familiarity with ASIC design flow and EDA tools is second to none. Your expertise in Verilog, SystemVerilog, and VHDL HDL, coupled with your experience in Unix/Linux platforms, makes you a valuable asset. You are well-versed in developer tools like gdb and Valgrind, and you understand the importance of source code control tools such as Perforce. Your analytical and problem-solving skills are top-notch, and you are always eager to learn and explore new technologies. As a highly enthusiastic and energetic team player, you are ready to go the extra mile to achieve success. What You’ll Be Doing: - Designing, developing, and troubleshooting core algorithms for word-level synthesis. - Collaborating with local and global teams to enhance synthesis QoR, performance, and logic interference. - Engaging in pure technical roles focused on software development and architecture. - Implementing multi-threaded and distributed code solutions. - Utilizing your knowledge of ASIC design flow and EDA tools to drive innovation. - Leveraging your expertise in Verilog, SystemVerilog, and VHDL HDL to develop cutting-edge solutions. The Impact You Will Have: - Driving technological innovation in chip design and verification. - Enhancing the performance and quality of synthesis tools used globally. - Solving complex logic interference problems to improve design accuracy. - Contributing to the development of high-performance silicon chips and software content. - Collaborating with cross-functional teams to achieve project milestones. - Pioneering new software architectures that set industry standards. What You’ll Need: - Strong hands-on experience in C/C++ based software development. - Deep understanding of design patterns, data structures, algorithms, and programming concepts. - Familiarity with multi-threaded and distributed code development. - Knowledge of ASIC design flow and EDA tools and methodologies. - Proficiency in Verilog, SystemVerilog, and VHDL HDL. Who You Are: - Highly enthusiastic and energetic team player with excellent communication skills. - Strong desire to learn and explore new technologies. - Effective problem-solver with a keen analytical mind. - Experienced in working on Unix/Linux platforms. - Adept at using developer tools such as gdb and Valgrind. The Team You’ll Be A Part Of: You will be part of the word-level synthesis team, catering to multiple EDA products. This team focuses on developing innovative solutions to improve synthesis quality of results (QoR), performance, and logic interference. You will work closely with both local and global teams to drive technological advancements and achieve project goals. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 8827 Date posted 02/24/2025 Experience : 5yrs to 12 years Expertise in UVM and System Verilog Experience in verification IP modelling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage. Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies. Protocol experience: Should have experience on UCIe/PCIe/CXL/Unipro/USB/MIPI/HDMI/Ethernet/DDR/LPDDR/HBM memory protocol Job responsibilities: Able to contribute to the development of the VIP Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective. Locally should be to be "go-to" person on all technical aspects of VIP At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Category Engineering Hire Type Employee Job ID 10481 Remote Eligible No Date Posted 13/04/2025 Staff ASIC Verification Engineer, Noida Location: Key responsibilities: Participate in development of verification test plan, verification environment documentation and test environment usage documentation Evaluates and exercises various aspects of the development flow. May include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modelling, and verification coverage metrics (functional coverage and code coverage) Collaborate with architect, designers , VIP team and peers to accomplish all verification goals. Identify design problems, possible corrective actions and/or inconsistencies on documented functionality Adhere to quality standards and good test and verification practices. May work to coach junior engineers and help them in debugging complex problems. Key Qualifications Proven desire to learn and explore new state of the art technologies Demonstrate good written and spoken English communication skills Demonstrate good review and problem-solving skills Knowledgeable with Verilog, VHDL and/or SystemVerilog Knowledgeable with scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plus Understanding of verification methodology such as UVM . Good organization and communication skills. 5 + years of relevant experience At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 9877 Date posted 03/04/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned professional with a passion for cutting-edge technology and innovation. With 8 -12 years of experience, you bring a wealth of knowledge in CMOS memory design and circuit implementation. Your expertise lies in developing non-volatile memories or SRAM. You are proficient in schematic entry, circuit simulation, layout planning, and design verification. You thrive in a collaborative environment, interfacing with CAD and Frontend engineers to drive memory compiler automation and EDA model generation. Your attention to detail ensures the highest quality in circuit and physical layout design. Self-motivated and self-directed, you demonstrate excellent analytical and problem-solving skills. You are adept at programming in C-Shell or Perl. Your strong command of English, both verbal and written, enables you to communicate effectively with team members and stakeholders. You are committed to continuous learning and professional growth, and you bring professionalism, critical thinking, and a focus on future goals to your work. Inclusion and diversity are important to you, and you contribute to a collaborative and inclusive work environment. What You’ll Be Doing: Develop CMOS embedded non-volatile memories such as MRAM and RRAM. Design architecture and circuit implementation, focusing on high speed, low power, and high-density designs. Perform schematic entry, circuit simulation, layout planning, layout supervision, design verification, and validation. Interface with CAD and Frontend engineers for memory compiler automation, EDA model generation, and full verification flow. Perform design verification and drive physical layout design and verification. Provide support and/or perform other duties as assigned and required. The Impact You Will Have: Contribute to the development of high-performance silicon chips and software content. Enhance the efficiency and performance of our CMOS non-volatile memory designs. Drive innovation in high speed, low power, and high density memory designs. Ensure the highest quality in circuit development and physical layout design. Collaborate effectively with CAD and Frontend engineers to streamline automation and verification processes. Support the continuous improvement and advancement of our memory design technology. What You’ll Need: Bachelor’s or Master’s degree in Electrical Engineering, Telecommunication, or related fields. Proficiency in CMOS memory design(NVM or SRAM), circuit simulation, memory layout designs, layout parasitic extraction, and layout verification tools and debugging techniques. Basic circuit know-how of Charge Pump, Voltage Regulator, Current Mirror, Reference voltage and current, Comparators preferred Programming capability in C-Shell or Perl Strong analytical and problem-solving skills with attention to detail. Experience in developing documents, reports, or presentations for a range of tasks. Who You Are: Self-motivated, self-directed, detail-oriented, and well-organized. Possess excellent analytical, problem-solving, and negotiation skills. Capable of leading and mentoring trainees and junior engineers, as well as managing projects. Strong command of English, both verbal and written. Exhibit strong interpersonal communication and teamwork skills. Professional, critical/logical thinker, and focused on future goals. Highly committed to continuous learning and professional development. The Team You’ll Be A Part Of: You will be a key member of our innovative R&D Engineering team, focused on developing cutting-edge CMOS embedded non-volatile memories (MRAM/RRAM). Our team thrives on collaboration and continuous improvement, working together to achieve technological advancements that shape the future. You will have the opportunity to lead and mentor junior engineers, contributing to a culture of learning and excellence. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Category Engineering Hire Type Employee Job ID 6673 Remote Eligible No Date Posted 28/10/2024 Alternate Job Titles: ASIC Physical Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated and experienced Physical Design Engineer with a passion for implementing and performing signoff verifications of digital blocks using ASIC design flow (Gate2GDSII). You thrive in dynamic environments and have a knack for problem-solving and innovation. Your expertise in digital block implementation, from gate netlist to GDSII, is complemented by your hands-on experience with state-of-the-art ASIC flows. You understand the intricacies of design initialization, power planning, floor planning/macro placement, scan-chain reordering, CTS, route, and chip finishing steps. You have a solid foundation in physical implementation, signoff verifications (DRC, LVS, Antenna), and reliability verifications (EMIR, ESD). Your ownership of writing MCMM and UPF for block designs showcases your leadership and technical prowess. You are adept at providing handoff data to other signoff closure like STA, formality, layout, and reliability verification. With a minimum of 5 years of relevant experience in the physical design domain and a B.E/B.Tech/M.Tech in ECE/EE, you are ready to take on new challenges and contribute to groundbreaking projects. What You’ll Be Doing: Implementing digital blocks using state-of-the-art gate to GDSII ASIC flows. Performing physical implementation of blocks from gate netlist to GDSII. Conducting signoff verifications, including layout verifications (DRC, LVS, Antenna) and reliability verifications (EMIR, ESD). Writing MCMM and UPF for block designs. Providing handoff data for other signoff closure processes like STA, formality, layout, and reliability verification. Collaborating with cross-functional teams to ensure the successful integration and testing of physical designs. The Impact You Will Have: Enhancing the quality and reliability of our digital block implementations. Driving innovation in physical design methodologies and processes. Enabling the successful deployment of high-performance silicon chips. Contributing to the development of cutting-edge technology that powers next-generation applications. Supporting the continuous improvement of our ASIC design flow and tools. Ensuring the seamless integration of physical designs into larger systems and platforms. What You’ll Need: In-depth understanding of the ASIC physical design flow steps from gate netlist. Experience in testchip implementation and testing exposure is a plus. Exposure to Synopsys toolset (such as FC/ICC2, Primetime, Formality, ICV) is highly desirable. Experience with FinFET designs is desirable. Experience in working on IO integration with wire-bond or flip-chip design is a big plus. Who You Are: A problem solver with strong analytical skills. Detail-oriented with a focus on quality and reliability. Effective communicator and collaborator. Innovative thinker with a passion for technology. Self-motivated and able to work independently. The Team You’ll Be A Part Of: Join a dynamic team of experts focused on pushing the boundaries of physical design and implementation. Our team is dedicated to continuous innovation and excellence, working collaboratively to solve complex challenges and deliver cutting-edge solutions. You'll be part of a supportive and inclusive environment where your contributions are valued and your professional growth is nurtured. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 9672 Date posted 03/02/2025 Candidate will be part of VC PS Noida team. Design, develop, troubleshoot the core algorithms. Design and develop standard and customized features / checks in VC PS for inference, propagation and verification. Will be working with other local and global teams. Design and development of state of the art EDA tools involving development of new and innovative algorithms. Create test cases to test the developed feature. Skills Required Ability to develop new software architecture and good leadership skills. Fluent in C/C++ with extensive work experience in data-structures and algorithms. Excellent algorithm analysis skills and a good knowledge of data structures. Good knowledge of Tcl and Perl-based development on Unix. Good knowledge of Verilog, SystemVerilog & VHDL HDL. Familiarity with ASIC design flow and the EDA tools and methodologies used therein. Familiarity with multi-threaded and distributed code development. Self-motivation, self- discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. Quality focus - one who believes in quality and wants to make a difference. Experience of production code development on Unix/Linux platforms. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 7228 Date posted 02/24/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and dedicated individual with a strong background in Electronics and Communication Engineering or Computer Science. You have a keen interest in software development and system validation, and you are eager to your skills in a dynamic and innovative environment. You thrive on solving complex problems and are always ready to take on new challenges. Your technical prowess is complemented by your excellent communication skills, making you an effective team player and a valuable contributor to any project. You have a meticulous eye for detail and a commitment to delivering high-quality work. You are not only technically proficient but also adaptable, able to quickly learn new tools and methodologies. Your previous experience in embedded systems, board-level testing, and programming in C/C++ sets you apart, and you are excited about the opportunity to work with high-speed serial interfaces and FPGA-based setups. Your proactive approach and analytical mindset enable you to excel in a fast-paced, collaborative environment. What You’ll Be Doing: Developing and testing software for validation and automation purposes. Performing device-level and system-level validation and debug in post-silicon environments. Executing software tests in verification environments to ensure product quality. Working with FPGA-based setups to run validation tests and update FPGA RTL modules as needed. Creating detailed test and validation reports with statistical analysis. Interfacing with customers to capture requirements and provide post-release support. The Impact You Will Have: Contributing to the development of cutting-edge technology that drives innovation in various industries. Ensuring the reliability and performance of high-speed serial interface PHYs like USB, PCIe, and Ethernet. Enhancing the validation and debug processes through meticulous testing and analysis. Improving the overall quality and functionality of Synopsys products through rigorous validation. Supporting the continuous improvement of product development cycles. Providing valuable insights and feedback to enhance future product iterations. What You’ll Need: B.Tech in ECE/CS or equivalent with 3-7 years of previous experience in a similar role/industry. Experience in programming and testing using C/C++. Board-level test and debug experience using lab equipment. Experience with embedded or resource-constrained environments. Development experience on Unix, Linux, and Windows platforms. Ability to quickly learn new workflows and adapt to new technologies. Exposure to MATLAB/Python programming is a plus. Exposure to verification and basic RTL is a plus. Excellent verbal and written communication skills. Who You Are: A proactive and motivated individual with a passion for technology and innovation. An effective communicator who can articulate technical concepts clearly and concisely. A team player who collaborates well with others and contributes to collective goals. A detail-oriented professional with a strong analytical mindset. An adaptable learner who thrives in dynamic environments and embraces new challenges. The Team You’ll Be A Part Of: You will be part of a dedicated team focused on the development and validation of high-speed serial interfaces and embedded systems. The team collaborates closely to ensure the quality and performance of Synopsys products, leveraging a diverse set of skills and expertise. You will work alongside experienced engineers who are passionate about technology and committed to driving innovation. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Bachelor's/Master’s degree in Electrical/Electronic Engineering from reputed institution 2-10 years of experience in Physical Design/Implementation Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3063953 Show more Show less

Role Description Memory Layout Hands on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context. Should have worked on 16nm / 14nm / 10nm/ 7nm/ Finfet process technologies . Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the compiler space. Good handle on IR/EM related issues in memory layouts . Must have worked on cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks. Strong knowledge of ultra-deep sub-micron layout design related challenges and good understanding of DFM guidelines. Experience & or strong interest in memory compilers developed. Excellent and demonstrated team player with ability to work with external customers and in cross functional teams Skills Memory Layout,Finfet,Cadence,Layout Design Show more Show less

Role Description Role Proficiency: Independently execute mid sized customer projects in any field of VLSI Frontend Backend or Analog design with minimal supervision Outcomes Work as an individual contributor owning any one task of RTL Design/Module. Provide support and guidance to engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc. Anticipate diagnose and resolve problems; coordinating as necessary with cross-functional teams On time quality delivery approved by the project manager and client Automate the design tasks flows and write scripts to generate reports Come up with novel ideas to reduce design cycle time and cost accepted by UST Manager and client Measures Of Outcomes Quality –verified using relevant metrics by UST Manager / Client Manager Timely delivery - verified using relevant metrics by UST Manager / Client Manager Reduction in cycle time cost using innovative approaches Number of papers published Number of patents filed Number of mandatory trainings attended adhering to training goals Outputs Expected Quality of the deliverables: Ensure zero bugs are present in the design / circuit design. Clean delivery of the design/module in-terms of ease in integration at the top level Meeting functional spec / design guidelines 100% without any deviation or limitation Documentation of tasks and work performed Timely Delivery Ensure project timelines as laid out by the client or program manager are met Meet intermediate tasks delivery for other team members to progress Calling out for help and support in the case of delay in tasks delivery New Skills Development Participate in training – skilling someone and also getting skilled in newer technologies Take up new areas of project development learn on the job and deliver Team Work Participation in team work and supporting team members at the time of need Able to take up additional tasks in-case of any team member(s) not available Able to hand hold junior team members to explain the project tasks and support to deliver Work dedication to go beyond the call of duty to ensure deadlines and quality are met Innovation & Creativity Approach towards repeated work by automating tasks to save design cycle time Participation on technical discussion training forum white paper etc Skill Examples Languages and Programming skills:a. System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (experience in one or more tools) Technical Knowledge:a. IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb. Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec. Strong Physical Design / Circuit Design / Analog Layout Knowledged. Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verificatione. Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below Strong communication skills and ability to interact with team members and clients equally Strong analytical reasoning and problem-solving skills with attention to details Ability to understand the standard specs and functional documents Ability to deliver the tasks on-time in a quality fashion per quality guidelines and GANTT Well versed with the available EDA tools and able to use them efficiently Required technical skills and prior design knowledge to execute the assigned tasks Ability to learn new skills in-case required technical skills are not present at a level needed to execute the project Knowledge Examples Knowledge of project(s) in any of the design by executing – RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc. Understanding of the design flow and methodologies used in the designing Understand the assigned tasks and have sufficient knowledge to execute the project tasks assigned by the client / manager as per known skills Additional Comments Job description: PHY design Experienced analog/mixed-signal designer for high-speed PHYs design. It is mandatory that the candidate has in-depth understanding of analog and mixed-signal design, with hand-on design experience of PHY circuits. Specific areas of expertise/knowledge required: Voltage & current references, LDO regulator, high-accuracy comparator and amplifier High speed custom digital circuits like serializer, de-serializer, clock divider and synchronizer High Speed flops, gates operating at low voltage with best in class PPA Voltage and current mode transmitters, duty-cycle corrector TX/RX equalization techniques and circuits (e.g. CTLE, DFE) Calibration technique to tune for PVT variation Mixed mode simulation Transmission line theory, concept of PDN, device mismatch, system linearity and stability, low power design Following areas would be a significant Plus: Skills in scripting and automation Knowledge of common PHY protocols (DP, USB, Ethernet etc.) Concept of Quality in design and IP delivery Understanding of behavioral modeling of Analog circuits and RTL-to-GDS flow Skills Analog Mixed Signal ,PHY Circuit ,LDO regulator Show more Show less

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. 5+ Year of industry experiences in the following areas: Expertise in Synthesis - Synopsys Design Compiler, DCG/DC_NXT/Fusion Compiler and/or Cadence RC/Genus. o Hands on with multi-voltage, power aware synthesis, UPF flows in synthesis and low power designs. o Expertise in formal verification with Cadence LEC/ Synopsys Formality o Expertise in writing and debugging timing constraints o Perl and/or TCL scripting, makefile flows. Qualcomm's compute sub system engineers will work on next generation low power, machine Learning sub-system for our system-on-chip (SoC) products used in Smartphone, Automotive and other low power devices. Become a key member of the core team developing fastest smartphone SoC devices implemented on the latest cutting-edge process technologies. In this role candidate will be responsible for compute sub system implementation that includes Physically aware Synthesis -DCG/Fusion Compiler/Genus. In addition, he/she will perform tasks toward constraints development, clock definitions, timing analysis, UPF, CLP check, Formal Verification and ECO flow. He/She will be working closely with physical Design team to optimize designs for power, area, and performance. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3075459 Show more Show less