886 Synopsys Jobs - Page 13

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: MTS SILICON DESIGN ENGINEER THE ROLE: This exciting position as MTS in AMD's Silicon IP solutions & SOC group will provide the individual with an opportunity to demonstrate strong technical leadership across the design hierarchy from architecture to Productization. Join us in providing innovative IP solutions as we embark on our journey into the cutting edge programmable logic based silicon designs by delivering the complex IP Solutions for multiple market segments As part of this opportunity, we are seeking a Synthesis and Timing engineer to participate in the development of large SOC’s with multiple physical blocks and 300+ clock domains. This position requires an individual to be creative, team-oriented, technology savvy, able to lead large cross-functional teams, comfortable and willing to provide regular updates to management chain during the project execution THE PERSON: You have a passion for modern, complex hardware and IP architecture, digital design, and physical design in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff Drive the effort to maintain RTL quality metrics in complex, hierarchical designs and automating that process for improved efficiency. Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Work with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) flows Requires a mix of SDC knowledge, EDA tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts) PREFERRED EXPERIENCE: About 6 to 10 years of relevant experience Worked with EDA tools that enable RTL quality checks Hands on experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows. Experience with analyzing the timing reports and identifying both the design and constraints related issues. Ability to multitask and grasp new flows/tools/ideas Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc Automating workflows in a distributed compute environment. Scripting language experience: Python/TCL preferred. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-MK1 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Job Title: Physical Design Engineer Domain: Semiconductor | VLSI | Chip Design Experience: 7 to 15 Years Location: Bangalore / Hyderabad / Cochin / Pune Budget: ₹30 LPA to ₹75 LPA Work Mode: 5 Days Office Key Responsibilities End-to-end ownership of chip-level and block-level floor planning. Drive partitioning, placement, clock tree synthesis (CTS), and routing. Utilize tools like Cadence Innovus and Synopsys Fusion Compiler for implementation. Perform timing analysis, DRC/LVS closure, and physical verification. Collaborate with cross-functional teams including RTL, DFT, STA, and packaging teams. Key Skills Required Strong experience in chip-level and block-level physical design. Hands-on expertise with Innovus and/or Fusion Compiler. Solid understanding of timing, power, signal integrity, and physical verification. Exposure to advanced technology nodes (e.g., 7nm, 5nm) is a plus. Excellent problem-solving and debugging skills. Skills: fusion compiler,chip level,signal integrity,chip-level physical design,timing,physical verification,timing analysis,physical design,debugging,block-level floor planning.,block-level physical design,power,problem-solving,advanced technology nodes,innovus,synopsys fusion compiler,drc/lvs closure,cadence innovus

Job Title: Physical Design Engineer Domain: Semiconductor | VLSI | Chip Design Experience: 7 to 15 Years Location: Bangalore / Hyderabad / Cochin / Pune Budget: ₹30 LPA to ₹75 LPA Work Mode: 5 Days Office Key Responsibilities End-to-end ownership of chip-level and block-level floor planning. Drive partitioning, placement, clock tree synthesis (CTS), and routing. Utilize tools like Cadence Innovus and Synopsys Fusion Compiler for implementation. Perform timing analysis, DRC/LVS closure, and physical verification. Collaborate with cross-functional teams including RTL, DFT, STA, and packaging teams. Key Skills Required Strong experience in chip-level and block-level physical design. Hands-on expertise with Innovus and/or Fusion Compiler. Solid understanding of timing, power, signal integrity, and physical verification. Exposure to advanced technology nodes (e.g., 7nm, 5nm) is a plus. Excellent problem-solving and debugging skills. Skills: fusion compiler,chip level,signal integrity,chip-level physical design,timing,physical verification,timing analysis,physical design,debugging,block-level floor planning.,block-level physical design,power,problem-solving,advanced technology nodes,innovus,synopsys fusion compiler,drc/lvs closure,cadence innovus

Hi Greetings from Eximietas Design! We are actively looking to hire Senior Analog Layout Design Engineers / Leads with 7–15 years of experience to join our growing team. 📍 Locations: Bangalore, Hyderabad & Visakhapatnam. 📅 Notice Period: 30 days or less preferred. Job Description: We’re seeking highly skilled professionals with a strong background in lower FINFET technology nodes (TSMC 5nm preferred) to contribute to cutting-edge analog layout design. Key Skills & Requirements: Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. Solid understanding of how layout impacts circuit performance (speed, area, etc.). Ability to implement layouts that meet tight design constraints and deliver high quality. Hands-on experience with CADENCE/SYNOPSYS layout tools and flows. Familiarity with scripting languages (PERL/SKILL) is a plus. Strong communication skills and experience working with cross-functional teams. If this opportunity interests you—or if you know someone suitable—please send your updated resume to: 📧 maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We look forward to connecting with talented engineers passionate about pushing the boundaries of analog layout design! Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam maruthiprasad.e@eximietas.design +91 8088969910.

Hi Greetings from Eximietas Design! We are actively looking to hire Senior Analog Layout Design Engineers / Leads (TSMC 5nm preferred) with experience to join our growing team. Locations: Bangalore & Visakhapatnam. Notice Period : 30 days or less preferred. Job Description: Were seeking highly skilled professionals with a strong background in lower FINFET technology nodes (TSMC 5nm preferred) to contribute to cutting-edge analog layout design. Key Skills & Requirements: Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. Solid understanding of how layout impacts circuit performance (speed, area, etc.). Ability to implement layouts that meet tight design constraints and deliver high quality. Hands-on experience with CADENCE/SYNOPSYS layout tools and flows. Familiarity with scripting languages (PERL/SKILL) is a plus. Strong communication skills and experience working with cross-functional teams. If this opportunity interests youor if you know someone suitableplease send your updated resume to: maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We look forward to connecting with talented engineers passionate about pushing the boundaries of analog layout design! Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam maruthiprasad.e@eximietas.design +91 8088969910.

Key Responsibilities: Define and lead the strategy for VLSI front-end design services Build and scale high-performing VLSI engineering teams (from 50 to 500+) Engage with customer design managers and secure design wins through deep technical collaboration Mentor and upskill engineering teams in line with evolving industry needs Ensure successful delivery of ASIC design and verification projects Develop innovative proposals and drive new project wins Collaborate with internal resourcing teams and external partners to fulfill staffing needs Represent VLSI practice in industry forums and events Must-Have Skills: Strong leadership experience in VLSI/ASIC front-end engineering Expertise in RTL design, UVM-based verification, UPF/SDC, formal verification, emulation Hands-on with commercial EDA tools (Synopsys, Cadence, Siemens) Familiarity with Verilog and standard formats (LEF/DEF/SPEF) Client engagement, delivery management, and proposal leadership Good-to-Have Skills: Industry connects with EDA vendors, foundries, and Tier-1 semiconductor companies Knowledge of ASIC-package co-design Experience in defining VLSI roadmaps, SoW/MSA processes Automation exposure (Python/Perl) Awareness of semiconductor industry trends and competitor insights

Key Responsibilities: Define and lead VLSI back-end services strategy and offerings Build and scale high-performing VLSI engineering teams (300+ roadmap) Engage with semiconductor clients for technical discussions and project wins Oversee delivery of back-end services including physical design, STA, DFT, timing/power analysis Collaborate with sales, presales, and partner ecosystem to drive business growth Mentor engineers and ensure alignment to latest tech trends and client needs Lead proposal creation, solution demos, and client engagement at senior levels Must-Have Skills: Strong experience in VLSI/ASIC back-end engineering Physical design, timing closure, DFT, power/performance optimization Expertise in EDA tools (Synopsys, Cadence, Siemens) Verilog, LEF/DEF/SPEF formats Excellent leadership, communication & stakeholder management Good-to-Have Skills: Proficiency in scripting (Python, Perl, Tcl) Experience with advanced node technologies (7nm, 5nm, etc.) Exposure to ASIC-package co-design Strong industry connects (EDA vendors, foundries, Tier-1 chipmakers) Strategy planning, SoW/MSA reviews, innovation initiatives

MTS Silicon Design Engineer Hyderabad, India Engineering 67041 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS SILICON DESIGN ENGINEER THE ROLE: This exciting position as MTS in AMD's Silicon IP solutions & SOC group will provide the individual with an opportunity to demonstrate strong technical leadership across the design hierarchy from architecture to Productization. Join us in providing innovative IP solutions as we embark on our journey into the cutting edge programmable logic based silicon designs by delivering the complex IP Solutions for multiple market segments As part of this opportunity, we are seeking a Synthesis and Timing engineer to participate in the development of large SOC’s with multiple physical blocks and 300+ clock domains. This position requires an individual to be creative, team-oriented, technology savvy, able to lead large cross-functional teams, comfortable and willing to provide regular updates to management chain during the project execution THE PERSON: You have a passion for modern, complex hardware and IP architecture, digital design, and physical design in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff Drive the effort to maintain RTL quality metrics in complex, hierarchical designs and automating that process for improved efficiency. Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Work with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) flows Requires a mix of SDC knowledge, EDA tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts) PREFERRED EXPERIENCE: About 6 to 10 years of relevant experience Worked with EDA tools that enable RTL quality checks Hands on experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows. Experience with analyzing the timing reports and identifying both the design and constraints related issues. Ability to multitask and grasp new flows/tools/ideas Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc Automating workflows in a distributed compute environment. Scripting language experience: Python/TCL preferred. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-MK1 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Key Responsibilities: Collaborate with customers to understand their design requirements and provide technical support throughout the implementation phase. Identify, troubleshoot, and resolve design issues such as DRC, LVS, and other verification checks to ensure successful tapeout. Hands-on in relevant EDA tools like Innovus, IC compiler, Calibre , PrimeTime etc Assist in the tapeout process, ensuring all design files are correctly prepared and submitted for manufacturing. Qualifications: Bachelor's or Master's degree in Electrical Engineering or a related field. Proven experience of atleast 8 years as digital chip designer and customer support. Strong problem-solving skills and ability to work under pressure. Excellent communication and interpersonal skills. Hands-on in EDA tools such as Cadence , Synopsys and Mentor Graphic

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: As a Data Science Staff member located in Hyderabad, you are a visionary with a passion for data engineering and analytics. You thrive in dynamic environments and are motivated by the challenge of building robust data infrastructure. Your expertise in data modeling, algorithm development, and data pipeline construction is complemented by your ability to derive actionable insights from complex datasets. You possess a deep understanding of modern data stack tools and have hands-on experience with cloud data warehouses, transformation tools, and data ingestion technologies. Your technical acumen is matched by your ability to collaborate effectively with cross-functional teams, providing support and guidance to business users. You stay ahead of the curve by continuously exploring advancements in AI, Generative AI, and machine learning, seeking opportunities to integrate these innovations into your work. Your commitment to best practices in data management and your proficiency in various scripting languages and visualization tools make you an invaluable asset to our team. What You’ll Be Doing: Building the data engineering and analytics infrastructure for our new Enterprise Data Platform using Snowflake and Fivetran. Leading the development of data models, algorithms, data pipelines, and insights to enable data-driven decision-making. Collaborating with team members to shape the design and direction of the data platform. Working end-to-end on data products, from problem understanding to developing data pipelines, dimensional data models, and visualizations. Providing support and advice to business users, including data preparation for predictive and prescriptive modeling. Ensuring consistency of processes and championing best practices in data management. Evaluating and recommending new data tools or processes. Designing, developing, and deploying scalable AI/Generative AI and machine learning models as needed. Providing day-to-day production support to internal business unit customers, implementing enhancements and resolving defects. Maintaining awareness of emerging trends in AI, Generative AI, and machine learning to enhance existing systems and develop innovative solutions. The Impact You Will Have: Driving the development of a cutting-edge data platform that supports enterprise-wide data initiatives. Enabling data-driven decision-making across the organization through robust data models and insights. Enhancing the efficiency and effectiveness of data management processes. Supporting business users in leveraging data for predictive and prescriptive analytics. Innovating and integrating advanced AI and machine learning solutions to solve complex business challenges. Contributing to the overall success of Synopsys by ensuring high-quality data infrastructure and analytics capabilities. What You’ll Need: BS with 5+ years of relevant experience or MS with 3+ years of relevant experience in Computer Sciences, Mathematics, Engineering, or MIS. 5 years of experience in DW/BI development, reporting, and analytics roles, working with business and key stakeholders. Advanced knowledge of Data Warehousing, SQL, ETL/ELT, dimensional modeling, and databases (e.g., mySQL, Postgres, HANA). Hands-on experience with modern data stack tools, including cloud data warehouses (Snowflake), transformation tools (dbt), and cloud providers (Azure, AWS). Experience with data ingestion tools (e.g., Fivetran, HVR, Airbyte), CI/CD (GitLab, Kubernetes, Airflow), and data catalog tools (e.g., Datahub, Atlan) is a plus. Proficiency in scripting languages like Python, Unix, SQL, Scala, and Java for data extraction and exploration. Experience with visualization tools like Tableau and PowerBI is a plus. Knowledge of machine learning frameworks and libraries (e.g., Pandas, NumPy, TensorFlow, PyTorch) and LLM models is a plus. Understanding of data governance, data integrity, and data quality best practices. Experience with agile development methodologies and change control processes. Who You Are: You are a collaborative and innovative problem-solver with a strong technical background. Your ability to communicate effectively with diverse teams and stakeholders is complemented by your analytical mindset and attention to detail. You are proactive, continuously seeking opportunities to leverage new technologies and methodologies to drive improvements. You thrive in a fast-paced environment and are committed to delivering high-quality solutions that meet business needs. The Team You’ll Be A Part Of: You will join the Business Applications team, a dynamic group focused on building and maintaining the data infrastructure that powers our enterprise-wide analytics and decision-making capabilities. The team is dedicated to innovation, collaboration, and excellence, working together to drive the success of Synopsys through cutting-edge data solutions. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a dedicated and enthusiastic individual with a passion for customer support and IT services. With 2-3 years of experience in End-user/Desktop Support within the IT industry, you possess a working knowledge of debugging skills in the Windows environment. Your experience supporting business and connectivity tools, including Microsoft Office, Outlook Exchange email, and Remote Access, has equipped you with the expertise needed to excel in this role. You have a good understanding and experience with Windows Active Directory Services and Exchange email tools, and some knowledge of LAN/WAN, including TCP/IP and DHCP, is preferred. Your ability to communicate clearly in person, in writing, and over the phone, coupled with your patience and politeness in handling customer calls, makes you an ideal candidate. Strong interpersonal skills and attention to detail are among your key strengths. Knowledge of UNIX, technical writing, MAC Operating System, networking, and/or Cisco Unified communications tools is a plus. What You’ll Be Doing: Providing IT support through phone, tickets, and chat to Synopsys workforce around the world. Resolving problems of moderate scope involving laptops/desktops, mobile devices, and applications. Handling common account issues and troubleshooting effectively. Providing ticket status updates to management and end-users. Maintaining effective relationships with end users. Exercising judgment within defined procedures and practices to determine appropriate actions. The Impact You Will Have: Ensuring smooth and efficient IT operations within Synopsys. Enhancing user satisfaction through prompt and effective problem resolution. Contributing to the overall productivity of the workforce by minimizing downtime. Supporting the implementation of IT projects and service delivery initiatives. Maintaining a robust IT knowledge base through content management. Fostering a positive user experience and maintaining high standards of customer service. What You’ll Need: Technical degree or diploma in a related field. 2-3 years of experience in End-user/Desktop Support. Proficiency in debugging within the Windows environment. Experience with Microsoft Office, Outlook Exchange email, and Remote Access. Knowledge of Windows Active Directory Services and Exchange email tools. Who You Are: A strong communicator, both verbally and in writing. Patient and polite in handling customer interactions. Detail-oriented with excellent organizational skills. A team player with strong interpersonal skills. Adaptable and able to exercise sound judgment within defined procedures. The Team You’ll Be A Part Of: Our Global IT Service Desk is the main entry point for all IT Products and Services at Synopsys. The team provides first-level, 24x7 support to some 25,000 employees worldwide via calls, chats, tickets, and walk-ups. With team members located in Mountain View, Shanghai, Hyderabad, Lisbon, Durham, and Bloomington, we participate in projects around service delivery, manage our IT Web knowledge base, and ensure the highest level of customer support. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Job Title: AI/ML Engineer - Time Series Forecasting & Clustering Location: Bangalore Experience: 2+ Years Job Type: Full-Time Mandatory Skills: AI/ML Engineer with Time Series Forecasting & Clustering experience Responsibilities in Brief: Time Series Forecasting : Build models to predict trends from time series data. Clustering : Develop algorithms to group and analyze data segments. Data Insights : Analyze data to enhance model performance. Team Collaboration : Work with teams to integrate models into products. Stay Updated : Apply the latest AI techniques to improve solutions. Qualifications: Education : Bachelors/Masters in Computer Science or related field. Experience : Hands-on experience with time series forecasting and clustering. Skills : Proficient in Python, R, and relevant ML tools Perks & Benefits: Health and Wellness: Healthcare policy covering your family and parents. Food: Enjoy scrumptious buffet lunch at the office every day. Professional Development: Learn and propel your career. We provide workshops, funded online courses and other learning opportunities based on individual needs. Rewards and Recognitions: Recognition and rewards programs in place to celebrate your achievements and contributions. Why join Relanto? Health & Family: Comprehensive benefits for you and your loved ones, ensuring well-being. Growth Mindset: Continuous learning opportunities to stay ahead in your field. Dynamic & Inclusive: Vibrant culture fostering collaboration, creativity, and belonging. Career Ladder: Internal promotions and clear path for advancement. Recognition & Rewards: Celebrate your achievements and contributions. Work-Life Harmony: Flexible arrangements to balance your commitments. To find out more about us, head over to our Website and LinkedIn

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Looking for a highly talented and a technically strong leader with an eye for quality to lead a high performing and talented team of engineers in the implementation domain for Display Sub-System. Able to handle multiple project execution that are time critical and complex Able to communicate effectively with all stakeholders across the organization Able to collaborate with cross functional teams for upholding the best practices and enabling smooth execution Focus on improving execution efficiency and improve on the optimizations in area, power and performance. Able to grow the team in terms of technical depth and size as we do more and more projects Able to innovate and bring fresh ideas Bachelor’s or master’s degree in engineering with 9-13+ Years of experience. Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools. Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure. Experience in all aspects of timing closure for multi-clock domain designs. Should be familiar with MCMM synthesis and optimization. Should have good understanding of low-power design implementation using UPF. Experience with scripting language such as Perl/ Python, TCL. Experience with different power optimization flows or technique such as clock gating. Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation Should be able to handle ECOs and formal verification and maintain high quality matrix Responsibilities include Synthesis, LEC, Low power checks, Memory BIST insertion, Constraints validation. Development of signoff quality constraints and the development of power intent constraints. May also include running RTL Lint, CLP, MEMBIST, DFT DRC etc. TCL script development in addition to running/analyzing/debugging designs. Hands on with Synopsys DCG/Genus/Fusion Compiler. Hands on with Synopsys Prime Time including constraint development for complex blocks with multiple clock domains. Hands on with Cadence Conformal LEC and Cadence Conformal Low Power including UPF development Experience with either RTL development or Physical Design is also a plus

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Job Summary: This position is open for 2-10 years’ experience candidate in Qualcomm CSI (Custom/SemiCustom implementation) team Candidate will be part of CSI team working on RTL- GDS HM implementations using custom flow and methodology for custom design . Qualcomm is one of the fastest growing semiconductor organization in India making high-end Chips with the most advanced technologies. To support its growing needs, we have strong CSI team for the design, development of various highspeed and low power IP’s being used in SoC. Individual has to work on RTL-GDS implementation. This will involve innovating new solutions in close collaboration with the other design teams. Job Responsibilities: Job responsibilities include design and development of custom macro using Schematic design at block level (Ex RegArray, memory subsystem) Frontend verification and model generations CLP/PAGLS/LEC verifications at block level. Functional verification using spice/gatesim. Timing Signoff using PT, Candidate should be able to collaborate with different teams. Skillset/Experience: 2-10 year of experience: Strong knowledge in transistor circuit design& block level logic design of Memory subsystem & Data path. STA for the design to close Set-up, Hold, MPW, Transition, etc Design verification using ESPCV & LEC, Simulation using Finesim & HSPICE. Front-end RTL Design (Verilog RTL design, System Verilog, Synopsys Design Compiler, Cadence RTL Compiler, LEC, PLDRC, Static Timing Analysis and PTPX) Physical Design using industry-standard RTL2GDS flow including Synopsys ICC2, Cadence Encounter. Scripting in Perl/Python/Shell/Tcl for productivity is a plus IP development (custom macro transistor level design, physical integration, collateral generation, flow development) and PPA quantification. Interface with Process Technology Team to understand the complex DRC and DFM requirements of the advanced technology nodes Work with cross functional teams (Architecture, Test/Verification , Product, CAD, Layout, Physical Design) to gather/define/implement specs Transistor level implementation of the block using CMOS/Domino/Cell-Based/Data path styles Implement power/clock gating techniques, Implement power/clock gating techniques, Implement industry standard as well as custom DFT techniques Implement clock distribution using custom/CTS techniques for low skew/latency/power, Implement block layout using custom/compiler techniques using custom/semi-custom/stdcell libraries Implement block level floor planning using custom and/or tiling techniques

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm GPU team is actively seeking candidates for several physical design engineering positions. Graphics HW team in Bangalore is part of a worldwide team responsible for developing and delivering GPU solutions which are setting the benchmark in mobile computing industry.Team is involved in Architecture, Design, Verification, implementation and Productization of GPU IP COREs that go into Qualcomm Snapdragon SOC Products used in Smartphone, Compute, Automotive, AR/VR and other low power devices. Qualcomm has strong portfolio of GPU COREs and engineers get an opportunity to work with world class engineering team that leads industry through innovation and disciplined execution. As a Graphics physical design engineer, you will innovate, develop, and implement GPU cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power GPU COREs. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals. Additional responsibilities in this role involves good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, debugging and fixing violations and formal verification. The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex Physical Design solutions from netlist and timing constraints to the final product. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelor's/Master’s degree in Electrical/Electronic Engineering from reputed institution 8+ years of experience in Physical Design/Implementation Minimum Physical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description: We are seeking a highly skilled and experienced System Architect, Hardware Engineer or Applications Engineer to join our dynamic team. The ideal candidate will work closely with System Level Architects to design and define block diagrams, schematics, and electrical requirements for our cutting-edge projects for memory packaging. This role requires a deep understanding of hardware design, package design and system architecture, as well as the ability to collaborate effectively with cross-functional teams. Key Responsibilities: Collaborate with System Level Architects to design and define block diagrams, schematics, and electrical requirements. Develop and implement hardware solutions that meet package specifications and requirements. Conduct detailed analysis and verification of system-in-package interfaces to ensure correct performance and reliability. Work closely with firmware & product engineers to ensure seamless integration of system-in-package product solutions. Provide technical guidance and support to junior engineers and other team members. Stay current with industry trends and advancements in hardware technology to ensure our solutions remain competitive and innovative. Prepare and present technical documentation and reports to stakeholders. Qualifications: Master's degree in Electrical Engineering, Computer Engineering, or a related field with 8-10 years of experience, or a PhD with 6-8 years of experience. Proven experience in hardware design and development, including block diagrams, schematics, and electrical requirements. Strong understanding of system architecture and the ability to work collaboratively with System Level Architects. Experience with common ASIC and processor architectures applicable to mNAND and SSD ASICs, such as ARM, RISC-V, and custom ASIC designs. Proficiency in hardware design tools and software. Excellent problem-solving skills and attention to detail. Strong communication and interpersonal skills. Ability to work effectively in a fast-paced and dynamic environment. Familiarity with NAND flash memory technology and SSD controller design. Proficiency in EDA schematic and simulation tools such as Cadence Allegro System Capture, Synopsys Design Compiler, Mentor Graphics PADS, Altium Designer, and OrCAD. Experience with logic verification tools such as Synopsys VCS, Cadence Incisive, and Mentor Graphics ModelSim. Preferred Skills: Experience with advanced hardware technologies and methodologies. Knowledge of industry standards and best practices in hardware design. Familiarity with software development and integration. Benefits: Competitive salary and benefits package. Opportunity to work on innovative and challenging projects. Collaborative and supportive work environment. Professional development and growth opportunities. About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. AI alert : Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

Job Requirements Define and implement DFT architecture and strategy for complex SoCs and ASICs Insert and verify scan chains, MBIST, LBIST, boundary scan (JTAG), and other test structures Develop and maintain ATPG (Automatic Test Pattern Generation) patterns and flows Work closely with RTL designers, verification teams, and physical design teams to ensure DFT requirements are met Debug DFT-related issues during simulation, emulation, and silicon bring-up Perform timing analysis and constraints development for DFT logic Drive silicon validation and yield improvement initiatives related to DFT Document DFT design and verification methodology Bachelor’s or Master’s degree in Electronics 4–8 years of hands-on experience in VLSI DFT Strong expertise in scan insertion, ATPG, MBIST/LBIST, and JTAG implementation Proficiency with DFT tools (Synopsys DFT Compiler, Tetramax, Cadence Modus, Mentor Tessent, etc.) Good understanding of RTL design, synthesis, and timing closure Experience with silicon bring-up and production test support Excellent problem-solving and debugging skills Strong communication and teamwork abilities Experience in low-power DFT techniques Familiarity with scripting (Perl, Python, Tcl) for automation Work Experience Strong expertise in scan insertion, ATPG, MBIST/LBIST, and JTAG implementation Proficiency with DFT tools (Synopsys DFT Compiler, Tetramax, Cadence Modus, Mentor Tessent, etc.) Experience in low-power DFT techniques Familiarity with scripting (Perl, Python, Tcl) for automation Good understanding of RTL design, synthesis, and timing closure

Job Requirements Define and implement DFT architecture and strategy for complex SoCs and ASICs Insert and verify scan chains, MBIST, LBIST, boundary scan (JTAG), and other test structures Develop and maintain ATPG (Automatic Test Pattern Generation) patterns and flows Work closely with RTL designers, verification teams, and physical design teams to ensure DFT requirements are met Debug DFT-related issues during simulation, emulation, and silicon bring-up Perform timing analysis and constraints development for DFT logic Drive silicon validation and yield improvement initiatives related to DFT Document DFT design and verification methodology Strong expertise in scan insertion, ATPG, MBIST/LBIST, and JTAG implementation Proficiency with DFT tools (Synopsys DFT Compiler, Tetramax, Cadence Modus, Mentor Tessent, etc.) Good understanding of RTL design, synthesis, and timing closure Knowledge of safety-critical or automotive DFT requirements (ISO 26262) Familiarity with scripting (Perl, Python, Tcl) for automation Excellent problem-solving and debugging skills Strong communication and teamwork abilities Work Experience Strong expertise in scan insertion, ATPG, MBIST/LBIST, and JTAG implementation Proficiency with DFT tools (Synopsys DFT Compiler, Tetramax, Cadence Modus, Mentor Tessent, etc.) Good understanding of RTL design, synthesis, and timing closure Knowledge of safety-critical or automotive DFT requirements (ISO 26262) Familiarity with scripting (Perl, Python, Tcl) for automation Excellent problem-solving and debugging skills Strong communication and teamwork abilities

Category Engineering Hire Type Employee Job ID 10619 Remote Eligible No Date Posted 17/04/2025 Position : R&D Engineer, Staff You will be part of an excellent development team in System Level Design space involved in creation of Virtual Prototypes (simulation models) for SoCs/MCUs/ECUs and bring up of Linux/Android/AutoSar OS/Embedded SW applications, catering to early Software Development & Testing use cases for Automotive, Datacentre, AI and Mobile products. The role is for a Staff R&D engineer having the required technical skills or the ability to build the required skills quickly. Education : BE / B. Tech / M.Tech in Computer Science or Electronics with 6+ Years of relevant experience Work location - Noida, Bangalore Technology Specific skills: Contribute in modelling, integration and testing of various peripherals, inside a SystemC based platform modelling framework, for different application domains like Automotive, Wireless etc. Understand IP modelling requirements and create ESL model specifications along-with effective closure of open technical issues. Ability to guide junior members, consultants in projects involving SoC platform creation, validation and SW bring-up. Technical Attributes: Mandatory: Proficiency in C/C++ Excellent problem-solving skills Experience in application development in assembly or higher-level languages. Preferred: Understanding of SoC architectures Understanding of serial bus protocols like CAN, LIN, SPI, I2C etc Experience in SoC peripherals modelling using C/C++/SystemC/HDL. Experience in multi-core-based platform developments. Personal Attributes : High energy person with the willingness to go an extra mile A team player with customer facing skills Good written and verbal communication skills High level of initiative and accountability towards assigned tasks Ability to prioritize and work independently on multiple tasks At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

This is a full-time on-site role for a Standard Cell & Memory Characterization Engineer located in Hyderabad. The Engineer will be responsible for the day-to-day tasks of developing standard cells and memory characterization methodologies, performing detailed analysis and verification, conducting research, and working with wireless technologies. The role requires a collaborative approach to problem-solving and a commitment to quality and precision in delivering engineering solutions. STD Cell Characterization (PrimeLib, Silicon Smart) Able to characterize basic standard cells. Static & Timig Analysis of SRAM and DRAM. Writing constraints and analysing the STA report. Reporting violations to design team. STA at block/top/cell level .lib QA, ARC files, timing constraints DRAM circuit/block-level analysis Parasitic extraction, tape-out support EDA Tools: Synopsys, Cadence, TCL, Python

Job Details Job Description: As a Intern Engineer, you will be responsible for chip designing, verifying, and optimizing digital circuits and systems. You will work closely with our engineering team to ensure high-quality and efficient design processes using industry-standard EDA tools. Key Responsibilities Collaborate with the design team to develop RTL (Register Transfer Level) designs for digital circuits. Perform verification and structural design tasks to ensure functionality and performance. Utilize standard EDA tools from Synopsys, Cadence, or Mentor Graphics for design and verification processes. Assist in the layout design and optimization of VLSI circuits. Participate in design reviews and provide technical insights to improve design quality. Qualifications Qualifications: Basic understanding of RTL, verification, and structural design in VLSI. Strong grasp of digital design concepts and basic VLSI layout principles. Experience with standard EDA tools from Synopsys, Cadence, or Mentor Graphics. Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. Excellent problem-solving skills and attention to detail. Strong communication skills and ability to work collaboratively in a team environment. Preferred Qualifications Familiarity with scripting languages for automation in design processes. Knowledge of semiconductor manufacturing processes. Educational Qualifications Candidate pursuing B.Tech/M.Tech in Electronics and communication/VLSI (2026 Passing only) Note: 2026 passing candidate would be considered for this role. Job Type Student / Intern Shift Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business Group Intel Labs is the company's world-class, industry leading research organization, responsible for driving Intel's technology pipeline and creating new opportunities. The mission of Intel Labs is to deliver breakthrough technologies to fuel Intel's growth. This includes identifying and exploring compelling new technologies and high risk opportunities ahead of business unit investment and demonstrating first-to-market technologies and innovative new usages for computing technology. Intel Labs engages the leading thinkers in academia and industry in addition to partnering closely with Intel business units. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. Legal Disclaimer It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Design for Testability (DFT) Good to have skills : NAMinimum 3 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your day will involve overseeing the application development process, coordinating with team members, and ensuring project milestones are met. Roles & Responsibilities:Bachelors degree in computer science, Electronics Engineering or related fields and 6+ years of related professional experience.Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at-least couple of DesignsCore DFT skills considered crucial for this position should include some of the following Scan compression and insertion, Memory BIST, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate-level verification, silicon debugUnderstanding of DFT Flows and Methodologies and Experience with Cadence/Mentor/Synopsys Tool set (Genus,Modus,NCSim / DC,Tessent,Spyglass/Tmax)Experience coding in Verilog RTL, and scripting language like TCL, and/or PerlProficient in Unix/Linux environmentsStrong fundamentals in Digital Circuit Design and Logic Design are required. Professional & Technical Skills: - Must To Have Skills: Proficiency in Design for Testability (DFT)- Strong understanding of software development methodologies- Experience in leading and managing software development projects- Knowledge of technologies and tools used in software development- Excellent communication and interpersonal skills Additional Information:- The candidate should have a minimum of 5 years of experience in Design for Testability (DFT)- This position is based at our Chennai office- A 15 years full time education is required Qualification 15 years full time education

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description We are seeking a highly skilled and experienced System Architect, Hardware Engineer or Applications Engineer to join our dynamic team. The ideal candidate will work closely with System Level Architects to design and define block diagrams, schematics, and electrical requirements for our cutting-edge projects for memory packaging. This role requires a deep understanding of hardware design, package design and system architecture, as well as the ability to collaborate effectively with cross-functional teams. Key Responsibilities Collaborate with System Level Architects to design and define block diagrams, schematics, and electrical requirements. Develop and implement hardware solutions that meet package specifications and requirements. Conduct detailed analysis and verification of system-in-package interfaces to ensure correct performance and reliability. Work closely with firmware & product engineers to ensure seamless integration of system-in-package product solutions. Provide technical guidance and support to junior engineers and other team members. Stay current with industry trends and advancements in hardware technology to ensure our solutions remain competitive and innovative. Prepare and present technical documentation and reports to stakeholders. Qualifications Master's degree in Electrical Engineering, Computer Engineering, or a related field with 8-10 years of experience, or a PhD with 6-8 years of experience. Proven experience in hardware design and development, including block diagrams, schematics, and electrical requirements. Strong understanding of system architecture and the ability to work collaboratively with System Level Architects. Experience with common ASIC and processor architectures applicable to mNAND and SSD ASICs, such as ARM, RISC-V, and custom ASIC designs. Proficiency in hardware design tools and software. Excellent problem-solving skills and attention to detail. Strong communication and interpersonal skills. Ability to work effectively in a fast-paced and dynamic environment. Familiarity with NAND flash memory technology and SSD controller design. Proficiency in EDA schematic and simulation tools such as Cadence Allegro System Capture, Synopsys Design Compiler, Mentor Graphics PADS, Altium Designer, and OrCAD. Experience with logic verification tools such as Synopsys VCS, Cadence Incisive, and Mentor Graphics ModelSim. Preferred Skills Experience with advanced hardware technologies and methodologies. Knowledge of industry standards and best practices in hardware design. Familiarity with software development and integration. Benefits Competitive salary and benefits package. Opportunity to work on innovative and challenging projects. Collaborative and supportive work environment. Professional development and growth opportunities. About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. AI alert : Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

Position: Senior Memory Design Engineer Location: Bangalore / Noida Responsibilities: As Memory Design Engineer, we will work on developing memory compilers and memory Fast Cache instances for our next generation Cores achieving outstanding PPA. Required Skills and Experience : Understanding of computer architecture and concepts. Basic understanding of CMOS Transistors, their behaviors. Understanding of high speed/low power CMOS circuit design, clocking scheme, Static and complex logic circuits. Understanding of Power versus Performance versus Area trade-offs in typical CMOS design. You have an engineering demeanor and Passion for Circuit design. Expected to have good interpersonal skills. Minimum 2 Yrs of experience in SRAM / memory design Margin, Char and its related quality checks. Nice To Have Skills and Experience : You know basic scripting languages, e.g. Perl/TCL/Python. Some Experience of working on Cadence or Synopsys flows. Experience with Circuit Simulation and Optimization of standard cells. Interested candidates can apply/share/refer profile at Krishnaprasath.s@acldigital.com

Principal Physical Design Engineer Greater Bangalore -Hybrid/Hyderabad (Hybrid ) PrincipalPhysical Design Engineer Company Background We are a well-funded, stealth-mode startup based in Mountain View, CA, founded by senior technical and business executives hailing from category leaders in infrastructure semiconductors and hyperscale cloud services, and backed by top-tier investors with an immensely successful formula & track record on early-stage investments. We are a diverse team of expert chip/software/systems architects and developers who excel in hardware/software solution co-design. Our team has built, and delivered into production, technologies that process over half of the world's global data center traffic. Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, from CAD tool flow setup, early floorplan exploration in conjunction with microarchitecture development, through block partitioning, power planning, clock network design and construction, through P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout. Roles and Responsibilities Build and support the CAD tool flow for physical implementation in a cloud-first development environment. Work with architects and microarchitects on the chip-level floorplan and block partitioning. Evaluate tradeoffs in functional partitioning, block size, and interface complexity with other stakeholders. Define and construct the major physical structures, including the clock and reset architecture, the power delivery network, and interconnect topologies. Execute on block-level, cluster-level, and top-level physical implementation, from synthesis, floorplan and power plan, through P+R, through timing closure, physical verification, and tapeout. Interface with foundry and library partners on 3rd party IP and process technology issues, including updates to device models, IP integration requirements, and pre-tapeout signoff. Skills/Qualifications : Proven industry experience and successful track record in the physical implementation of large, high-performance network switching/routing fabrics (Ethernet, Infiniband, HPC), Network Interface Controllers, Smart-NICs, CPUs, or GPUs in the latest silicon process nodes. Deep experience with the latest CAD tools through the entire physical design workflow, e.g., Cadence Genus and Innovus, Synopsys ICC2/FusionCompiler, Tempus, PrimeTime SI, PrimeTime PX, StarRC, ICV, Calibre. Strong familiarity with various analysis tools such as Redhawk, Voltus. Experience with circuit analysis using HSPICE is a plus. Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages. Minimum BSEE/CE + 12 years or MSEE/CE + 10 years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"