We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and dedicated individual with a strong background in Electronics and Communication Engineering or Computer Science. You have a keen interest in software development and system validation, and you are eager to apply your skills in a dynamic and innovative environment. You thrive on solving complex problems and are always ready to take on new challenges. Your technical prowess is complemented by your excellent communication skills, making you an effective team player and a valuable contributor to any project. You have a meticulous eye for detail and a commitment to delivering high-quality work. You are not only technically proficient but also adaptable, able to quickly learn new tools and methodologies. Your previous experience in embedded systems, board-level testing, and programming in C/C++ sets you apart, and you are excited about the opportunity to work with high-speed serial interfaces and FPGA-based setups. Your proactive approach and analytical mindset enable you to excel in a fast-paced, collaborative environment. What You’ll Be Doing: Developing and testing software for validation and automation purposes. Performing device-level and system-level validation and debug in post-silicon environments. Executing software tests in verification environments to ensure product quality. Working with FPGA-based setups to run validation tests and update FPGA RTL modules as needed. Creating detailed test and validation reports with statistical analysis. Interfacing with customers to capture requirements and provide post-release support. The Impact You Will Have: Contributing to the development of cutting-edge technology that drives innovation in various industries. Ensuring the reliability and performance of high-speed serial interface PHYs like USB, PCIe, and Ethernet. Enhancing the validation and debug processes through meticulous testing and analysis. Improving the overall quality and functionality of Synopsys products through rigorous validation. Supporting the continuous improvement of product development cycles. Providing valuable insights and feedback to enhance future product iterations. What You’ll Need: B.Tech in ECE/CS or equivalent with 3-7 years of previous experience in a similar role/industry. Experience in programming and testing using C/C++. Board-level test and debug experience using lab equipment. Experience with embedded or resource-constrained environments. Development experience on Unix, Linux, and Windows platforms. Ability to quickly learn new workflows and adapt to new technologies. Exposure to MATLAB/Python programming is a plus. Exposure to verification and basic RTL is a plus. Excellent verbal and written communication skills. Who You Are: A proactive and motivated individual with a passion for technology and innovation. An effective communicator who can articulate technical concepts clearly and concisely. A team player who collaborates well with others and contributes to collective goals. A detail-oriented professional with a strong analytical mindset. An adaptable learner who thrives in dynamic environments and embraces new challenges. The Team You’ll Be A Part Of: You will be part of a dedicated team focused on the development and validation of high-speed serial interfaces and embedded systems. The team collaborates closely to ensure the quality and performance of Synopsys products, leveraging a diverse set of skills and expertise. You will work alongside experienced engineers who are passionate about technology and committed to driving innovation. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 11861 Date posted 06/03/2025 Description Candidate will be part of TCM Front End team. Design, develop, troubleshoot the core algorithms used in TCM Front End tool Design and develop standard and customized features / checks in TCM FE for seamless consumption of VCS OM. Will be working with other local and global teams of TCM and VC SpyGlass Design and development of state-of-the-art EDA tools involving development of new and innovative algorithms. Create test cases to test the developed feature. Skills Required Strong knowledge of Front-end compilers and their flow Ability to develop new software architecture and good leadership skills. Fluent in C/C++ with extensive work experience in data-structures and algorithms. Good knowledge of Verilog, SystemVerilog & VHDL HDL. Excellent algorithm analysis skills and a good knowledge of data structures. Familiarity with ASIC design flow and the EDA tools and methodologies used therein. Familiarity with multi-threaded and distributed code development. Self-motivation, self- discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. Quality focus - one who believes in quality and wants to make a difference. Experience of production code development on Unix/Linux platforms. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Job Details: Job Description: Designs, develops, and builds analog circuits in advanced process nodes for analog and mixed signal IPs. Designs floorplans, performs circuit design, extracts chip parameters, and simulates analog behavior models. Creates test plans to verify design according to circuit and block microarchitecture specifications and evaluates test results. Verifies functionality to optimize circuit for power, performance, area, timing, and yield goals. Collaborates cross functionally to report design progress and collects, tracks, and resolves any performance and circuit design issues. Optimizes performance, power, area, and reduces leakage of circuits. Works with architecture and layout team to design circuit for best functionality, robustness, and electrical capabilities. Qualifications: Qualifications: B.Tech / M.Tech/ Phd with hands-on experience in high-speed analog circuit design, with a proven track record of successful projects. Expertise in designing and verifying analog circuits such as High-speed transmitter, receiver, amplifiers, PLLs, voltage regulators, and data converters. Proficiency in using EDA tools like Cadence Virtuoso, SPICE, or Synopsys.

Role & responsibilities Physical Design Engineer (PD/STA/Synthesis) Must-Haves: •Tools: Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime for STA •Flow Experience: •Floorplanning •Power planning •Placement •Clock Tree Synthesis (CTS) •Routing •Physical Verification (DRC/LVS) •Timing Closure •Knowledge of: •Low-power design (UPF/CPF) •ECOs •IR Drop, EM Analysis •STA constraints and timing analysis Nice-to-Haves: •Experience with block-level and/or full-chip PD •Familiarity with scripting (Tcl, Perl, Python)

Lead Verification Engineer Experience: 10+ Years Location:[Bangalore| Ahmedabad | Pune| Hyderabad] Employment Type: Full-Time Job Description: We are seeking a highly skilled and motivated Design Verification Engineer with 10+ years of hands-on experience in SoC verification. The ideal candidate will be responsible for developing and executing comprehensive verification plans for high-performance SoCs, collaborating with cross-functional teams, and ensuring quality standards are met throughout the verification cycle. Key Responsibilities: Drive SoC Design Verification efforts for complex projects, ensuring thorough validation of functionality and performance. Develop and implement verification strategies, including test plans and test benches for both low-speed peripherals (I2C/I3C, SPI, UART, GPIO, QSPI) and high-speed interfaces (PCIe, Ethernet, CXL, MIPI, DDR, HBM). Conduct Gate-level simulations and power-aware verification using Xprop and UPF. Collaborate with architects, designers, and pre/post-silicon teams to define and validate verification requirements. Implement and analyze System Verilog assertions and coverage (functional, toggle, code). Guide and mentor junior verification engineers while fostering a collaborative and innovative team environment. Ensure verification signoff criteria are met, with complete and accurate documentation. Contribute to continuous improvement of verification methodologies and best practices. Integrate third-party VIPs from Synopsys and Cadence. Required Skills & Experience: Strong expertise in UVM and System Verilog-based verification environments. Hands-on experience with: SoC-level and IP-level verification DDR, HBM, Xprop, and UPF-based simulations Processor-based SoC verification environments (native, Verilog, System Verilog, UVM) Proficiency in verification tools like VCS, Xsim, waveform analyzers. Solid experience in scripting (Shell, Makefile, Perl) and C-SystemVerilog handshaking. Strong understanding of test practices and adherence to verification quality standards. Problem-solving mindset with excellent analytical and debugging skills. Qualifications: Bachelor’s, Master’s, or PhD in Computer Science, Electrical/Electronics Engineering, or a related field. 10+ years of relevant experience in SoC design verification. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled and passionate individual with a strong background in semiconductor manufacturing technology and device physics. You hold a PhD in Electrical Engineering or Physics and have a deep understanding of numerical methods. You possess excellent IT skills, particularly in Linux as well as Python and TCL scripting. With at least three years of experience using TCAD simulation tools, you are adept at both pre-sales and post-sales activities, including technical support, customer relationship management, technical training, and presentation delivery. You thrive in a dynamic environment, working closely with R&D, Sales, Marketing, and customers to drive the development and acceptance of cutting-edge TCAD products. What You’ll Be Doing: Serving as the primary technical interface with customers, assisting them in evaluating, using, and applying TCAD tools. Providing technical support, troubleshooting, and resolving complex issues related to TCAD products. Managing new and existing customer relationships, ensuring high levels of customer satisfaction. Preparing and delivering technical training and presentations to customers and internal teams. Conducting beta testing, benchmarking, and onsite evaluations to support product development and customer needs. Collaborating with R&D to specify new features and drive continuous product improvement. The Impact You Will Have: Enhancing customer experience and satisfaction with Synopsys TCAD products. Driving the successful adoption and integration of TCAD tools in leading semiconductor companies. Contributing to the development and refinement of state-of-the-art TCAD tools. Strengthening Synopsys' market position through exceptional technical support and customer engagement. Facilitating knowledge transfer and training to empower customers and internal teams. Playing a key role in the continuous innovation and advancement of semiconductor technology. What You’ll Need: PhD in Electrical Engineering, Physics, or a related field. Strong background in semiconductor manufacturing technology and device physics. Proficiency in numerical methods and simulation tools. Excellent IT skills, particularly in Linux, Python, and TCL scripting. Minimum of three years of experience with TCAD simulation tools. Who You Are: A proactive and customer-oriented professional with excellent communication skills. Detail-oriented with strong problem-solving abilities. A collaborative team player who thrives in a dynamic environment. Adaptable and able to manage multiple priorities effectively. Passionate about technological innovation and continuous learning. The Team You’ll Be A Part Of: You will be part of a dynamic and innovative team focused on driving the development and adoption of Synopsys TCAD products. Collaborating closely with R&D, Sales, Marketing, and customers, you will play a crucial role in ensuring the success and continuous improvement of our cutting-edge semiconductor technology solutions. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled engineer with 6-10 years of experience, passionate about developing cutting-edge emulation solutions for industry-standard protocols such as PCIe, CXL, and UCIe. You possess a strong background in software development using C/C++ and synthesizable RTL development with Verilog. Your deep understanding of digital design concepts, HDL languages, and scripting languages like Python or Perl will be invaluable in this role. You thrive in collaborative environments, have excellent communication skills, and are adept at solving complex problems. Your ability to interact with customers during deployment and debug processes will ensure successful implementation and satisfaction. A B.E/B.Tech/M.Tech in Electronic & Communication or Computer Science Engineering is essential. Knowledge of ARM architecture, UVM, and functional verification, along with experience in emulation, will be a significant advantage. What You’ll Be Doing: Developing emulation solutions for PCIe, CXL, and UCIe protocols for semiconductor customers. Engaging in software development using C/C++ and synthesizable RTL development with Verilog. Verifying solutions to ensure high performance and reliability. Interacting with customers during the deployment and debug phases to ensure smooth implementation. Collaborating with cross-functional teams to integrate emulation solutions. Maintaining and enhancing existing emulation solutions to meet evolving industry standards. The Impact You Will Have: Driving the development of advanced emulation solutions that meet industry standards. Enhancing the performance and reliability of semiconductor products through innovative solutions. Ensuring customer satisfaction by providing robust and efficient deployment support. Contributing to the continuous improvement of Synopsys' emulation technologies. Supporting the adoption of new protocols and standards in the semiconductor industry. Strengthening Synopsys' position as a leader in chip design and verification solutions. What You’ll Need: 5+ years of relevant experience In-depth knowledge of PCIe, CXL, and UCIe protocols. Proficiency in C/C++ programming and object-oriented programming concepts. Strong understanding of digital design principles and HDL languages such as System Verilog and Verilog. Experience with scripting languages like Python, Perl, or TCL. Familiarity with ARM architecture and UVM/functional verification is a plus. Who You Are: A collaborative team player with excellent communication skills. A problem-solver with a keen eye for detail and a passion for innovation. Adaptable and able to work effectively in a fast-paced, dynamic environment. Customer-focused, with the ability to handle deployment and debugging challenges efficiently. Committed to continuous learning and staying updated with industry advancements. The Team You’ll Be A Part Of: You will be part of a dynamic team focused on developing and enhancing emulation solutions for cutting-edge semiconductor technologies. Our team collaborates closely with various departments to ensure the highest quality and performance of our products, driving innovation and excellence in the industry. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Alternate Job Titles: Senior Digital Design Engineer ASIC Design Engineer High-Speed SerDes Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated and experienced ASIC Digital Design Engineer with a strong background in digital design for high-speed serial interfaces. You have a deep understanding of USB, PCIe, Ethernet, Display, and HDMI protocol standards, and you thrive in a collaborative environment. Your expertise in Verilog RTL design, microarchitecture, and timing constraints development makes you a valuable asset to any team. You are adept at using tools like Spyglass for CDC/RDC/Lint and have excellent debugging skills. Your ability to propose and implement design updates based on various requirements, coupled with your experience in test coverage and physical design timing closure, sets you apart as a leader in your field. With a passion for innovation and a keen eye for detail, you are ready to take on new challenges and contribute to the success of Synopsys. What You’ll Be Doing: Driving and working on digital design for high-speed serial interface PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards. Proposing micro-architecture of design/design updates based on customer requirements, analog requirements, system performance improvements, Link layer interface changes, or overall robustness of design. Implementing RTL in Verilog and running Spyglass CDC/RDC/Lint. Collaborating with verification teams to test desired functionality and corner cases. Developing timing constraints, DFT insertion, and test coverage, and closing timing with physical design teams. Well versed in Micro-Architecture and Block Ownership, Design from scratch. The Impact You Will Have: Enhancing the performance and reliability of high-speed serial interface PHY IPs. Contributing to the development of cutting-edge technologies that power modern electronics. Driving innovation in digital design and influencing the future of semiconductor technology. Collaborating with cross-functional teams to deliver robust and high-quality designs. Ensuring that Synopsys remains a leader in the semiconductor industry through continuous improvement and excellence. Supporting customers by providing high-performance and reliable IP solutions that meet their needs. What You’ll Need: 5-8 years of relevant experience in digital design for ASICs. Strong knowledge of Verilog RTL design and microarchitecture. Experience with timing constraints development and synthesis flow. Proficiency in using Spyglass or similar tools for Lint/CDC/RDC. Proficiency in scripting and automation using TCL, PERL, or Python. Excellent debugging skills and attention to detail. Who You Are: A collaborative team player with strong communication skills. A problem solver with a proactive approach to challenges. A detail-oriented professional with a passion for innovation. A self-motivated individual who thrives in a fast-paced environment. An adaptable engineer who can handle multiple tasks and priorities. The Team You’ll Be A Part Of: You will be part of the High-Speed SerDes Digital Design Team, a group of talented engineers dedicated to developing high-performance serial link PHY IPs. The team focuses on innovation, quality, and collaboration to deliver industry-leading solutions. Together, you will work on challenging projects that push the boundaries of technology and make a significant impact on the semiconductor industry. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

About Tata Electronics Private Limited Tata Electronics Pvt. Ltd. is a prominent global player in the electronics manufacturing industry, with fast-emerging capabilities in Electronics Manufacturing Services, Semiconductor Assembly & Test, Semiconductor Foundry, and Design Services. Established in 2020 as a greenfield venture of the Tata Group, the company aims to serve global customers through integrated offerings across a trusted electronics and semiconductor value chain. With a rapidly growing workforce, the company currently employs over 65,000 people and has significant operations in Gujarat, Assam, Tamil Nadu, and Karnataka, India. Tata Electronics is committed to creating a socioeconomic footprint by employing many women in its workforce and actively supporting local communities through initiatives in environment, education, healthcare, sports and livelihood. About the Job Description: Job Overview: Person will be responsible for developing multiple test chips for IP verification and drive optimized full-chip architecture for modular design. Will continue to push the boundaries of innovation by developing architectures that inherently support testability, with the objective of achieving zero-defect silicon. This will be driven by a "correct-by-construction" mindset throughout the design process. The role necessitates a comprehensive understanding and active involvement in all facets of VLSI development, including microarchitecture and platform architecture, front-end design, and design convergence. Additionally, the candidate will be responsible for overseeing the physical design and verification processes. Job Description: Full chip design for multimillion gates SoC Digital design and development (RTL) Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification Manage IP dependencies, planning and tracking of all front-end design related tasks Driving the project milestones across the design, verification and physical implementations Minimum Qualifications: Minimum 12 years of solid experience Test Chip / SoC design Solid expertise and understanding of digital design concepts. Developing architecture and micro-architecture from specs Understanding of JTAG base test chip architecture for IP testability and enable programmable registers for IP testability Ability to review full chip top level test plans Hands-on working knowledge and expertise in FEV, Cadence LEC & Synopsys Design Compiler Synthesis. Ability to make effective decisions, even with incomplete information when time is of essence. Working knowledge of timing closure is a must. Work on key design collaterals such as SDC and UPF flows. Work with key stakeholders like PD, DFT and Verification to discuss the right collateral quality and identify solutions/workarounds. Demonstrated good post silicon bring up and debug experience Demonstrated good SoC/ Test-Chip integration exposure and its challenges Demonstrated good exposure to design verification aspects Having SoC specification to GDS to commercialization experience is highly desired Should possess a strong understanding of a particular technical area and accumulated significant experience in this area and other related areas. Provides direction, mentoring, and leadership to a small to medium sized groups. Should possess strong communication and leadership skills to ensure effective communication with Program Perform RTL coding for SS/SOC integration, function/performance simulation debug, Lint/CDC/FV/UPF checks. Own the Clock-Domain crossing, Linting aspects of the overall design of the IP and the subsystem. Conduct timely review of the RTL progress and work with program managers to provide weekly update on the progress towards RTL milestones completion. Work closely with DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design Should possess expertise in front-end EDA tools sign-off and its flows. Ability to program with scripting languages such as Python or Perl is a plus. Highly motivated to seek out solutions and willing to learn new skills to fulfil job requirements. Proven interpersonal skills, leadership and teamwork. Understanding of various bus protocols AHB, AXI and peripherals like USB, SDCC Understanding of Memory controller designs and Microprocessors is an added advantage Understanding of Chip IO design and packaging is an added advantage Show more Show less

Physical Design Engineer (PD/STA/Synthesis) Must-Haves: • Tools: Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime for STA • Flow Experience: • Floorplanning • Power planning • Placement • Clock Tree Synthesis (CTS) • Routing • Physical Verification (DRC/LVS) • Timing Closure • Knowledge of: • Low-power design (UPF/CPF) • ECOs • IR Drop, EM Analysis • STA constraints and timing analysis Nice-to-Haves: • Experience with block-level and/or full-chip PD • Familiarity with scripting (Tcl, Perl, Python) Show more Show less

Hyderabad, Telangana, India Category: Engineering Hire Type: Employee Job ID 9973 Date posted 06/02/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled and motivated software developer with a strong foundation in C++ and Python programming and experience in data analysis. You are familiar with Machine Learning (ML) applied to data analysis and optimization problems. Your collaborative nature allows you to work seamlessly with cross-functional teams, including product application engineering (PAE) and front-end development teams, to deliver intuitive and effective solutions for our customers. You thrive in a dynamic, international environment and are eager to learn and new technologies to advance our TCAD products. Your ability to communicate complex technical concepts clearly and effectively makes you an invaluable asset to our team. What You’ll Be Doing: Design and implement Data Ingestion & Processing pipelines for our Sentaurus Calibration Workbench (SCW) – Format support, validation, DB with search/filters, AI/ML-driven analysis. Integrate core TCAD simulation engines with SCW – Optimize connectivity to reduce turnaround time (TAT), improve scalability, quality of results (QoR), and ease-of-use (EoU) Collaborate closely with the product application engineering (PAE) team to ensure functionality and quality requirements are met. Collaborate closely with the front-end team to ensure backend features are seamlessly integrated into the GUI for end-users. The Impact You Will Have: Drive advancements in TCAD calibration automation, leading to significant improvements in simulation efficiency and accuracy. Enhance the user experience by supporting integration of backend features into a user-friendly GUI, enabling seamless deployment of calibration workflows to customers. Support the creation of innovative solutions that address complex semiconductor design challenges, contributing to the success of our customers. Streamline the TCAD calibration process, reducing TAT and improving overall productivity for both internal teams and customers. Foster collaboration and knowledge sharing within the team, driving continuous improvement and innovation in SCW. What You’ll Need: MS or PhD in Computer Science, Software Engineering, Electrical Engineering, or equivalent. 4+ years of hands-on experience in software development with solid programming skills in C++ and Python. Solid data analysis knowledge and skills. Familiarity and hands-on experience with ML applied to data analysis and optimization. Strong desire to learn and explore new technologies. English language working proficiency and communication skills allowing teamwork in an international environment. Willingness to work in a distributed international team. Who You Are: You are a proactive and innovative engineer with a passion for technology and a keen eye for detail. Your strong analytical skills enable you to solve complex problems efficiently, and your collaborative spirit ensures successful teamwork across diverse teams. You are adaptable and open to learning, always seeking to enhance your skills and contribute to the team's success. With excellent communication skills, you effectively convey technical concepts and foster a positive and productive work environment. The Team You’ll Be A Part Of: You will join the Sentaurus Calibration Workbench (SCW) team, a dynamic group of experts dedicated to developing and optimizing calibration workflows for TCAD simulation models. Our team collaborates closely with the product application engineering (PAE) team and front-end developers to deliver cutting-edge solutions that meet the evolving needs of our customers. We are committed to continuous innovation and excellence, driving advancements that shape the future of semiconductor technology. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Senior SoC Director / SoC Director Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/Bangalore A US based well-funded product-based startup looking for highly talented SoC Director for the following roles Senior Director / SoC Director of SOC is : Trust, loyalty, and ability to command Technical respect with foreign partners after having Taped out Successfully multiple chips to high volume production….this should be easily achieved under his/her belt !!!!!!!! Somebody we can trust to drive on the World stage without embarrassing us Job Description: We are seeking an experienced professional to lead full chip design for multi-million gate SoCs. The ideal candidate will have expertise in digital design and RTL development, with a deep understanding of the design convergence cycle, including architecture, micro-architecture, synthesis, timing closure, and verification. Key Responsibilities: Proficiency in Interconnect Fabric Cache Coherency D2D C2C Oversee full chip design for complex SoCs. Develop and implement digital designs (RTL). Manage IP dependencies and track all front-end design tasks. Drive project milestones across design, verification, and physical implementation phases. Qualifications: At least 18-25 years of solid experience in SoC design. Proven ability to develop architecture and micro-architecture from specifications. Familiarity with bus protocols such as AHB and AXI, as well as peripherals like QSPI, NVMe, and I3C. Knowledge of memory controller designs and microprocessors is a plus. Understanding of chip I/O design and packaging is advantageous. Experience in reviewing top-level test plans. Expertise in Synopsys Design Compiler for synthesis and formal verification. Strong working knowledge of timing closure processes. Experience with post-silicon bring-up and debugging. Familiarity with SoC integration challenges. Knowledge of design verification aspects is essential. Experience from SoC specification to GDS and commercialization is highly desired. Ability to make timely and effective decisions, even with incomplete information. Demonstrated expertise in specific technical areas, with significant experience in related fields. Provide direction, mentoring, and leadership to small to medium-sized teams. Strong communication and leadership skills are necessary for effective collaboration with program stakeholders. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

Senior Staff Physical Design Engineer Greater Bangalore -Hybrid/Hyderabad (Hybrid ) PrincipalPhysical Design Engineer Company Background Introducing The Information’s 50 Most Promising Startups for 2024 We are a well-funded, stealth-mode startup based in Mountain View, CA, founded by senior technical and business executives hailing from category leaders in infrastructure semiconductors and hyperscale cloud services, and backed by top-tier investors with an immensely successful formula & track record on early-stage investments. We are a diverse team of expert chip/software/systems architects and developers who excel in hardware/software solution co-design. Our team has built, and delivered into production, technologies that process over half of the world's global data center traffic. Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, from CAD tool flow setup, early floorplan exploration in conjunction with microarchitecture development, through block partitioning, power planning, clock network design and construction, through P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout. Roles and Responsibilities Build and support the CAD tool flow for physical implementation in a cloud-first development environment. Work with architects and microarchitects on the chip-level floorplan and block partitioning. Evaluate tradeoffs in functional partitioning, block size, and interface complexity with other stakeholders. Define and construct the major physical structures, including the clock and reset architecture, the power delivery network, and interconnect topologies. Execute on block-level, cluster-level, and top-level physical implementation, from synthesis, floorplan and power plan, through P+R, through timing closure, physical verification, and tapeout. Interface with foundry and library partners on 3rd party IP and process technology issues, including updates to device models, IP integration requirements, and pre-tapeout signoff. Skills/Qualifications : Proven industry experience and successful track record in the physical implementation of large, high-performance network switching/routing fabrics (Ethernet, Infiniband, HPC), Network Interface Controllers, Smart-NICs, CPUs, or GPUs in the latest silicon process nodes. Deep experience with the latest CAD tools through the entire physical design workflow, e.g., Cadence Genus and Innovus, Synopsys ICC2/FusionCompiler, Tempus, PrimeTime SI, PrimeTime PX, StarRC, ICV, Calibre. Strong familiarity with various analysis tools such as Redhawk, Voltus. Experience with circuit analysis using HSPICE is a plus. Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages. Minimum BSEE/CE + 10years or MSEE/CE + 8 years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

Senior Staff Physical Design Engineer Greater Bangalore -Hybrid/Hyderabad (Hybrid ) PrincipalPhysical Design Engineer Company Background Introducing The Information’s 50 Most Promising Startups for 2024 We are a well-funded, stealth-mode startup based in Mountain View, CA, founded by senior technical and business executives hailing from category leaders in infrastructure semiconductors and hyperscale cloud services, and backed by top-tier investors with an immensely successful formula & track record on early-stage investments. We are a diverse team of expert chip/software/systems architects and developers who excel in hardware/software solution co-design. Our team has built, and delivered into production, technologies that process over half of the world's global data center traffic. Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, from CAD tool flow setup, early floorplan exploration in conjunction with microarchitecture development, through block partitioning, power planning, clock network design and construction, through P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout. Roles and Responsibilities Build and support the CAD tool flow for physical implementation in a cloud-first development environment. Work with architects and microarchitects on the chip-level floorplan and block partitioning. Evaluate tradeoffs in functional partitioning, block size, and interface complexity with other stakeholders. Define and construct the major physical structures, including the clock and reset architecture, the power delivery network, and interconnect topologies. Execute on block-level, cluster-level, and top-level physical implementation, from synthesis, floorplan and power plan, through P+R, through timing closure, physical verification, and tapeout. Interface with foundry and library partners on 3rd party IP and process technology issues, including updates to device models, IP integration requirements, and pre-tapeout signoff. Skills/Qualifications : Proven industry experience and successful track record in the physical implementation of large, high-performance network switching/routing fabrics (Ethernet, Infiniband, HPC), Network Interface Controllers, Smart-NICs, CPUs, or GPUs in the latest silicon process nodes. Deep experience with the latest CAD tools through the entire physical design workflow, e.g., Cadence Genus and Innovus, Synopsys ICC2/FusionCompiler, Tempus, PrimeTime SI, PrimeTime PX, StarRC, ICV, Calibre. Strong familiarity with various analysis tools such as Redhawk, Voltus. Experience with circuit analysis using HSPICE is a plus. Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages. Minimum BSEE/CE + 12 years or MSEE/CE + 10 years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

ASIC/SOC Front End Design Engineer Job description: 1. Setup ASIC QA flows for RTL design quality checks. 2. Understand the design: top level interfaces, clock structure, reset structure, RAMs, CDC boundaries, power domains. 3. Running Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, CLP steps. 4. Come up with clock constraints, false paths, multi-cycle paths, IO delays, exceptions and waivers. 5. Checking the flow errors, design errors & violations and reviewing the reports. 6. Debugging CDC, RDC issues and come up with the RTL fixes. 7. Supporting DFX team for DFX controller integration, Scan insertion, MBIST insertion and DFT DRC & MBIST checks. 8. Handling multiple PNR blocks, building wrappers and propagating constraints, waivers, etc. 9. Flows or Design porting to different technology libraries. 10. Generating RAMs based on targeted memory compilers and integrating with the RTL. 11. Running functional verification simulations as needed. Job Requirements: 1. B.E/M.E/M.Tech or B.S/M.S in EE/CE with 3 to 5 years of relevant experience 2. ASIC design flow and direct experience with ASIC design in sub-20nm technology nodes 3. Modern SOC tools including Spyglass, Synopsys design compiler & primetime, Questa CDC, Cadence Conformal, VCS simulation 4. Experience in signoff of front end quality checks & metrics for various milestones of the project 5. TCL, Perl, Python scripting Experience: 3 to 5 years Location: Hyderabad Notice Period: Immediate Show more Show less

Role Description Role Proficiency: Ability to e xecute any small to mid size customer project in any field of VLSI Frontend Backend or Analog design with minimal supervision Outcomes Work as an individual contributor to own any one task of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc. Independently analyze and complete the assigned task in the defined domain(s) successfully and on-time On time quality delivery approved by the project lead/manager Measures Of Outcomes Quality –verified using relevant metrics by Lead/Manager Timely delivery - verified using relevant metrics by Lead/Manager Reduction in cycle time and cost using innovative approaches Number of trainings attended Number of new projects handled Outputs Expected Quality of the deliverables: Ensure clean delivery of the design and module in-terms of ease in integration at the top level Meet functional spec / design guidelines 100% of the time without any deviation or limitation Documentation of the tasks and work performed Timely Delivery Meeting project timelines as requested by the program manager Support the team lead in intermediate tasks delivery Team Work Participation in team work; supporting team members/lead at the time of need Able to perform additional tasks in-case any team member(s) is not available Innovation & Creativity Automate repeated tasks to save design cycle time as a necessary approach Participation in technical discussion training forum Skill Examples Languages and Programming skills:a. System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice (any one) EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (any one) Technical Knowledge: (any one)a. Partially implement IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb. Strong in Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec. Strong knowledge in Physical Design / Circuit Design / Analog Layout d. Strong understanding of Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verificatione. Strong knowledge of Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below Strong communication skills Good analytical reasoning and problem-solving skills with attention to details Able to deliver the tasks on-time per quality guidelines and GANTT in every instance. Required technical skills and prior design knowledge to execute the assigned tasks Ability to learn new skills in-case required technical skills are not present to a level needed to execute the project Knowledge Examples Frontend / Backend / Analog Design:a. Project experience in any of the design by executing any one of – RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc.b. Strong understanding of the design flow and methodologies used in designing Understanding of the technical specs and assigned tasks: Understand the assigned tasks and have strong knowledge to execute the project tasks assigned by the client / manager as per shown skill Additional Comments Experience- 4+yrs Analog Layout Candidate should work independently on block level and chip level Analog layout design, coordinating with the circuit designer & the project lead. Candidate should have minimum 3+ years of hands-on experience in Analog layout. Custom layout experience in DAC, ADC, Band gap, Regulators, LDOs etc. Knowledge of finfet or technology exposure to 28nm or below is an added advantage. Full Understanding of IC fabrication and reliability issues. Full familiarity with Cadence-Virtuoso, PVS, ASSURA and Calibre tools. Outstanding written and verbal communication skills. Skills Analog Layout,Finfet,Cadence Virtuoso Show more Show less

Alternate Job Titles: Analog Design Staff Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned Analog Design Staff Engineer with a passion for innovation and a forward-looking approach to design. With over a decade of experience in the industry, you bring a wealth of knowledge in full custom analog/mixed-signal circuit design, circuit simulations, custom layout, and post-silicon characterization. Your expertise extends to advanced process challenges, including ESD and Reliability, and you are well-versed in the architecture, design, and verification of PVT sensors, Oscillators, Bandgap, PLLs, LDOs, ADCs, Amplifiers, PHYs, and other Mixed-signal blocks. You excel in leading teams, managing projects, and providing innovative solutions to meet project deadlines. Your exceptional communication, mentoring, and interpersonal skills enable you to collaborate effectively with both internal teams and external customers. You are proficient with circuit design and simulation tools from various EDA vendors and have hands-on experience with Custom Compiler or equivalent schematic and layout editor tools. Your technical expertise in the productization of advanced technologies sets you apart as a high-caliber individual in the field of analog design. What You’ll Be Doing: Developing new solutions in the field of on-die monitoring Liaising with the layout team to achieve the best possible engineering solutions Deploying new sensors into test chips and conducting post-silicon characterization Guiding junior engineers and tracking their work Conceptualizing, designing, and productizing state-of-the-art analog sensors Engaging in full custom analog/mixed-signal circuit design, simulations, and custom layout The Impact You Will Have: Driving innovation in on-die monitoring solutions Ensuring the highest quality engineering solutions through close collaboration with the layout team Advancing the deployment and characterization of new sensor technologies Mentoring and developing the next generation of engineers Contributing to the design and productization of cutting-edge analog sensors Enhancing the overall performance and reliability of our products What You’ll Need: B.Tech. or M.Tech. degree in Electrical Engineering with 10+ years of relevant industry experience or a Ph.D. with relevant experience Strong technical experience in custom Analog/AMS design techniques, implementation, and verification Knowledge of full custom layout techniques Experience with circuit design and simulation tools, IC design CAD packages from any EDA vendor Understanding of SPICE simulator concepts and simulation methods Who You Are: You possess a design-oriented and forward-looking thought process, capable of leading teams and managing projects independently. You are adept at providing innovative solutions and working towards meeting project deadlines. Your expertise in custom Analog/AMS design techniques, implementation, and verification is complemented by your excellent teamwork, communication, mentoring, and interpersonal skills. The Team You’ll Be A Part Of: You will be part of the PVT sensor group, a dynamic team focused on the design and implementation of state-of-the-art analog sensors. This team works collaboratively to develop new solutions in the field of on-die monitoring and deploy these solutions into test chips for post-silicon characterization. Your role will involve close collaboration with the layout team and guiding junior engineers to achieve the best possible engineering outcomes. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and highly motivated individual with a passion for technology and innovation. You have a strong technical background in RTL, Physical Design, and post-silicon test and testability development. Your expertise in debugging and developing Process, Voltage, Temperature, Current, and Droop sensors is unparalleled. You thrive in a dynamic environment and excel in communication, teamwork, and leadership. You are eager to learn and contribute to the development of state-of-the-art PVT IP sensors that are integral to the silicon lifecycle monitoring process. You possess a mindset geared towards meticulous IP debug and documentation, ensuring the highest standards of product development and performance. What You’ll Be Doing: Serving as the single point of contact for post-silicon debug activities. Enabling Product Requirement Documents (PRDs). Working to enable IP as a product development platform. Handling hands-on post-silicon test setups. Collaborating on top-level physical design, board-level, and package-level designs. Developing post-silicon reports and conducting debug analysis. The Impact You Will Have: Driving the successful development and deployment of PVT IP sensors. Enhancing the reliability and performance of Synopsys' silicon lifecycle monitoring solutions. Ensuring high-quality product development through meticulous testing and debugging. Contributing to the continuous innovation in chip design and software security. Supporting Synopsys' leadership in the market for PVT IP developments. Empowering the creation of high-performance silicon chips used in various advanced technologies. What You’ll Need: Hands-on experience in post-silicon test setups. Sound knowledge of Digital/AMS chip design and post-silicon debug. BS or MS degree in Electrical Engineering with 3+ years of experience. Understanding of top-level physical design, board-level, and package-level designs. Expertise in RTL development and physical design. Who You Are: Strong communicator with excellent teamwork and interpersonal skills. Detail-oriented with a mindset geared towards IP debug and documentation. Proactive learner with the ability to adapt to new IP functionalities. Effective leader with strong people management skills. Highly motivated and capable of mentoring both internal teams and external customers. The Team You’ll Be A Part Of: You will be part of the rapidly expanding PVT IP group at Synopsys, focusing on the development of cutting-edge PVT IP sensors. This team is dedicated to conceptualizing, designing, and productizing state-of-the-art sensors that play a critical role in the silicon lifecycle monitoring process. Collaborate with a group of innovative and highly skilled professionals to drive the future of technology. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Alternate Job Titles: DFT Solutions Engineer Design for Test Engineer DFT Project Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: An experienced Solutions Engineer with a proven track record in project execution and overall project management within the semiconductor industry. You excel in deploying Synopsys DFT technologies on customer designs, ensuring projects are completed on schedule and with high quality. You are adept at managing multiple projects simultaneously, recognizing and mitigating risks, and working proactively on contingency plans. You possess exceptional verbal and written communication skills, leadership abilities, and a strong teamwork ethic. Your proficiency in PowerPoint, Excel, and Word, along with your ability to work unsupervised, makes you a valuable asset to any team. You have a solid background in the implementation of DFT technologies and are eager to work cross-functionally with internal teams, gaining exposure and visibility on a global scale throughout the organization. What You’ll Be Doing: Deploying Synopsys DFT technologies on key customers’ designs and successfully executing the project. Acting as the focal point of contact and managing all external and internal communications across cross-functional teams. Planning and directing project schedules, identifying and escalating issues, and driving problems to resolution. Identifying and managing risks, ensuring the completion of projects on schedule and with high quality. Organizing interdepartmental activities and ensuring clear and concise communication. Working closely with internal teams (Applications Engineering, R&D) to meet customer requirements and achieve goals and targets. The Impact You Will Have: Ensure successful deployment of Synopsys DFT technologies on customer designs. Facilitate effective communication and coordination between cross-functional teams. Drive projects to completion, meeting deadlines and maintaining high standards of quality. Identify and mitigate risks to ensure project success. Contribute to the overall success of Synopsys by delivering high-quality solutions that meet customer needs. Enhance customer satisfaction and build strong, long-lasting relationships with key customers. What You’ll Need: Solid background and proven track record in the implementation of DFT technologies. Experience in deploying Scan Compression, On-chip DFT Fabric, ATPG, Diagnosis, MemoryBIST, LogicBIST, and Boundary Scan. Proficiency in project management and the ability to manage multiple projects simultaneously. Exceptional verbal/written communication, leadership, interpersonal, and teamwork skills. Good working knowledge of PowerPoint, Excel, and Word. Who You Are: A detail-oriented and process-driven professional with a strong engineering background. You possess excellent organizational skills and the ability to communicate effectively across various levels of the organization. You are a proactive problem-solver who can work independently and within a team. Your leadership abilities and teamwork ethic enable you to drive projects to successful completion, ensuring high-quality outcomes and customer satisfaction. The Team You’ll Be A Part Of: You will be part of a dynamic and innovative team that focuses on deploying Synopsys DFT technologies to key customer designs. This team works cross-functionally with internal teams such as Applications Engineering and R&D, and has a global presence within the organization. Together, you will strive to meet customer requirements and achieve project goals, contributing to the overall success of Synopsys. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: As a seasoned Software Engineering, Staff Engineer, you thrive in fast-paced environments and have a proven track record of delivering high-quality results. You are proficient in both front-end and back-end development, with extensive experience in various programming languages and frameworks. Your expertise in Linux platform and familiarity with common stacks enables you to build scalable and efficient systems. You possess a deep understanding of CI/CD tools and have hands-on experience with automation scripts, enhancing testing efficiency and coverage. Your ability to analyze complex technical problems and implement effective solutions makes you a valuable asset to any team. You are committed to iterative development, continuous integration, and delivery, ensuring that projects are completed successfully. With a Masters or Bachelor’s degree in computer science or a related field, and over seven years of experience as a Software Engineer, you are ready to take on new challenges and drive innovation at Synopsys. What You’ll Be Doing: Follow design principles of software engineering and systems to build features that improve platform and tools' availability, scalability, latency, and efficiency. Design and maintain test frameworks, including various tools to empower developers to automate test cases effectively. Develop, update, and manage automation scripts for various Infrastructure and application test case scenarios to enhance testing efficiency and coverage. Evaluate design approaches and tools, build frameworks, and improve existing systems. Set up CI/CD tools as part of the engineering efforts. Collaborate with cross-functional teams to drive productivity, robustness, agility, and time-to-market advantage in the creation of Synopsys products and solutions. The Impact You Will Have: Enhance the availability, scalability, latency, and efficiency of Synopsys platforms and tools. Empower developers with effective automation tools, improving testing efficiency and coverage. Drive significant productivity and robustness in the creation of Synopsys products and solutions. Lead corporate infrastructure transformation and IT operations leadership. Invest in the next wave of disruptive technologies to maintain Synopsys' competitive edge. Contribute to the growth and scaling strategy of Synopsys through innovative solutions. What You’ll Need: Ability to work in a high-performing team and balance high-quality delivery with customer focus to meet business needs. Prior experience as a Full Stack Developer or similar role. Experience working on Linux platform and familiarity with common stacks. Knowledge of multiple front-end languages and libraries (e.g., HTML/CSS, JavaScript, XML, jQuery). Knowledge of multiple back-end languages (e.g., .NET, Java, Python, Ruby) and JavaScript frameworks (e.g., React, Node.js). Familiarity with databases (e.g., MySQL, MongoDB), web servers (e.g., Apache), and UI/UX design principles. Experience working in an Agile development environment, with a commitment to iterative development, continuous integration, and delivery. Experience with build systems, CI/CD tools (like AWS DevOps, Jenkins), application analytics/monitoring. Experience with Artifactory, package managers including yum, rpm, and apt. Ability to analyze complex technical problems, troubleshoot issues, and implement effective solutions in a timely manner. Takes pride in working on projects to successful completion involving a wide variety of technologies and systems. Masters/Bachelor’s degree in computer science or related field of study and 7+ years of experience as a Software Engineer. Who You Are: Innovative thinker who is always looking for ways to improve systems and processes. Detail-oriented and committed to delivering high-quality results. Excellent communicator with the ability to collaborate effectively with cross-functional teams. Proactive problem solver who can troubleshoot and resolve issues efficiently. Adaptable and able to thrive in a fast-paced, dynamic environment. Passionate about technology and continuous learning. The Team You’ll Be A Part Of: The Engineering Excellence Group drives innovation velocity and enterprise infrastructure automation, which are critical elements of our growth and scaling strategy. This team is chartered to drive significant productivity, robustness, agility, and time-to-market advantage in the creation of Synopsys products and solutions. The group also leads corporate infrastructure transformation as we continue to drive IT operations leadership and invest in the next wave of disruptive technologies. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SMTS SILICON DESIGN ENGINEER The Role The position will involve working with a very experienced CPU physical design team. The person is responsible for delivering the physical design of critical CPU units to meet challenging goals for frequency, power, and other design requirements for AMD's next-generation processors in a fast-paced environment with cutting-edge technology. The Person Engineer with a good attitude, strong analytical skills, effective communication, and excellent problem-solving abilities. Key Responsibilities Own critical CPU units and drive to convergence from RTL-to-GDSII - synthesis, floor-planning, place and route, timing closure, and signoff Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoffs for design closure. Develop and improve physical design methodologies and customize recipes across various implementation steps to optimize PPA. Implement floor plan, synthesis, placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), EM/IR and signoff. Handling different PNR tools - Synopsys fusion compiler, Cadence, PrimeTime, StarRC, Calibre, Apache Redhawk Preferred Experience 12+ years of professional experience in physical design, preferably with high-performance designs. Must have closed high-performance IPs- CPU/GPU/DPU/memory controller, etc. Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality; familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow - Perl/Tcl/Python Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in advanced sub 7nm nodes Excellent physical design and timing background. A good understanding of computer architecture is preferred. Strong analytical/problem-solving skills and pronounced attention to detail. Academic Credentials Qualification: Bachelors or Masters in Electronics/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled and experienced Analog Design Engineer with a strong background in SerDes/High-Speed analog design. With a technical degree in Electrical Engineering or a related field, you possess a deep understanding of transistor-level circuit design and CMOS fundamentals. Your experience spans across various analog and mixed-signal building blocks, including equalizers, data samplers, voltage/current-mode drivers, serializers, LDOs, Bandgap, ADC/DAC, PLLs, and DLLs. You are adept at identifying and refining circuit implementations to achieve optimal power, area, and performance targets. Your ability to propose efficient design and verification strategies, coupled with your expertise in overseeing physical layout and minimizing parasitic effects, sets you apart. You thrive in collaborative environments, presenting simulation data for peer reviews and documenting design features and test plans meticulously. Your silicon-proven experience and consultative approach to electrical characterization within SerDes IP products make you an invaluable asset to our team. What You’ll Be Doing: Ensure analog sub-block performance adheres to SerDes standards and architecture document specifications. Identify and refine circuit implementations to achieve optimal power, area, and performance targets. Propose design and verification strategies that efficiently use simulator features to ensure highest quality design. Oversee physical layout to minimize the effect of parasitic, device stress, and process variation. Present simulation data for peer review. Ownership of analog and mixed-signal building block that is integrated as part of a larger SerDes design. Document design features and test plans. Consult on the electrical characterization of your circuit within the SerDes IP product. The Impact You Will Have: Contribute to the development of cutting-edge SerDes technologies that drive high-performance computing and communication systems. Enhance the overall performance and efficiency of our analog and mixed-signal designs, ensuring they meet industry standards. Improve the quality and reliability of our designs through meticulous verification and layout oversight. Support the seamless integration of analog and mixed-signal building blocks within larger SerDes designs. Drive innovation by identifying and implementing optimal circuit solutions for complex design challenges. Collaborate with cross-functional teams to deliver high-quality IP products that meet customer requirements. What You’ll Need: BTech or MS with 2+ years of SerDes/High-Speed analog design experience. Familiarity with transistor-level circuit design of fundamental analog and mixed-signal building blocks. Sound CMOS design fundamentals. Design experience with some of the following SerDes sub-circuits: equalizers, data samplers, voltage/current-mode drivers, serializers, LDOs, Bandgap, ADC/DAC, PLLs, DLLs. Who You Are: Detail-oriented and meticulous in your approach to design and verification. A strong communicator, able to present complex technical data clearly and concisely. Collaborative and team-oriented, thriving in a peer-review environment. Innovative and solution-focused, always seeking to optimize design performance. Proactive and self-motivated, with a passion for continuous learning and improvement. The Team You’ll Be A Part Of: Our team is dedicated to developing high-performance SerDes IP products that are integral to modern communication systems. We are a collaborative group of engineers who value innovation, quality, and continuous improvement. Together, we tackle complex design challenges, ensuring our solutions meet the highest industry standards and exceed customer expectations. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

You Are: You are a seasoned digital verification engineer with a passion for innovation and problem-solving. With a BE/B.Tech degree in electronics or a related engineering field, you bring 3-5 years of hands-on experience in digital verification. Your proficiency in system verilog, UVM, coupled with a strong understanding of formal verification techniques, sets you apart. You thrive in UNIX/Linux OS environment and have a keen interest in exploring new technologies. Your ability to build UVM based testbenches , along with your prior knowledge of EDA tools and simulators, makes you an ideal candidate. Excellent English communication skills and the ability to compile verification plans and strategies are essential for this role. What You’ll Be Doing: Creation of test plans Development of testbenches Creation of tests – both directed and random Functional coverage modelling and review, Code coverage review Debugging and resolving mismatches between design and C-model Integration of third party and internal verification IP Review and improvement of verification test suites and testbench Mentor junior team members Creation of Test plan, test strategy Coverage databases (Fully traceable from test plan and specification) The Impact You Will Have: Driving innovation in processor verification techniques Enhancing the efficiency and effectiveness of our verification mechanisms Contributing to the development of cutting-edge technology that sets Synopsys apart in the industry Ensuring high-quality IP delivery through rigorous verification Supporting the continuous improvement of our hardware verification processes What You’ll Need: Bachelor’s degree in engineering from a reputed college Minimum 3+ years of relevant experience Microprocessor verification experience is an advantage Hands-on experience with SystemVerilog and Verilog Proficiency with Verification methodologies: UVM/OVM Programming skills: C, assembly, Perl, makefile generation Experience with latest verification techniques like formal, low-power, safety etc. is an added advantage Who You Are: Innovative thinker with a passion for technology Excellent communicator and collaborator Detail-oriented and highly organized Adept at problem-solving and critical thinking Proactive and self-motivated The Team You’ll Be A Part Of: You will be part of a dynamic and innovative team focused on developing and verifying ARC processor IPs. Our team values collaboration, creativity, and continuous improvement, and we are dedicated to pushing the boundaries of technology to deliver exceptional products. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a motivated and skilled engineer with 3-7 years of experience in emulation solutions development. You bring a strong foundation in programming concepts using C/C++ and an understanding of digital design. Your expertise includes HDL languages such as System Verilog and Verilog, and you are familiar with protocols like AXI, AMBA, JTAG, AVB, CAN, and TSN. You thrive in collaborative environments and have excellent communication skills. Your educational background includes a B.E, B.Tech, or M.Tech in Electronic & Communication or Computer Science Engineering. You are passionate about developing cutting-edge emulation solutions for semiconductor customers and are eager to engage in both software development and synthesizable RTL development. What You’ll Be Doing: Developing emulation solutions for industry-standard protocols such as AXI, AMBA, JTAG, AVB, CAN, and TSN. Engaging in software development using C/C++ and synthesizable RTL development using Verilog. Verifying emulation solutions to ensure they meet the highest standards of quality and performance. Interacting with customers during the deployment and debugging phases to provide technical support and ensure successful implementation. Collaborating with cross-functional teams to integrate emulation solutions with other Synopsys products and technologies. Continuously improving and optimizing emulation solutions to meet evolving industry needs and standards. The Impact You Will Have: Enhancing the efficiency and performance of semiconductor design processes through advanced emulation solutions. Contributing to the development of high-performance silicon chips and software content that drive technological innovation. Supporting semiconductor customers in overcoming design and verification challenges, leading to successful product launches. Improving the reliability and functionality of emulation solutions, thereby increasing customer satisfaction and trust in Synopsys products. Driving continuous improvement and innovation within the emulation solutions domain. Facilitating seamless integration of emulation solutions with other Synopsys technologies, enhancing overall product offerings. What You’ll Need: Strong programming skills in C/C++ and understanding of OOPS concepts. Good understanding of digital design concepts. Knowledge of HDL languages such as System Verilog and Verilog. Experience with scripting languages like Perl or TCL is a plus. Understanding of ARM architecture is an added advantage. Knowledge of UVM and functional verification will be a plus. Who You Are: A team player with excellent communication skills. Detail-oriented and capable of working independently. Adaptable and eager to learn new technologies and methodologies. Proactive in identifying and solving problems. Passionate about delivering high-quality solutions. The Team You’ll Be A Part Of: You will be part of a dynamic and innovative team focused on developing state-of-the-art emulation solutions for semiconductor customers. The team collaborates closely with other engineering groups within Synopsys to ensure seamless integration and optimal performance of our products. We value creativity, continuous learning, and a commitment to excellence. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

We're looking for an Experienced RTL Design Engineer to join our Automotive Digital Interface Controller IP team. The Automotive Digital Design Engineer is expected to : Be responsible for specification development, architecture design and RTL development of Automotive specific features / enhancements. Proactively develop safety mechanisms that can be embedded within our IP and reused easily Work closely with the verification team and review verification plan mapping with the specification. Work with product teams to evaluate customer requirements related to quality, functional safety, and automotive reliability. Work closely with the Functional Safety and internal development teams on projects and task planning, progress tracking and reporting. Key Qualifications Must have BSEE in EE with 5+ years of relevant experience or MSEE with 4+ years of relevant experience. Must have proven experience working on Automotive SoC’s / Digital IP’s. Must have proven experience working of one or more of protocols at the IP level: DDR / PCIe / UCIe. Hands on experience with architecting / micro-architecture / detailed design from functional specifications. Hands on experience with Synthesizable Verilog/ System Verilog RTL coding for ASIC designs and Simulation tools. Lint, CDC, synthesis flow and static timing flows, formal checking, etc experience. Working knowledge / experience TCL, Perl, Python is added advantage. Has a solid desire to learn and explore new technologies. Performs in project leadership role & guides more junior peers with aspects of their job. Frequently networks with senior internal and external personnel in own area of expertise. Proficient in English. Formal training in ISO 26262 is preferred. Experience in qualifying systems with embedded hardware to various ISO 26262 ASIL levels up to ASIL D Experience with various ISO 26262 work products such as DFMEA; FMEDA; DFA Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability. Show more Show less