You will be responsible for PMIC (Power Management IC) Characterization in locations such as Bangalore, Hyderabad, and Noida. Your role will involve having a good knowledge of PMIC hardware validation engineering. It is essential to have a strong understanding of NPU Architecture, with preference given to Broadcom and experience with Qumran/Jericho family. Expertise in Labview is considered a plus for this position. Additionally, you should possess a good understanding of Switching and Linear Voltage Regulators. The ideal candidate for this role should have 2 to 7 years of relevant experience. A BTECH/MTECH degree in Electrical/Electronics/Computer Science Engineering or an equivalent qualification is required to qualify for this position.,
You are a Physical Design Engineer with 2-5 years of hands-on experience in different PnR steps including Floor planning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation, and DRC closure. You should be well versed with high frequency design & advanced tech node implementation, in-depth understanding of PG-Grid optimization, custom clock tree design, and tackling high placement density/congestion bottlenecks. Your expertise should include identifying high vs low current density paths, layer/via optimization, and Adaptive PDN experience. You must have knowledge of custom clock tree designs such as H-tree, SPINE, Multi-point CTS, Clock metrics optimization through tuning of CTS implementation. Familiarity with PnR tool knobs/recipes for PPA optimization is essential. Experience in automation using Perl/Python and tcl is required. Good communication skills are necessary as you will be working in a cross-site cross-functional team environment. The ideal candidate will have a BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or an equivalent field with a minimum of 3 years of relevant experience. This is a great opportunity to be part of a fast-paced team responsible for delivering high-performance designs for high performance SoCs in sub-10nm process for the mobile space.,
As a software engineer at Mirafra, you will be part of a fast-growing company with a global presence, specializing in Semiconductor design, Embedded systems, Digital and Application software. With over 1500 employees, we offer product engineering services to Fortune 500 companies. Our expertise ranges from ASIC design to end-to-end software development. You should have at least 4 years of experience in software development within an agile team setup, including collaboration with remote or distributed teams. Proficiency in React Native is essential, along with a strong background in full-stack mobile development encompassing technologies such as Javascript, React, and React Native. Knowledge of Native iOS and Android platforms is highly valued. Your responsibilities will include project management, ensuring successful project delivery from inception to deployment. You should possess the ability to debug native code, optimize mobile applications for performance, and exhibit strong communication skills to convey technical concepts effectively to diverse audiences. Additionally, a proven track record in team leadership and technical excellence is expected. To qualify for this role, you should hold a BE degree in Computer Science or Electronics. Mirafra has been recognized as the Best Company to Work for in 2016 and the Most Promising Design Services Provider in 2018 by siliconindia. We have also been listed among the Top 10 Admired Companies for cutting-edge software services in 2022 by DigiTech Insight. Our esteemed clientele includes leading companies in various industries such as Semiconductor, Internet, Aerospace, Networking, Insurance, Telecom, Medical devices, Smartphone OEM, Storage, and Consumer electronics. If you are seeking a challenging opportunity to work on innovative projects and contribute to technical excellence, Mirafra is the place for you.,
As an Analog Circuit Simulation specialist, you will be responsible for conducting simulations and characterizations of analog circuits, specifically focusing on blocks like SerDes Rx Tx. Your role will require a strong foundation and expertise in high-speed custom digital circuits. With a minimum of 2 years of experience in this field, you will play a key role in ensuring the performance and reliability of analog circuits. To excel in this position, you should hold a BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or a related field. Your educational background will provide you with the necessary knowledge and skills to contribute effectively to the simulation and characterization of analog circuits. Joining our team in Bangalore, Hyderabad, or Noida, you will have the opportunity to work on cutting-edge technologies and collaborate with a dynamic group of professionals. If you are passionate about analog circuit simulations and eager to apply your expertise in a challenging environment, we welcome you to apply for this exciting opportunity.,
As a Coex BT WLAN Test professional, you will be responsible for conducting functional testing of Bluetooth and WiFi in coexistence. Your primary domain will be Coex (BT-WiFi), and you should have a solid understanding of the testing procedures in this area. The ideal candidate for this position should have 2 to 4 years of relevant experience in the field. This role may require you to work in locations such as Bangalore, Hyderabad, Chennai, and Pune. Your expertise in testing the coexistence of Bluetooth and WiFi technologies will be crucial in ensuring the quality and performance of the products or services being tested. Your attention to detail and ability to identify and resolve issues related to BT+WiFi coexistence will be highly valued in this role.,
As an IO Layout specialist, you will be responsible for designing and verifying GPIO library layouts. Your expertise in floorplanning, placement, IO ring implementation, and IO bus design will be crucial in ensuring the efficient functioning of the layout. With at least 3 years of experience in the field, you will bring valuable insights and knowledge to the team. To excel in this role, you should hold a BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or a related field. Your educational background will provide you with the necessary foundation to tackle the challenges associated with IO layout design. Join us in Bangalore, Hyderabad, or Noida, and be a part of our dynamic team where your skills and experience will contribute to the success of our projects.,
You are a skilled SOC Verification engineer with over 3 years of experience in the field. Your expertise includes a strong knowledge of ARM architecture, CPU fundamentals, and Cache coherency. You are proficient in programming languages such as C/C++, assembly, and scripting languages. Additionally, you have a good understanding of low-power design and verification methodologies. In this role, you will be responsible for developing CDV UVM verification environments at the system level. You will verify CPU connectivity to IP blocks and develop SoC test plans and test cases. Tracking metrics, including code and functional coverage, will be an essential part of your responsibilities. To qualify for this position, you should hold a Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field. You must have a minimum of 3 years of experience in SoC ASIC/FPGA verification. Proficiency in SystemVerilog (SV) and Universal Verification Methodology (UVM) is required. Experience with simulation, emulation, and formal verification techniques is also necessary. Strong debugging and problem-solving skills will be beneficial in this role. This position is located in Noida, and the ideal candidate should possess a BTECH/MTECH degree in Electrical/Electronics/Computer Science Engineering or an equivalent field.,
You will be working as a DFT Engineer in Noida with the following responsibilities: Strong fundamental knowledge of DFT techniques including JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IJTAG, and MBIST/LBIST. Experience in Tessent based ATPG flow, GLS, and Post-silicon-debug. Proficient in Perl/Tcl/Python scripting for automation and efficiency. Demonstrate excellent analytical and problem-solving skills. Conduct Core and SOC level ATPG to ensure Automotive grade quality. Handle Hierarchical ATPG retargeting and Pattern release for application on ATE. Execute SOC and Core level Timing/Non-timing GLS. Support silicon bring-up, diagnosis, and physical failure analysis. Facilitate Emulation of Gate-level SCAN patterns for comprehensive testing. You should possess a minimum of 5 years of experience in a similar role and hold a BTECH/MTECH degree in Electrical/Electronics/Computer Science Engineering or an equivalent field.,
As a Fullstack Developer at Mirafra, you will be responsible for building modular and reusable components and libraries, contributing to RESTful APIs development using .Net framework, optimizing application performance, implementing automated testing, and staying updated on web application and programming language developments. You should be highly proficient in .NET, .NET Core, and C#, with expertise in Entity Framework and LINQ. A good understanding of Front End Javascript development, particularly Vue.js or React.js, HTML, JS, JQuery, and CSS is essential. Knowledge of MS SQL, SSIS, Solid principles, unit testing tools like NUnit, XUnit, mocking tools like moq, and experience in designing and consuming RESTful APIs using .Net are required. Additionally, familiarity with .NET microservices, Graphql APIs, Entity Framework, JQuery, server-side rendering, functional programming, and object-oriented programming paradigms is beneficial. You should be able to write efficient, secure, well-documented, and clean JavaScript code and have proficiency in modern development tools such as Git, Bitbucket, Jira, Confluence, etc. To excel in this role, you must possess excellent verbal, written, and communication skills, along with good problem-solving abilities. The position requires a minimum of 5+ years of experience and a BE degree in Computer Science or Electronics. Mirafra, a global product engineering services company, has received accolades such as being recognized as the Best Company to Work for in 2016 and the Most Promising Design Services Provider in 2018 by siliconindia. Moreover, it has been listed among the Top 10 Admired Companies in 2022 for cutting-edge software services by DigiTech Insight. Mirafra's clientele includes some of the world's largest companies in industries like Semiconductor, Internet, Aerospace, Networking, Insurance, Telecom, Medical Devices, Smartphone OEM, Storage, and Consumer Electronics.,
As an Analog Circuit Design professional, you will be responsible for working on high-speed circuits such as serializer, deserializer, Rx, Tx, PLL, ADC, etc. Your expertise in VLSI fundamentals, circuit design, and digital systems will be crucial for deep submicron CMOS design based on FinFET technology. You should have a strong foundation in circuit analysis and clock/memory circuit design. With a minimum of 2 years of experience in Analog Circuit Design, you will be expected to leverage your skills in designing and optimizing analog circuits to meet the requirements of various projects. Your educational background should include a BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or a related field. This role will be based in Bangalore, Hyderabad, or Noida, where you will collaborate with cross-functional teams to deliver high-quality analog circuit designs that meet the specifications and standards set by the organization. Your ability to innovate, troubleshoot, and adapt to new technologies will be essential in this dynamic and challenging environment.,
As an RTL Design Engineer, you will be responsible for demonstrating strong design fundamentals with hands-on experience in front-end design flows. Your role will involve designing micro-architecture blocks, RTL coding, and conducting block-level verification. Additionally, you will be expected to perform tasks such as Linting, CDC analysis of reports, and identifying ways to fix violations. You should have hands-on experience in SoC/IP integration and possess an excellent understanding of SoC components such as processors, memories, peripherals, and IOs. It is essential to have a good grasp of at least one protocol like UFS, PCIe, SAS, SATA, or USB. Experience working with ARM or ARC processors/sub-systems is preferred. You will also be involved in UPF flow and updating constraints, requiring the ability to work independently, ramp-up quickly, and collaborate effectively with verification/validation teams for front-end flows. Proficiency in PERL/TCL scripting is necessary for this role. Moreover, strong verbal and written communication skills are essential for effective interaction with team members and stakeholders. The ideal candidate for this position should have 3 to 12 years of experience in the field and hold a BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or a related field.,
As a Test Automation Engineer at Mirafra, you will play a crucial role in ensuring the success of our software development projects. With a focus on Playwright, Cypress, API testing, and JMeter, you will be responsible for creating and maintaining automated test scripts for web, desktop, and mobile applications. Your expertise will be instrumental in integrating Playwright and Cypress with tools like JIRA and Jenkins, as well as in executing load/performance testing. Collaboration is key in our Agile development environment, and you will actively participate in sprint planning and retrospectives. Working closely with developers and the Testing team, you will contribute to the timely delivery of high-quality software applications. Your analytical skills will be put to use in analyzing and reporting test results to identify areas for improvement, ensuring continuous enhancement of our products. To excel in this role, you should bring 3 to 5 years of experience in automation testing using Playwright, Cypress, and JMeter for performance/load testing. Proficiency in scripting languages such as TypeScript and JavaScript, as well as programming languages like Java and Python, is essential. Familiarity with Agile methodologies, experience in designing automated test suites for various applications, and knowledge of setting up CI/CD pipelines using tools like Jenkins or Gitlab will be advantageous. A strong foundation in software testing principles, combined with hands-on experience in PTC Windchill, will set you apart as an ideal candidate for this position. With a Bachelor's degree in Computer Science or Electronics, you will join a dynamic team at Mirafra that has been recognized for its excellence in the industry. If you are looking to grow your career in automation testing and contribute to cutting-edge software services across industries such as Semiconductor, Internet, Aerospace, and more, Mirafra offers an exciting opportunity to be part of a fast-growing and innovative company. Join us in our mission to deliver top-quality solutions to Fortune 500 companies and be a part of our success story. Experience Required: 3+ years Education Qualification: BE in Computer Science/Electronics Achievements: - Best company to work for 2016 by siliconindia - Most Promising Design Services Provider 2018 by siliconindia - Top 10 Admired Companies 2022 for cutting-edge software services by DigiTech Insight,
As an Emulation Engineer, you will be responsible for creating emulation models from RTL/Netlist and mapping designs to Zebu/Palladium/Haps emulation platforms to enhance model performance. Your expertise in the Palladium flow and experience in migrating designs to Palladium will be crucial for success in this role. You should possess good knowledge of runtime and debug skills to effectively identify signals, take wave dumps on Palladium platforms, and analyze failures. In addition, exposure to ARM/ARC cores and their architectures, as well as familiarity with AMBA bus architectures like AXI/AHB/APB, will be valuable assets. Proficiency in bug tracking tools such as Jira and version control tools like Github, Bitbucket, and GIT is essential for efficient project management. Knowledge of Flash (NAND) and HDD (Hard disk) storage technologies is also desirable. Ideally, you should have 3 to 12 years of experience in emulation engineering and hold a BTECH/MTECH degree in Electrical/Electronics/Computer Science Engineering or an equivalent field. Understanding JTAG-based debuggers will further strengthen your candidacy for this role. If you are passionate about pushing the boundaries of emulation technology and possess the required skills and qualifications, we encourage you to apply for this exciting opportunity.,
As an FPGA Design Engineer, you will play a crucial role in designing and implementing FPGA solutions using Xilinx FPGA technology. Your responsibilities will include: - Having good experience with Xilinx FPGA and being well aware of RTL logic. - Demonstrating proficiency with Vivado tool and associated IP. - Understanding and applying LUT considerations in FPGA design. - Conducting FPGA simulation and testing using appropriate methods. - Utilizing FPGA debug techniques with Xilinx JTAG debugger. To qualify for this role, you should possess the following qualifications: - BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent. If you're passionate about FPGA design and have 3 to 12 years of experience in this field, we encourage you to apply for this exciting opportunity.,
Role Overview: You will be responsible for performing STA timing fixes, ECO, and Synthesis of complex SOCs at Subsystem level, Block level, and Chip level. Proficiency in tools such as Design compiler, Prime time, and Tempus is required for this role. Key Responsibilities: - Perform STA timing fixes for complex SOCs - Execute ECO (Engineering Change Order) tasks effectively - Conduct Synthesis activities at Subsystem, Block, and Chip levels - Utilize tools like Design compiler, Prime time, and Tempus to optimize timing Qualification Required: - B-TECH/M-TECH in Electrical/Electronics/Computer Science Engineering or Equivalent - Minimum of 3 years of experience in the field (Note: No additional details of the company are mentioned in the job description),
Role Overview: You will be responsible for PMIC (Power Management IC) Characterization in locations such as Bangalore, Hyderabad, and Noida. Your role will involve having a good knowledge of PMIC hardware validation engineering. It is essential to have a strong understanding of NPU Architecture, with preference given to Broadcom and experience with Qumran/Jericho family. Expertise in Labview is considered a plus for this position. Additionally, you should possess a good understanding of Switching and Linear Voltage Regulators. Key Responsibilities: - Characterize PMIC (Power Management IC) in various locations like Bangalore, Hyderabad, and Noida. - Demonstrate a strong understanding of PMIC hardware validation engineering. - Familiarity with NPU Architecture, especially Broadcom, and experience with Qumran/Jericho family. - Utilize expertise in Labview for enhanced performance. - Ensure a comprehensive understanding of Switching and Linear Voltage Regulators. Qualifications Required: - The ideal candidate should have 2 to 7 years of relevant experience. - A BTECH/MTECH degree in Electrical/Electronics/Computer Science Engineering or an equivalent qualification is necessary for this role.,
As an Analog Circuit Simulation Engineer, you will be responsible for: - Proficiently conducting analog circuit simulations and characterisation for blocks such as SerDes Rx Tx. - Demonstrating strong fundamentals and knowledge of high-speed custom digital circuits. Qualifications required for this role include: - A minimum of 2 years of experience in the field. - A degree in Electronics and Communication, Electrical Engineering, or a related field (BE/B-Tech/ME/M-Tech).,
Job Description: You will be responsible for designing and verifying GPIO library layouts. Your expertise in floorplanning, placement, IO ring implementation, and IO Bus design will be crucial for this role. Key Responsibilities: - Design and verify Layouts for GPIO library - Perform floorplanning and placement activities - Implement IO ring and IO Bus designs Qualifications Required: - BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or related field - Minimum 3+ years of experience in Layout design and verification of GPIO library,
As a Physical Design Engineer at our company, you will be part of a dynamic team responsible for delivering high-performance design flows for advanced SoCs in sub-10nm process technology for the mobile space. Your role will involve hands-on experience in various PnR steps such as Floor planning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation, and DRC closure. Additionally, you will be expected to: - Demonstrate expertise in high-frequency design and advanced tech node implementation - Utilize in-depth understanding of PG-Grid optimization for identifying high vs low current density paths, layer/via optimization, and Adaptive PDN experience - Possess comprehensive knowledge of custom clock tree design, including H-tree, SPINE, Multi-point CTS, and Clock metrics optimization - Address high placement density/congestion bottlenecks effectively - Apply expertise in PnR tool optimization for Power, Performance, and Area (PPA) enhancements - Utilize automation skills using Perl/Python and tcl for efficient design implementation - Exhibit strong communication skills and collaborate effectively in a cross-site cross-functional team environment Furthermore, the ideal candidate should hold a BTECH/MTECH degree in Electrical/Electronics/Computer Science Engineering or an equivalent field, with a minimum of 3 years of relevant experience.,
Role Overview: You will be responsible for implementing Design for Test (DFT) techniques to ensure the quality and reliability of semiconductor products. Your primary focus will be on areas such as JTAG, ATPG, logic diagnosis, Scan compression, and MBIST/LBIST. Additionally, you will be involved in Tessent based ATPG flow, GLS, and Post-silicon-debug. Your expertise in Perl/Tcl/Python scripting will be crucial for this role. Key Responsibilities: - Utilize your strong fundamental knowledge of DFT techniques to perform Core and SOC level ATPG, ensuring Automotive grade quality. - Engage in hierarchical ATPG retargeting and Pattern release for application on ATE. - Conduct SOC and Core level Timing/Non-timing GLS to optimize performance. - Support silicon bring-up, diagnosis, and physical failure analysis. - Collaborate on the emulation of Gate level SCAN patterns for comprehensive testing. Qualification Required: - Bachelor's or Master's degree in Electrical, Electronics, Computer Science Engineering, or a related field. - Minimum of 5 years of experience in DFT engineering. - Proficiency in Perl, Tcl, and Python scripting languages. - Excellent analytical and problem-solving skills to address complex DFT challenges.,