DFT Engineers

Role Overview: You will be responsible for implementing Design for Test (DFT) techniques to ensure the quality and reliability of semiconductor products. Your primary focus will be on areas such as JTAG, ATPG, logic diagnosis, Scan compression, and MBIST/LBIST. Additionally, you will be involved in Tessent based ATPG flow, GLS, and Post-silicon-debug. Your expertise in Perl/Tcl/Python scripting will be crucial for this role. Key Responsibilities: - Utilize your strong fundamental knowledge of DFT techniques to perform Core and SOC level ATPG, ensuring Automotive grade quality. - Engage in hierarchical ATPG retargeting and Pattern release for application on ATE. - Conduct SOC and Core level Timing/Non-timing GLS to optimize performance. - Support silicon bring-up, diagnosis, and physical failure analysis. - Collaborate on the emulation of Gate level SCAN patterns for comprehensive testing. Qualification Required: - Bachelor's or Master's degree in Electrical, Electronics, Computer Science Engineering, or a related field. - Minimum of 5 years of experience in DFT engineering. - Proficiency in Perl, Tcl, and Python scripting languages. - Excellent analytical and problem-solving skills to address complex DFT challenges.,