DFT Engineers

You are an experienced Design-for-Test (DFT) Engineer with over 5 years of hands-on expertise in DFT methodologies and implementation. You should possess a solid understanding of MBIST, Scan, ATPG, and simulation concepts, along with a proven track record of executing industry-standard DFT flows. Your key responsibilities will include performing MBIST insertion, Scan insertion, and ATPG pattern generation using industry-standard EDA tools. You will be conducting MBIST simulations and analyzing results using tools from Cadence, Siemens Tessent, or Synopsys. Additionally, you will execute zero delay and SDF-based timing simulations, and efficiently debug issues using simulators such as VCS, NCSim, or Xcelium in GUI mode. Working with fault models including Stuck-at Faults and Transition Delay Faults (TDF) will be part of your role. You will also be responsible for optimizing and improving scan test coverage using established DFT techniques. The required skills and experience for this position include 5+ years of relevant experience in DFT, hands-on expertise with tools from Cadence, Siemens Tessent, and Synopsys, proficiency in debugging and analysis using VCS, NCSim, or Xcelium, strong analytical and problem-solving skills, and good communication and collaboration skills. Preferred qualifications for this role include experience in DFT automation using scripting languages like TCL, Perl, or Python, and prior exposure to automotive, networking, or high-performance computing SoCs is considered a plus.,