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15.0 - 19.0 years
0 Lacs
karnataka
On-site
You are a highly skilled and experienced Full Chip RTL Design Architect with over 15 years of experience, seeking to join a dynamic team in Bangalore, Hyderabad, or Pune. Your role will involve a deep understanding of RTL design and SoC architecture, contributing to innovative semiconductor design solutions to drive successful chip-level RTL designs. **Key Responsibilities:** - **RTL Architecture and Design:** - Define and develop full chip architecture and RTL designs for complex SoCs. - Drive top-level integration of IPs and subsystems into full chip designs, ensuring design quality and efficiency. - Collaborate on micro-architectural specifications for seamless implementation. - **Design ...
Posted 2 weeks ago
5.0 - 9.0 years
0 Lacs
karnataka
On-site
As an ATE Test Engineer at our company, you will be responsible for developing, debugging, and optimizing ATE test programs for Advantest testers. Your role will be crucial in ensuring the reliability, efficiency, and quality of semiconductor testing processes. You will also support RMA analysis, maintain test methodologies, manage ATE testers, collaborate with cross-functional teams, and analyze test data. Key Responsibilities: - Develop, debug, and optimize ATE test programs for Advantest testers. - Support RMA analysis, identify root causes of failures, and implement corrective actions. - Maintain and enhance test methodologies to improve efficiency and yield. - Manage and operate ATE tes...
Posted 1 month ago
15.0 - 19.0 years
0 Lacs
karnataka
On-site
You are a highly skilled and experienced Full Chip RTL Design Architect sought by the company to join their dynamic team. Your role involves a deep understanding of RTL (Register-Transfer Level) design, SoC (System-on-Chip) architecture, and a passion for innovation in semiconductor design. You will be pivotal in defining and implementing full chip-level RTL designs to ensure successful execution. - Define and develop full chip architecture and RTL designs for complex SoCs. - Drive top-level integration of IPs and subsystems into full chip designs, ensuring design quality and efficiency. - Collaborate on micro-architectural specifications and ensure seamless implementation. - Develop and opt...
Posted 2 months ago
5.0 - 9.0 years
0 Lacs
karnataka
On-site
You are an experienced Design-for-Test (DFT) Engineer with over 5 years of hands-on expertise in DFT methodologies and implementation. You should possess a solid understanding of MBIST, Scan, ATPG, and simulation concepts, along with a proven track record of executing industry-standard DFT flows. Your key responsibilities will include performing MBIST insertion, Scan insertion, and ATPG pattern generation using industry-standard EDA tools. You will be conducting MBIST simulations and analyzing results using tools from Cadence, Siemens Tessent, or Synopsys. Additionally, you will execute zero delay and SDF-based timing simulations, and efficiently debug issues using simulators such as VCS, NC...
Posted 3 months ago
6.0 - 10.0 years
0 Lacs
pune, maharashtra
On-site
As a PHY Hardening Engineer at Ampere, you will play a pivotal role in the development of cutting-edge expertise in high-speed digital design. You will collaborate with various teams including architects, RTL designers, packaging and PCB design teams, and post-silicon validation groups to optimize layouts, ensure signal and power integrity, and perform chip-level physical design tasks. Your expertise in managing high-speed signals and advanced packaging techniques will be crucial in delivering reliable designs that meet timing, power, and manufacturability requirements. The ideal candidate for this role is a self-motivated individual with a Bachelor's degree and 8 years of related experience...
Posted 5 months ago
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