Principal Physical Design Engineer

As a PHY Hardening Engineer at Ampere, you will play a pivotal role in the development of cutting-edge expertise in high-speed digital design. You will collaborate with various teams including architects, RTL designers, packaging and PCB design teams, and post-silicon validation groups to optimize layouts, ensure signal and power integrity, and perform chip-level physical design tasks. Your expertise in managing high-speed signals and advanced packaging techniques will be crucial in delivering reliable designs that meet timing, power, and manufacturability requirements. The ideal candidate for this role is a self-motivated individual with a Bachelor's degree and 8 years of related experience or a Master's degree and 6 years of related experience. You should have a strong background in floor planning, bump planning, routing, power grid design, clock design/distribution, and optimization for high-speed digital circuits. Experience in developing high-speed digital layouts, handling chip assembly, and using EDA tools for chip-level physical verification is essential. Additionally, familiarity with signal and power integrity concepts, advanced packaging technologies, and DFT structures will be advantageous. In return, Ampere offers a comprehensive benefits package including premium medical, dental, and vision insurance, parental benefits, retirement plans, and generous paid time off. You will also enjoy fully catered lunches, healthy snacks, and energizing beverages in the office. At Ampere, we nurture an inclusive culture that encourages personal and professional growth, empowering employees to innovate and contribute to a more sustainable future through industry-leading cloud-native designs. Join us at Ampere and be part of our journey to invent the future of computing.,