179 Ddr Jobs

As a Senior Design/Verification - Subsystems Lead at Synopsys, you will be part of the Digital IP Subsystem team in Bangalore/Hyderabad, India, contributing to cutting-edge technological work in the field of integrated circuits. Your expertise will be crucial in driving the design and verification efforts for complex IP/Subsystem/SoC blocks. Design Lead: In the role of RTL Design Lead, you will be responsible for ensuring bug-free RTL from requirements or specifications. Your experience in multiple tape-outs and driving the design effort for complex blocks will be instrumental in the success of our projects. Verification Lead: As a Verification Lead, your role will involve catching bugs and ensuring that the design intent is met. Your expertise in leading multiple tape-outs and closing the verification of complex blocks will be essential in delivering high-quality results. For the Design role, we are looking for a Senior RTL Subsystems Designer Lead with a minimum of 8 years of experience. You should be able to drive the Subsystem life cycle from requirements to final release phases, work on defining micro-architectures, coding RTL with best practices, and collaborate with cross-functional teams to drive projects to completion. Key skills required for the Design role include proficiency with standard protocols such as PCIe, DDR, UFS, USB, AMBA, hands-on experience with low power design, understanding of DFT requirements and architecture, and the ability to work effectively with cross-functional teams. For the Verification role, we are seeking a Senior Verification Lead with a minimum of 8 years of experience. You should be able to drive the complete Verification cycle, including crafting test plans, architecting verification environments, developing test infrastructure, and driving closure with coverage. Key skills required for the Verification role include proficiency with Functional Verification of standard protocols such as PCIe, DDR, UFS, USB, AMBA, power-aware Verification with UPF, gate-level verification hands-on experience, and the ability to work effectively with cross-functional teams to drive projects to completion. If you are passionate about pushing the boundaries of technology and working on challenging projects in the SysMoore era, we invite you to join our dynamic team at Synopsys and contribute to the exciting world of integrated circuit design and verification.,

As a Senior/Lead/Sr. Lead Design Verification Engineer at our company located in Bangalore or Hyderabad, you will play a crucial role in ensuring the verification of high-speed interfaces such as DDR, PCIe, UCIe, or NVMe. You will need to have a Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field with a minimum of 4 years of hands-on experience in this domain. Your responsibilities will include utilizing your expertise in SystemVerilog and UVM to develop verification components like scoreboards, monitors, and sequencers. You will be required to have a strong understanding of digital design principles, verification methodologies, and simulation tools. Additionally, familiarity with protocol specifications and industry standards for DDR, PCIe, UCIe, or NVMe will be crucial for this role. Having experience with simulation tools such as VCS, ModelSim, or Questa will be an added advantage. You should also possess good debugging skills using tools like Waveform Viewers, Logic Analyzers, and protocol analyzers. Problem-solving skills, attention to detail, and the ability to work collaboratively are essential traits for this position. Preferred qualifications for this role include experience with formal verification techniques, knowledge of interface protocols like USB, Ethernet, or SATA, and proficiency in scripting languages like Python for automation purposes. Familiarity with FPGA-based verification platforms and hardware debugging tools will be beneficial in excelling in this role. If you are looking to join a dynamic team where you can leverage your skills in design verification and work on cutting-edge technologies, this position is ideal for you. Join us in our mission to push the boundaries of innovation and make a significant impact in the field of high-speed interface verification.,

You are in search of an experienced senior verification engineer with over 10 years of expertise in ASIC/SOC/IP/block level functional verification utilizing system verilog/UVM. The perfect candidate for this role should possess a comprehensive understanding of UVM, advanced UVM, and system verilog. Your main responsibilities will include developing a detailed test plan, constructing a complete test-bench, and creating a robust verification environment that comprises interface agents and scoreboard in UVM. Additionally, you should have in-depth knowledge of at least one industry-standard protocol such as Ethernet, PCIe, DDR, USB. Strong debugging skills are essential to promptly address test-bench issues and failures. As part of this role, you will be accountable for verification closure by focusing on coverage and managing bug reports. Proficiency in utilizing industry-standard verification tools like Questa, VCS, or ModelSim is required. Experience with scripting languages like python, perl, or TCL for automation tasks is also beneficial. Furthermore, you will be responsible for managing a team of 6 to 7 Engineers and engaging with customers to provide task updates. Experience in collaborating with Japanese customers is a prerequisite for this position. Proficiency in the Japanese language is a mandatory skill. If you meet these qualifications and are enthusiastic about taking on these responsibilities, we encourage you to apply for this challenging and rewarding role.,

As a Hardware-Assisted Verification Expert at Synopsys, you will play a crucial role in bridging and closing gaps between Emulation IP features and Design IP verification for both Controller and PHY functions. Your deep knowledge of IP interfaces like PCIe and DDR, coupled with experience in platforms such as Zebu, HAPS, and EP, will be essential in driving requirements for Emulation IP and ensuring its correct deployment in verification strategies. Your hands-on approach and collaborative mindset will drive innovation in defining requirements for IP product development in the context of emulation. Your responsibilities will include reporting metrics, driving improvements in Emulation IP, ensuring test plans deliver required function and quality, and staying ahead of evolving standards. You will enhance cross-functional collaboration, change the validation mindset in using Emulation IP for digital designs, and evolve best-in-class methodologies within the organization. Your impact will be felt in improving product quality, driving innovation, and standardizing workflows to increase efficiency and compliance. To excel in this role, you should have 10+ years of relevant experience, a results-driven mindset, exposure to advanced protocols like PCIe and DDR interfaces, and a proven track record in IP product development, particularly in emulation. Your excellent communication skills, adaptability, and comfort in a matrixed, international environment will be key in driving success in this position. Join us at Synopsys to transform the future through continuous technological innovation.,

You will be joining Eximietas as a Senior Design Verification Engineer/Lead in Bengaluru with 5-15 years of experience. Your primary responsibility will be to lead the SoC Design Verification efforts for complex projects, ensuring the successful execution of verification plans. This includes developing and implementing comprehensive verification strategies for high-speed and low-speed peripherals such as I2C, SPI, UART, GPIO, QSPI, as well as high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR, HBM. You will be conducting Gate-level simulations and power-aware verification using tools like Xprop and UPF. Collaboration with cross-functional teams, including architects, designers, and pre/post-silicon verification teams, will be crucial to ensure alignment and seamless integration of verification efforts. Your role will involve analyzing and implementing System Verilog assertions and functional coverage to ensure thorough verification of design functionality. Mentorship and technical guidance to junior verification engineers will be part of your responsibilities to elevate team performance. Leading and managing a dynamic team of verification engineers, fostering a collaborative and innovative work environment will be essential. You will also ensure that all verification signoff criteria are met, with clear and comprehensive documentation. Your dedication, work ethic, and commitment to meeting project goals and deadlines will be vital. Upholding quality standards and implementing best test practices to contribute to continuous improvements in verification methodologies will also be expected. You will work with verification tools from Synopsys and Cadence, including VCS and Xsim, and integrate third-party VIPs (Verification IP) to enhance verification coverage. To qualify for this role, you should have 5+ years of hands-on experience in SoC Design Verification and expertise in verification of high-speed SoCs and various protocols. Proficiency in System Verilog for verification, gate-level simulations, and power-aware verification using Xprop and UPF are necessary. Strong hands-on experience with VCS and Xsim from Synopsys and Cadence, mentorship experience, and demonstrated ability to work with cross-functional teams are also required. A strong understanding of verification methodologies and the ability to contribute to their continuous improvement are essential.,

As a Principal Software Engineer at Cadence, you will have the opportunity to work on cutting-edge technology in an environment that encourages creativity, innovation, and making a real impact. Cadence, a pivotal leader in electronic design, with over 30 years of computational software expertise, is seeking a candidate to join their highly talented team in Bangalore or Ahmedabad. In this role, you will be responsible for developing, implementing, and testing features for the next generation of verification IP tools. The ideal candidate should have excellent communication skills, the ability to quickly ramp up on new technologies independently, and a strong background in functional verification using SV/UVM. Additionally, hands-on knowledge of Python/Scripting, experience with memories such as HBM, LPDDRR, GDDR, and DDR, as well as prior VIP usage and development experience would be advantageous. Cadence offers an employee-friendly work environment that focuses on the physical and mental well-being of its employees, career development, learning opportunities, and celebrating success. The company's unique One Cadence - One Team culture promotes collaboration to ensure customer success, while providing avenues for learning and development based on individual interests and requirements. Qualifications for this role include a BE/BTech/ME/MS/MTech in Electrical/Electronics or equivalent, along with strong analytical and communication skills. The successful candidate should be self-motivated, possess strong written, verbal, and presentation skills, and have the ability to establish close working relationships with both customers and management. Creativity, the willingness to explore unconventional solutions, and the ability to work effectively across functions and geographies are essential behavioral skills required for this position. Join Cadence and be part of a diverse team of passionate individuals dedicated to making a difference in the world of technology. If you are ready to work in a supportive and friendly environment where innovation and collaboration are valued, we encourage you to apply for the Principal Software Engineer position by sending your CV to kmadhup@cadence.com. Regards, Madhu,

As a Senior Design/Verification - Subsystems Lead at Synopsys, you will be part of the Digital IP Subsystem team that has experienced significant growth. We are seeking talented engineers to join us in Bangalore/Hyderabad, India and be a part of our exciting journey in the SysMoore era. **Design Lead:** In the role of an RTL Design lead, you will experience the thrill of achieving bug-free RTL from requirements or specifications. Your expertise in driving the design effort for complex IP/Subsystem/SoC blocks, with a track record of multiple tape-outs, will be invaluable in delivering high-quality results. **Verification Lead:** As a Verification lead, you will enjoy the challenge of identifying and rectifying bugs to ensure the design intent is realized. Your role is critical in ensuring the flawless operation of chips, such as those on space telescopes capturing stunning images of galaxies. Your experience in leading multiple tape-outs and closing verifications of complex IP/Subsystem/SoC blocks will be instrumental in our success. **Design role:** In the position of a Senior RTL Subsystems Designer Lead with over 8 years of experience, you will be responsible for driving the Subsystem life cycle from requirements to final release phases. This includes crafting functional specifications, defining micro-architectures, coding RTL using best practices, conducting RTL quality checks, collaborating with Verification and implementation teams, and overseeing project completion. Proficiency in standard protocols like PCIe, DDR, UFS, USB, AMBA, as well as hands-on experience in low power design and understanding of DFT requirements and architecture are essential. Your ability to work effectively with cross-functional teams will be crucial in delivering successful projects. **Verification role:** In the role of a Senior Verification lead with over 8 years of experience, you will lead the complete Verification cycle by crafting test plans, architecting verification environments, developing test infrastructure, and executing plans to closure with coverage. Proficiency in Functional Verification of standard protocols like PCIe, DDR, UFS, USB, AMBA, as well as power-aware Verification with UPF, is required. Hands-on experience in Gate Level Verification is a valuable addition. Your collaboration with cross-functional teams will be key to driving projects to completion.,

You are a highly experienced ASIC RTL Design Architect responsible for leading the design and verification of cutting-edge SoCs and high-speed digital IPs. With over 10 years of experience in ASIC/FPGA design, your expertise lies in RTL using Verilog/SystemVerilog, Lint, CDC, and Spyglass-based design verification methodologies. Your main responsibilities include leading RTL design and micro-architecture for high-performance ASIC SoCs, ensuring compliance with Lint, CDC, and SDC constraints using Spyglass or equivalent tools, driving design optimization and timing closure, as well as collaborating with cross-functional teams such as Design Verification, DFT, Physical Design, and Software teams. You will also be involved in developing and reviewing architecture specifications, coding guidelines, and best practices, as well as performing synthesis, timing analysis, and static verification using tools like STA, LEC, and Formal Verification. Key requirements for this role include a minimum of 10 years of experience in ASIC RTL design and architecture, expertise in Verilog/SystemVerilog for RTL design, strong knowledge of Spyglass Lint/CDC and static verification methodologies, experience in SoC micro-architecture, high-speed interfaces, and power optimization. Additionally, you should have a solid understanding of synthesis, STA, timing closure, backend constraints, experience with EDA tools like Synopsys, Cadence, Mentor Graphics, and familiarity with UVM-based verification and scripting languages such as TCL, Python, or Perl. Preferred qualifications include an M.Tech/MS/PhD in Electrical Engineering, Computer Engineering, or related field, experience in chip tape-out and production silicon, and an understanding of hardware security, reliability, and safety standards. If you are looking to be part of a team that is shaping the future of high-performance computing, apply now and join us in building innovative solutions together.,

HCL Technologies is a next-generation global technology company that helps enterprises reimagine their businesses for the digital age. With a strong foundation built on four decades of innovation, a world-renowned management philosophy, and a relentless focus on customer relationships, we pride ourselves on our culture of invention and risk-taking. HCL is committed to diversity, social responsibility, sustainability, and education initiatives, exemplified by our worldwide network of R&D facilities and co-innovation labs. With over 187,000+ Ideapreneurs across 50 countries, we deliver holistic services across industry verticals to leading enterprises, including 250 of the Fortune 500 and 650 of the Global 2000. Enterprises today are at a critical juncture where digital technologies such as analytics, cloud, IoT, and automation are key to success. To help enterprises leverage these technologies for their business objectives, HCL offers an integrated portfolio of products and services through three business units: IT and Business Services (ITBS), Engineering and R&D Services (ERS), and Products and Platforms (P&P). As a Technology Manager at HCL Technologies in Ha Noi or Ho Chi Minh (Vietnam), your responsibilities will include managing technology in projects, providing technical guidance or solutions, developing and guiding team members to enhance their technical capabilities, preparing status reports to minimize exposure and risks on projects, ensuring process compliance, and participating in technical discussions or reviews. **Responsibilities:** - Manage technology in projects and provide technical guidance or solutions - Develop and guide team members to enhance their technical capabilities - Prepare and submit status reports to minimize exposure and risks on projects - Ensure process compliance in the assigned module and participate in technical discussions or reviews **Requirements:** - 5+ years of experience - Bachelors/Masters degree in Electronics/Electrical Engineering with 5+ years of experience in verification - Good understanding of ASIC/SoC life cycle - Experience in OVM/UVM methodologies using SV - Experience with Full chip test plan development/modification - Experience with Testbench development/modification, Test case development, coding, execution, bug analysis, Regressions, coverage analysis, Verification closure - Experience in prevalent standards & Protocols viz. PCIe Gen3/4/5/USB3/DDR4/5, /Ethernet/CSI2/I3C/AMBA - Experience with Gate level simulations - Experience in scripting - Participation in multiple ASIC/SoC verifications till tape out stage - Good command of English. Opportunity to work onsite in Japan **Benefits:** - 18 paid leaves per year (including 12 annual leaves + 6 personal leaves) - Insurance plan based on full salary + 13th salary + Performance Bonus - 100% full salary in probation period - Medical Benefit for Employee and Family - Fast-paced, flexible, and multinational working environment - Opportunity to travel onsite (in 49 countries) - Internal Training (Technical & Functional). Scope of English Training - Working hours: 8:30 AM-6:00 PM, Mondays to Fridays,

Core Technical Skills : SystemVerilog / UVM testbench and coverage methodologies Constraint-random verification, simulation and debug flow Formal verification techniques (e.g. Jasper, VC Formal) Scripting languages: Python, TCL, Perl, Shell Experience with high-speed protocols (PCIe, DDR, Ethernet) and emulation tools Resume & Interview Prep Advice : Highlight projects involving ASIC/SoC verification, testbench implementation, coverage closure using UVM/SystemVerilog Reddit+15Reddit+15Meta Careers+15Indeed+8Atos Jobs+8Indeed+8Reddit+1Indeed+1Reddit+2Meta Careers+2Reddit+2Reddit+2Reddit+2Reddit+2 Showcase contributions in debugging RTL, developing functional coverage models, and scripting automation for regressions Next Steps Role & responsibilities Preferred candidate profile

Strong on Digital Design, SV, UVM. Hands-on experience in any of the DV protocols like PCIe, USB 3.0, DDR 3/4/5, AMBA, Ethernet (10G/100G), SATA, and MIPI (CSI/DSI), UFS, CXL Also Hiring PD, RTL, DFT Apply& Share resume to mansoor@hisoltech.com

You are a Hardware Engineer / Hardware Lead at GRL, a world leader in testing and engineering services for hardware product developers. You will be based in Bangalore, India, and will play a crucial role in Analog, Digital, and Mixed Signal Embedded Hardware Product Development. Your responsibilities include using schematic, simulation, and layout review tools proficiently, designing mixed signal hardware, determining test requirements for hardware designs, supporting firmware/software teams, and producing high-quality technical documentation. You will collaborate with internal teams to understand product requirements, analyze existing content, create and maintain hardware design information, and write user guides and R&D documentation. To qualify for this role, you should have a BS in Electronics Engineering or related field with 5-10 years of experience. You must possess a good understanding of high-speed interfaces, experience in OrCAD for schematic design, ability to review PCB layouts, component selection optimization, technical documentation skills, and knowledge of DDR, I2C, SPI, ADC, DAC, and power supply. Expertise in interfaces like USB3&4, HDMI, DisplayPort, PCIe, or Thunderbolt is preferred. Join GRL, an Equal Opportunity Employer, and be part of a dynamic team that shapes the future of technology. Submit your CV to careers@graniteriverlabs.com to explore this exciting opportunity.,

Softnautics is seeking a skilled Verification Engineer to join our VLSI group function. As a Verification Engineer at Softnautics, you will play a crucial role in the architecture development, implementation, and documentation of verification IPs. You will be responsible for various tasks including SV/VUM coding, test-plan development, assertion and functional coverage coding, simulations, and more. Additionally, you will have the opportunity to lead a small team and contribute to the overall success of our projects. Responsibilities: - Understanding the standards and specifications relevant to the project - Developing and documenting architecture details - Hands-on involvement in all aspects of the verification cycle - Ensuring compliance with the latest methodologies - Creating Verification IPs - Defining Functional Coverage matrix and Comprehensive Test plan - Managing regression and achieving functional coverage closure - Integrating and verifying Design Under Test (DUT) for IP delivery sign-off - Leading a small team of engineers Required Skills: - Hands-on experience in complete verification cycle with a strong understanding of verification concepts - Proficiency in Verilog, SystemVerilog, and UVM - Experience in UVM based Verification IP development - Familiarity with AMBA AXI/AHB/APB System buses - Hands-on experience with protocols such as PCIe, Ethernet, USB, DDR, etc. - Knowledge of System Verilog Assertions - Proficiency in scripting for automation, release processes, simulations, and regressions - Excellent written and oral communication skills Desired Skills: - Experience in leading Verification IP development with junior engineers - Exposure to the full verification cycle If you are a confident, self-motivated individual with strong fundamentals in verification engineering, we encourage you to apply for this exciting opportunity at Softnautics. Join our team and be a part of a collaborative environment focused on delivering high-quality results.,

As a Senior Engineer, Analog Design at Micron Technology, your primary responsibilities will involve designing, implementing, and enhancing Complex Analog Circuits in advanced semiconductor process nodes for cutting-edge DRAM products. This includes the development of CMOS Amplifiers, Comparators, IO circuits (DDR/LPDDR) - Tx & Rx, DFE, CTLE, along with integrating modules with Power delivery network and proposing design solutions for optimal performance. You will be tasked with validating and optimizing designs for reliability, conducting Clock & Datapath design, performing EM/IR simulation, optimizing layout for enhanced circuit performance, as well as engaging in custom digital circuit design & validation. Additionally, you will be involved in parasitic modeling, assisting in design validation, reticle experiments, and necessary tape-out revisions. As part of your role, you will oversee and manage the layout process, including floor-planning, placement, and routing, while also conducting verification processes using industry-standard simulators. Collaboration will be key, as you will work across various groups such as Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering to ensure accurate manufacturability of products. Furthermore, you will play a crucial role in driving innovation for future Memory generations within a dynamic work environment. Your contributions will be vital in advancing technology and pushing boundaries to meet the evolving needs of the industry. Micron Technology, Inc. is a global leader in innovative memory and storage solutions, committed to transforming the way information is utilized to enhance life for all. With a strong focus on technology leadership, operational excellence, and customer satisfaction, Micron delivers a diverse range of high-performance DRAM, NAND, and NOR memory and storage products under the Micron and Crucial brands. If you are passionate about being part of a team that drives the data economy forward, enabling advancements in artificial intelligence and 5G applications from data centers to the intelligent edge and beyond, Micron is the place for you. Join us in shaping the future of technology and exploring new opportunities in the ever-evolving tech landscape. For more information about career opportunities at Micron, please visit micron.com/careers. For any assistance with the application process or to request reasonable accommodations, please reach out to hrsupport_in@micron.com. Micron upholds a strict policy against the use of child labor and adheres to all relevant laws, regulations, and international labor standards.,

As a Staff Engineer - Design Verification at Micron Technology, you will be part of a highly innovative and motivated design team working on cutting-edge memory technologies to develop advanced DRAM and Emerging memory products. Your role will involve verifying high density memory chips with complex circuit capabilities, ultra-high-speed designs, and next-generation DDR/LPDDR technologies. You will collaborate with various design and verification teams globally to ensure the successful completion of design projects. Your responsibilities will include: - Taking ownership of verification and conducting end-to-end analysis of complex block-level custom designs for DDR4, LPDDR4, DDR5, and LPDDR5 memory architectures operating at high speeds. - Guiding and directing the verification effort for all projects undertaken by the team. - Providing verification support by simulating, analyzing, and debugging pre-silicon block level/full chip designs. - Developing test cases and stimulus to enhance functional coverage for DRAM and emerging memory products. - Creating and maintaining test benches and test vectors using simulation tools, running regressions for coverage analysis, and collaborating with international colleagues to develop new verification flows. - Contributing to the development of verification methodologies and environments for advanced DRAM and emerging memory products. - Demonstrating a good understanding of digital/mixed-signal circuits and experience in digital/mixed-signal verification. - Utilizing tools like Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, and Hspice. - Writing Verilog and Real Number Models, as well as building SV testbenches at block and full-chip levels. - Implementing SV and UVM-based verification, with proficiency in scripting using Perl and Python. - Having previous experience in DRAM memory-related fields is advantageous, along with possessing strong communication, debugging skills, and the ability to work effectively in a team. To qualify for this role, you must hold a Bachelor's or Post Graduate Degree in Electronics Engineering or a related field, with 5-15 years of relevant experience. Micron Technology, Inc. is a global leader in memory and storage solutions, driving innovations that enhance the way information is used to enrich life for all. With a focus on customer satisfaction, technology leadership, and operational excellence, Micron offers a range of high-performance DRAM, NAND, and NOR memory and storage products through its Micron and Crucial brands. The advancements made by Micron's team members contribute to the data economy, enabling progress in artificial intelligence and 5G applications across various platforms. For more information, please visit micron.com/careers. If you require assistance during the application process or need accommodations, please contact hrsupport_in@micron.com. Micron Technology strictly prohibits the use of child labor and complies with all relevant laws, regulations, and international labor standards.,

As a Design Verification Engineer at our company, you will be responsible for verifying high-speed interfaces such as DDR, PCIe, UCIe, or NVMe. You will need a Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field along with at least 4 years of hands-on experience in design verification. Your role will require expertise in SystemVerilog and UVM (Universal Verification Methodology) as well as a strong understanding of digital design principles, verification methodologies, and simulation tools. It is essential for you to be familiar with protocol specifications and industry standards for the interfaces mentioned above. You should have experience working with simulation tools like VCS, ModelSim, or Questa, and be proficient in debugging tools such as Waveform Viewers, Logic Analyzers, and protocol analyzers. The ability to write efficient and reusable verification components like scoreboards, monitors, and sequencers is crucial for this role. Strong problem-solving skills, attention to detail, and excellent communication skills are also required. You should be comfortable working in a collaborative environment and have a willingness to engage with team members effectively. Preferred qualifications for this role include experience with formal verification techniques, knowledge of interface protocols like USB, Ethernet, or SATA, proficiency in scripting languages for automation (e.g., Python), and familiarity with FPGA-based verification platforms and hardware debugging tools. If you are someone who enjoys working on challenging projects, has a passion for design verification, and meets the qualifications mentioned above, we would love to have you join our team in Bangalore or Hyderabad.,

Job Summary: Seeking an experienced FPGA developer to join our team and work on the design and development of complex FPGA-based systems. The ideal candidate will have a strong background in FPGA design, verification, and implementation, as well as experience working with hardware and software engineers to integrate FPGA designs into larger systems.

We are hiring RTL Design Engineers with strong expertise in developing high-performance digital designs for ASIC/SoC products. Contact-7982405927

Job Overview We are seeking an experienced and highly skilled Senior SOC Design Verification Engineer with a minimum of 5 years of hands-on experience in SOC Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System on Chip designs. Job Description Lead and manage SOC Design Verification efforts for complex projects, ensuring the successful execution of verification plans. Develop and implement comprehensive verification strategies, test plans, and test benches for high-speed SOCs, including low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI, and high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR and HBM Conduct Gate-level simulations, and power-aware verification using Xprop and UPF.Collaborate closely with cross-functional teams, architects, designers, and pre/post-silicon verification teams. Analyze and implement System Verilog assertions and coverage (code, toggle, functional). Provide mentorship and technical guidance to junior verification engineers.Manage and lead a dynamic team of verification engineers, fostering a collaborative and innovative work environment. Ensure verification signoff criteria are met and documentation is comprehensive.Demonstrate dedication, hard work, and commitment to achieving project goals and deadlines. Adhere to quality standards, implement good test practices, and contribute to the continuous improvement of verification methodologies. Experience with verification tools from Synopsys and Cadence, including VCS and Xsim. Integration of third-party VIPs (Verification IP) from Synopsys and Cadence. Qualifications Bachelors degree in computer science, Electrical/Electronics Engineering, or related field. ORMasters degree in computer science, Electrical/Electronics Engineering, or related field. ORPhD in Computer Science, Electrical/Electronics Engineering, or related field. 5+ years of hands-on experience in SOC Design Verification. Expertise in UVM (Universal Verification Methodology) and System Verilog. Prior experience working on IP level and SOC level verification projects. Proficient in verification tools such as VCS, Xsim, waveform analyzers, and third-party VIP integration (e.g., Synopsys VIPs and Cadence VIPs). Hands-on experience with UFS (Universal Flash Storage), Ethernet, PCIe, CXL, MIPI protocols.Solid understanding of low-speed peripherals (I2C/I3C, SPI, UART, GPIO, QSPI) and high-speed protocols. Experience in DDR, HBM, Gate-level simulations, and power-aware verification using Xprop and UPF. Proficiency in scripting languages such as shell, Makefile, and Perl. Strong understanding of processor-based SOC verification, including native, Verilog, System Verilog, and UVM mixed environment. C-System Verilog handshake and writing C test cases for bootup verification. Excellent problem-solving, analytical, and debugging skills.

As a Design Verification Engineer, you will be responsible for verifying complex designs such as accelerators, datapath IP, processor core subsystems, and complex interfaces/protocols using leading-edge methodologies like UVM and Formal DV. Your role will involve architecting the testbench, developing the verification environment, and defining test plans, tests, and verification methodology for block/sub-system level verification. You will collaborate with the design team to generate test plans, ensure code and functional coverage closure, integrate block testbenches at the sub-system level UVM environment, and verify integration. Additionally, you will interact with the analog co-simulation and firmware team to enable top-level chip verification aspects. Your responsibilities will also include packaging verification environments for Digital IP for seamless integration into the verification flow at different stages of execution. You will evaluate 3rd party IPs on key qualitative aspects and establish evaluation flows for home-grown and 3rd party IPs for consistent benchmarking of DV evaluation. To excel in this role, you should have a minimum B.E./B.Tech degree in Electrical/Electronics/Computer Science and 7-10+ years of experience in design verification with UVM and constrained random, coverage-based verification approaches. You must possess a strong understanding of DV concepts and the ability to develop scalable DV environment architecture for achieving first-pass DV success. Your adaptability to learn end application/systems and map them into smart verification test plans will be crucial. Excellent debugging and analytical skills, along with good interpersonal, teamwork, and communication skills, are essential for effectively driving discussions with geographically dispersed teams. Knowledge of assertion-based formal verification, standard on-chip interfaces, processor/SoC architecture, and/or DSP fundamentals will be advantageous. Experience with ASIC/SoC product DV and productization is highly desirable for this role.,

As an FPGA Design and Verification/Validation Engineer at Dexcel Electronics in Bengaluru or Hyderabad, you will be responsible for independently overseeing FPGA Design Blocks. You should have a minimum of 2 years of experience in RTL Design, 2 years in IP Verification, 4 years in IP Design/SOC Design, and 6 years in FPGA Design. Your primary task will involve working with various Interfaces such as PCIe 2.0, SATA, Fiber Channel, 1G/10G BASE, MII/RMII/GMII/RGMII/SGMII/XAUI, RXAUI, SDI- SD/HD/3G, Display Port, USB, JESD204B, SRIO, MIPI, DDR/LPDDR/DDR2/DDR3, and QDR memories. Additionally, hands-on experience in Design and Debugging is preferred. You should have prior experience working on projects based on FPGAs and SOC, with a solid understanding of SOC and Hi-Speed Interfaces domain knowledge. At Dexcel Electronics, we are seeking highly motivated individuals who are eager to learn and develop in a dynamic environment. If you are passionate about technology and seeking exciting career opportunities, we invite you to join our team. For more information on current job openings, please visit our website or email your updated resume to careers@dexceldesigns.com.,

As a Lead Analog Validation Engineer, you should have a minimum of 7 years of experience and hold a Bachelors or Masters degree in Electronics or Electronics & Communication. Your expertise should include a strong understanding of electrical circuit analysis, design, and test fundamentals. You must be proficient in automating Analog Characterization Setups using Labview and Test Stand, and have strong debugging and problem-solving skills. Your responsibilities will include bringing up Silicon & Analog Validation Platforms for new ASIC/SoC designs, developing bench characterization test methodologies for various Analog IPs such as ADC, DAC, PLL, USB, VREG, OSC, DDR, LOW POWER, and IO PADs. You will also be required to develop automated code to control test equipment and generate required PVT electrical parameters. Additionally, you should possess expertise in using test & measurement equipment for Analog Validation, PVT characterization of Analog IPs, and have experience in Multilayer Board design, testing, integration, and Signal Integrity issues. Knowledge of C programming is essential for this role. Strong leadership and planning skills are crucial as you will be expected to deliver timely results in lead positions. You will work closely with cross-functional teams including marketing, systems, design, test, and project management to support the successful launch of new products. Your ability to communicate effectively with individuals from diverse backgrounds and strong team-building skills are essential for this role. Your motivation and energy to tackle bench characterization challenges on stand-alone/automated setups will be key to success in this position.,

You will be responsible for designing and leading the development of high-speed IP such as GDDR7, DDR5, and LPDDR6. As a strong individual contributor in the analog domain, you will actively participate in all aspects of development including analog design, layout, digital design, documentation, and silicon validation. Your role will also involve engaging in customer-facing discussions to address their requirements and concerns. To qualify for this position, you should hold a B.Tech / BE / ME / Mtech degree with at least 5 to 15+ years of experience. It is essential to have hands-on design experience and leadership skills in GDDR/DDR/LPDDR IPs. A successful candidate must have been involved in the entire cycle of analog IP creation, from specification to silicon debugging and characterization. Good communication skills and the ability to work effectively in a team are crucial for this role. Moreover, expertise in areas such as PLL, high-speed circuits like TX, RX, clocking circuits, etc., is mandatory. Experience with other common IP blocks like BGR, LDO, POC, temperature sensor, etc., would be considered advantageous.,

The ideal candidate for this position should have at least 7+ years of experience in the field. The location for this role includes Bangalore, Delhi NCR, and Hyderabad with 8-10 openings available. The preferred education qualifications are BE/B.Tech./MS/M.Tech. in Electronics or Electronics & Communication. **Required Basic Qualification & Skills:** - Strong understanding of electrical circuit analysis, design, and test fundamentals - Automation of Analog Characterization Setups using Labview and Test Stand - Strong debugging and problem-solving skills - Experience in bring up of Silicon & Analog Validation Platforms - Proficiency in C programming - Leadership and planning skills for timely results delivery **Additional Preferred Qualifications:** - Expertise in using test & measurement equipment for Analog Validation - PVT characterization experience of Analog IPs like ADC, DAC, PLL, USB, VREG, OSC, DDR, LOW POWER, and IO PADs - Good debugging exposure and root cause analysis for new analog designs - Knowledge of Multilayer Board design, testing, integration, and Signal Integrity issues - Experience with LabVIEW and Test Stand automation software - Working experience in a lab environment **Primary and Secondary Responsibilities:** - Develop unique bench characterization test methodologies for Analog IPs - Write automated code for controlling test equipment during data collection and processing - Perform Design Evaluation and Bench Characterization for Analog IPs - Provide requirements and review schematics for circuit board development **Other Complex Tasks:** - Provide customer application note support by generating characterization data - Collaborate with cross-functional teams for successful product launches **Team and People Skills:** - Strong team-building skills and effective communication abilities are essential for this role.,

As FPGA Architect, you will play a pivotal role in leading the design and development efforts across a range of projects in a dynamic and collaborative environment. Your primary responsibility will involve defining and creating complex FPGA designs for our Test products. Working closely with a diverse team including R&D Project Managers, Product Architects, Solution Teams, FPGA developers, Software Qualification, and Software Engineers, you will contribute to the innovation of new product offerings and enhancements to existing products. A vital aspect of this role will be your ability to work effectively with design teams based in the US and Europe, showcasing your strong teamwork skills and collaborative mindset. To excel in this role, you should possess the following qualifications: - A Bachelor's or Master's degree in Electrical/Electronic Engineering - Minimum of 10 years of experience in FPGA development with expertise in Altera and Xilinx technologies - Proficiency in RTL languages such as VHDL or Verilog - Familiarity with Xilinx FPGA Tools Design Flow including Vivado, Chipscope, and Quartus - Experience in using EDA Functional Simulation tools like Synopsys, Mentor, or Cadence - Proven ability to adapt quickly to new technologies, protocols, and product segments - Hands-on experience in developing self-checking Simulation environments, test benches, automation scripts, and test case creation - Collaborative work with system architects to define system architecture and FPGA integration with other components on PCA boards - Strong background in timing closure for intricate designs - Exceptional written communication skills for creating various technical documents such as Product Definitions, Detailed FPGA Designs, and Hardware & Software Interface documents - Self-motivated, well-organized, and proactive individual - Excellent team player with a high level of responsiveness and accountability - Strong verbal communication skills Preferred qualifications include: - Familiarity with Keysight instruments like Oscilloscope, Analyzer, AWG & BERT - Experience working with protocols such as PCI Express, USB, MIPI, Ethernet, and DDR - Exposure to international and multi-vendor collaboration environments - Full-time job type with flexible schedule This role offers the opportunity to work in person at the specified location, providing a conducive environment for professional growth and innovation.,