38 Serdes Jobs

: 6 to 8 years of Semiconductor industry experience in Custom Mixed-Signal layout design with a bachelors degree in electrical/Electronic Engineering. Able to deliver Custom analog layouts independently from schematic to layout generation, estimating the area, optimizing floorplan, routing, and complete verification flows. Firsthand experience in critical analog layout design blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc. Good at LVS/DRC debugging skills and other verifications for lower technology nodes - 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is necessary. Understanding layout effects on the circuit such as speed, capacitance, power, and area etc. Ability to understand design constraints and implement high-quality layouts. Multiple Tape out support experience and collaborating with cross functional teams will be an added advantage. Good people skills and critical thinking abilities to resolve the issue technically and professionally. Excellent communication. Responsible for timely execution with high quality of layout design. Multiple foundries experience is an added plus. Minimum Educational Qualification : Educational Bachelor's, Electrical or Electronics Engineering or equivalent Role And Responsibilities Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, EM, quality check and documentation. Responsible for on-time delivery of block-level/top-level layouts with acceptable quality. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Guide junior team-members in their execution of Sub block-level layouts & review their work Should have good experience in working with cross-functional team. Ensure standard processes and procedures are followed to resolve all client queries. Handle technical escalations through effective diagnosis and troubleshooting of client queries Manage and resolve technical roadblocks/ escalations to timely deliverable with high quality. Troubleshoot all client queries in a user-friendly, courteous, and professional manner. Offer alternative solutions to clients (where appropriate) with the objective of retaining customers' and clients' business. Build people capability to ensure operational excellence and maintain superior customer service levels of the existing account/client. Contribute to effective project-management. Effectively communicating with engineering teams in different Geographical locations to assure the success of the layout project. Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications.1. Applies scientific methods to analyse and solve software engineering problems.2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance.3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers.4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities.5. The software engineer collaborates and acts as team player with other software engineers and stakeholders.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Serdes PHY Analog Design Job Function BDC SerDes Mixed-Signal design team is actively looking for experienced (4-12+ years) analog circuit designers to work on high speed SerDes PHYs . You will be directly involved in delivering next-generation custom PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-nodes - finfets & beyond. Design goals include low-power analog designs to address Qualcomm's low-power wireless products. Responsibilities Hands-on experience - Analog circuit design Experience in designing multiple analog building blocks - LDO, high speed TX and RX (Equalizer, Sampler, PI, Deserializer etc) , Bias, Reference etc. Analog and or Digital PLLs for frequency synthesis and/or SerDes applications" Charge pump, loop filter, VCO/DCO, PFD/TDC, high speed dividers. PLL Loop Dynamics, Jitter sources and modeling (RJ & DJ) Ability to take a design, perform schematic to post layout verification, integration sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Skills & Experience For lead position, candidates must have performed PHY Lead roles which include PHY integration to SOC & interaction with post silicon teams like HSIO, ATE, SVE, CE etc. Understanding of advance Finfet process effects on designs and layout is required. Experience in using SPICE simulators, adexl & virtuoso. Experience with post-Si bring-up and debug is must. Good understanding on peripheral PHYs (USBs, UFS, PCIe) protocols is added advantage. Master/Bachelor in Electronics Shell/Perl-python scripting to automate circuit design and verification work. Able to work with teams across the globe and possess good communication and presentation skills. Preferred Mixed signal design experience Keywords Analog circuit Design, Rx, Tx, PLL, SerDes, PHY, Serializer, Deserializer, VCO, High-speed Trans receiver

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Job Function BDC SerDes Mixed-Signal design team is actively looking for experienced (12+ years) analog circuit designers to work on high speed SerDes PHYs . You will be directly involved in delivering next-generation custom PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-nodes - finfets & beyond. Design goals include low-power analog designs to address Qualcomm's low-power wireless products. Responsibilities Hands-on experience - Analog circuit design Experience in designing multiple analog building blocks - LDO, high speed TX and RX (Equalizer, Sampler, PI, Deserializer etc) , Bias, Reference etc. Analog and or Digital PLLs for frequency synthesis and/or SerDes applications" Charge pump, loop filter, VCO/DCO, PFD/TDC, high speed dividers. PLL Loop Dynamics, Jitter sources and modeling (RJ & DJ) Ability to take a design, perform schematic to post layout verification, integration sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY. Skills & Experience For lead position, candidates must have performed PHY Lead roles which include PHY integration to SOC & interaction with post silicon teams like HSIO, ATE, SVE, CE etc. Understanding of advance Finfet process effects on designs and layout is required. Experience in using SPICE simulators, adexl & virtuoso. Experience with post-Si bring-up and debug is must. Good understanding on peripheral PHYs (USBs, UFS, PCIe) protocols is added advantage. Master/Bachelor in Electronics Shell/Perl-python scripting to automate circuit design and verification work. Able to work with teams across the globe and possess good communication and presentation skills. Preferred Mixed signal design experience Keywords Analog circuit Design, Rx, Tx, PLL, SerDes, PHY, Serializer, Deserializer, VCO, High-speed Trans receiver

Analog layout design requires knowledge of designing layouts of complex VLSI (very large scale integration) circuits using graphic editing tools in the Analog domain. A major portion of the job is in the creation of new physical design data from concepts, partial schematics, or a working knowledge of overall requirements. Responsibilities include checking the design integrity with respect to semiconductor ground rules and the logical function of the circuit. Symbolic circuit data (schematics) are converted to physical shapes which represent the semiconductor process. The role ranges from manual shapes and checking tool manipulations to extended team coordination and methodology creation. The employee guides functional objectives or technologies. Your Role and Responsibilities Hands-on work on custom layout for analog blocks like High Speed SerDes and General purpose IO designs with Cadence Virtuoso on latest technologies like 5nm and below , and also take leadership roles in delivery of IPs. Work on Floor planning, power design, signal routing strategy, EMIR awareness, and parasitic optimizations . Understand and apply analog Layout techniques to ensure the design meets performance with minimum possible area and good yield. Participate in building and enhancing layout flow for faster, higher quality design process. Checking physical verifications like DRC/LVS/ERC/ANT/DFM and other IBM internal checks. Collaborate with Circuit Designers to solve challenging problems. Writing SKILL/PYTHON scripts to automate repetitive tasks. Work with Place and Route engineer to integrate custom macros into the top level. Able to perform design reviews across global teams. Work closely with required global teams to ensure the success of the whole product. Leadership in delivery of macros we plan to own from India. Job Requirements Experience in doing layouts for analog blocks like SerDes, ADCs, DACs, LDOs, PLLs, BGAP & amplifiers , etc. Experience in designing layouts for high-speed circuits is a plus. Layout experience in the following technology nodes: 3nm, 5nm, and 7nm FinFET . Good team worker with multi-discipline, multi-cultural, and multi-site environments. Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability, and failure mechanisms. Good problem-solving skills are essential where problems are analyzed upfront, identifying gaps, and providing optimum solutions. Knowledge in Skill/perl/tcl/Python scripting is a plus. Required Education Bachelor's Degree Preferred Education Master's Degree Required Technical and Professional Expertise The Analog layout design engineer with experience in next-generation Ultra high-speed serial IO link (HSS) interface for Cognitive, ML, DL, and data center applications. The engineer needs to have knowledge in the design and development full custom analog layouts for ultra high-speed 32G/50G/112G IO link interfaces . Preferred Technical and Professional Experience Experience in 7 and 14 nm analog layout design . Working on Cutting edge technology and HSS domain. Quick learner, deep layout design knowledge, problem-solving skills, and good communication skills with cross teams across the Geos.

1. Hands on work on custom layout for analog blocks like High Speed SerDes and General purpose IO designs with Cadence Virtuoso on latest technologies like 5nm and below and also take leadership roles in delivery of IPs 2. Work on Floor planning, power design, signal routing strategy, EMIR awareness andparasitic optimisations 3. Understand and apply analog Layout techniques to ensure the design meets performance with minimum possible area and good yield. 4. Participate in building and enhancing layout flow for faster, higher quality design process. 5. Checking physical verifications like DRC/LVS/ERC/ANT/DFM and other IBM internal checks 6. Collaborate with Circuit Designers to solve challenging problems 7. Writing /PYTHON scripts to automate repetitive tasks 8. Work with Place and Route engineer to integrate custom macros into top level. 9. Able to perform design reviews across global team 10. Work closely with required global teams to ensure the success of the whole product. 11. Leadership in delivery of macros we plan to own from India Job requirements: 1. Experience in doing layouts for analog blocks like SerDes, ADCs, DACs, LDOs, PLLs, BGAP & amplifiers etc. 2. Experience in designing layouts for high-speed circuits is a plus. 3. Layout experience in the following technology nodes3nm, 5nm and 7nm FinFET. 4. Good team worker with multi-discipline, multi-cultural and multi-site environments 5. Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability and failure mechanisms6. Good problem-solving skills are essential where problems are analysed upfront, identifying gaps, and providing optimum solutions7. Knowledge in Skill/perl/tcl/Python scripting is a plus. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise The Analog layout design engineer with experience in next generation Ultra high speed serial IO link (HSS) interface for Cognitive, ML,DL, and data center applications. The engineer needs to have knowledge in the design and development full custom analog layouts for ultra high speed 32G/50G/112G IO link interfaces. Preferred technical and professional experience Experience in 3,5,7,14 nm analog layout design. Working on Cutting edge technology and HSS domain . Quick learner, deep layout design knowledge, problem solving skills and good communication skills with cross teams across the Geos.

You're an experienced and passionate Analog and Mixed-Signal (A&MS) Senior Circuit Design Expert with a strong background in PLL and SERDES design . You bring a deep understanding of mixed-signal techniques for dynamic and static power reduction, performance enhancement, and area reduction. Your expertise covers circuit architectures simulation, circuit layout, and knowledge of bipolar, CMOS, passive structures, and interconnect failure modes in advanced FinFET technology nodes. You excel at developing Analog Full Custom circuit macros , including PLLs, Clock Path Functions, clocking solutions, TX/RX datapaths, and power management and regulation for High Speed PHY IP in both planar and FinFET CMOS technology. You thrive in collaborative environments, working closely with silicon test and debug experts to enhance quality through Sim2Sil correlation . You're also passionate about building and nurturing analog design talent to boost business impact through successful project execution. What You'll Be Doing: Leading SERDES analog design and development. Analyzing various mixed-signal techniques for power reduction, performance enhancement, and area reduction. Developing Analog Full Custom circuit macros for High Speed PHY IP in advanced technology nodes. Collaborating with silicon test and debug experts for Sim2Sil correlation. Building and nurturing a team of analog design talent. Working with experienced teams both locally and globally. The Impact You Will Have: Driving innovation in mixed-signal analog design. Enhancing the performance and efficiency of high-speed physical interfaces. Contributing to the development of cutting-edge technology in High Speed PHY IP. Improving quality and reliability through collaboration and Sim2Sil correlation. Growing the business impact by building and leading a talented team. Advancing Synopsys leadership in chip design and IP integration. What You'll Need: BE with 18+ years or MTech with 15+ years of relevant experience in mixed-signal analog, clock, and datapath circuit design. Strong knowledge of RF architecture and blocks such as transceivers, VCOs, LNA, and up/down converters. Experience in designing Charge-pump-based PLLs, Fractional-N PLLs, Digital PLLs, XTAL oscillators, and LO generation circuits. Proficiency in high-speed digital circuit design and timing/phase noise analysis. Ability to create behavioral models of PLL to drive architectural decisions. Who You Are: Possessing strong fundamentals in CMOS, device physics, and sub-micron design methodologies. Experienced with PLL designs and high-speed digital circuit design. Knowledgeable in control systems, band gaps, bias, op-amps, LDOs, and feedback techniques. Experienced in LC VCO/DCO design and performance parameters of VCO. Familiar with digitally assisted analog circuit techniques. The Team You'll Be A Part Of: You'll be joining an expanding analog/mixed-signal SERDES team focused on the design and development of cutting-edge High Speed Physical Interface Development . You'll collaborate with experienced teams locally and with colleagues from various sites across the globe, fostering a truly collaborative and innovative environment.

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Develop the verification environment and test bench and creating testcases. Debug fails using waveform, trace tools and debug RTL code Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5 + years of experience in Functional Verification of Processors or ASICs. Minimum 3+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Multi-processor cache coherency, Memory subsystem, IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Good object-oriented programming skills in C/C++, and any of scripting languages like Python/Perl Development experience on Linux/Unix environments and in GIT repositories and basic understanding of Continues Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in verification coverage closure Preferred technical and professional experience Verify the different functions/components in a PCI Express Controller & high speed SERDES (PHY). Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug Formal verification experience

• Drive Area estimation, Floor Planning, Placement, Routing, Power planning, Verification, EMIR, ESD-LUP Verification & Tape out. • Understanding of low parasitic, high frequency design techniques. • Finfet process & Lower nodes; 2nm/3nm/5nm/7nm Required Candidate profile • Exp with Cadence (Virtuoso), Synopsys (CC), Calibre & ICV verification tools like LVS, DRC, Extraction. • Debugging/fixing LVS/DRC errors • Experience with EMIR, PERC tools. • Skill/TCL scripting.

Knowledge of High-Speed Board Design Experience in designing with memories like DDR3 / DDR4 / eMMC / NAND / NOR Flash etc. Experience in designing with High-speed communication protocols like PCIe / SerDes / USB3.0 / SGMII / SFP+ /10G/100G/ Hands-on experience with MII, SGMII, RGMII, HSGMII, QSGMII, XGMII and its PHY interfaces Hands-on experience with Intel or Broadcom or Marvel or MediaTek Quad/Octal port Ethernet PHYs transceivers Should have design experience in Multiport Gigabit Network Switches, Hubs and Gigabit Router Added Advantage for knowledge of PoE 802.3at , PoE+ 802.3bt Type 2 , or PoE++ 802.3bt Type 3 or 4PPoE PoE++ Type 4 Should Have Experience of different Gbit Standard such as 1000Base – SX, 1000Base-LX, 1000Base- CX, and 1000Base-T 1Gb/s SFP(INF-8074i),10Gb/s SFP+ (SFF-8431 4.1) or 25Gb/s SFP28 (SFF-8402) and QSF,QSFP+,QSFP28 would be advantage Experience with High-speed Hardware design, Complex Analog and Digital Hardware System level design, circuit analysis, SI/PI, PSPICE simulation, Boundary scan, EMC/EMI analysis and safety standards Responsibilities include Schematic Capture, Component Selection, Library Creation and Guiding Board Layout. Should Have product development understanding like Enterprise switching, Port extender, Embedded Ethernet fabric, and TSN products Hands-on experience in Telecom/Datacom product design Experience like PDH/SDH/SONET/ and fibre optic products Should Have telecom backhaul Network transmission products design Experience, Experience in working with complex ASSPs, Microprocessors/controllers and FPGAs Experience in Signal Integrity / Power Integrity Should have worked on testing equipment like high-speed Oscilloscope, Network analysers, spectrum analysers etc

Requirement : Analog Circuit Design Lead Experience Range : 7 - 12 Yrs. Work Location(s) : Bengaluru, Karnataka Candidates who are ready to join Immediately Requirements: Experience in entire Analog IP development including circuit design, layout, AMS verification, and characterization. Must have led the entire Analog IP development cycle and team. Circuit Design implementation of IPs including LDOs, Band Gap reference, Current Generators, POR, ADC/DACs, PLLs, Oscillators, General Purpose IOs, Temperature sensor, SERDES, PHYs, Die to Die interconnect, High-speed IOs, etc. Analog/custom layout design in advanced CMOS process. Ability to understand design constraints and implement high-quality layouts. Conceptualize and implement chip-level mixed signal simulation environments (testbenches, run scripts, etc...). Characterization . Hands-on experience on lower FINFET technology nodes and design/PPA trade-offs

Job Details: : Intel is a leader in the wireless communication industry, offering products that set the benchmark for performance and innovation. We are seeking a motivated Junior SerDes PHY Integration Engineer to join our team. In this role, you will focus on integrating physical layer components for high-speed SerDes systems, playing a crucial part in ensuring their performance and reliability.Key Responsibilities:SerDes PHY IntegrationsSupport the integration of the physical layer for SerDes systems, including transmitter and receiver architectures, equalization techniques, and signal integrity.Simulation and ValidationAssist in conducting simulations using MATLAB and Python, along with lab testing, to validate the performance and compliance of the SerDes PHY, optimizing it for high-speed data transmission.Calibration TechniquesHelp integrate calibration methods to enhance the performance of the SerDes PHY, ensuring high-quality data transmission.CollaborationWork collaboratively with cross-functional teams, including digital design, hardware, and software, to ensure seamless integration of the PHY layer into the overall SerDes system.DocumentationContribute to maintaining detailed and up-to-date documentation of design specifications, test plans, and results.Problem-SolvingAssist in addressing and resolving technical issues related to the SerDes PHY, ensuring optimal performance.Quality AssuranceSupport the implementation of quality control measures and best practices to ensure the reliability and robustness of the SerDes PHY.Develop SERDES TestsParticipate in the development of comprehensive tests to support integration efforts, including writing scripts for software and firmware in Intel's test environment. Qualifications: Bachelor's degree in Electrical Engineering; a Master's degree in a relevant field is a plus.Passion for lab work, collaboration, and solution development.Familiarity with scripting and programming languages such as C, C#, MATLAB, and Python.Experience in silicon development and SerDes technologies is beneficial.Strong problem-solving abilities and analytical skills.Self-motivated and capable of executing tasks in uncertain environments.Demonstrated ability to contribute effectively in a matrix organization. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Analog Design Engineer Skills & Experience Required: 5+ years of relevant experience. Has relevant knowledge and hands on experience of SerDes design at high data rates, up to 20Gbps. Study the assigned block, analyze the circuit carefully, and work on the hand analysis. Understand the required performance, the targeted specs and trade-off between different performance metrices. Write behavioral model of the circuit blocks for system-level simulations. Simulate and verifying designed schematics using Synopsys tools using circuit simulators. Debug to find out the root cause for any performance degradation. Being capable of solving all the faced issues. Working with layout team on layout optimization. Evaluate post layout performance using extraction tools (ICV and Calibre). Understand the interface with other blocks (if any) and work with other team members to optimize the interface. Coordinate and handling top-level simulations. Develop and executing characterization plans of the designed blocks, systems, and chips. Check the design reliability (EM/IR/Aging) using available tools. Do timing models using custom static timing analysis tools. Deliver the corresponding documentation as per the design process. Excellent knowledge of design/simulation tools such as Synopsys, Cadence and/or Mentor tools or any relevant tool. Good knowledge of any EM simulation tool. Good knowledge in behavioral modeling (Verilog, Verilog AMS). Very Good knowledge of custom timing static analysis tool (Synopsys NanoTime and SiliconSmart). Job Location IndiaBangalore IndiaChennai IndiaHyderabad IndiaKolkata IndiaNoida S. KoreaSeoul Location - Bengaluru,Chennai,Kolkata,Noida

locationsIndia, Bangaloreposted onPosted Today job requisition idJR0275251 Job Details: About The Role : Intel is at the forefront of the wireless communication industry, offering cutting-edge products that set the standard for performance and innovation. We are seeking a highly skilled SerDes PHY System Engineer to join our team. In this pivotal role, you will be responsible for the design and development of physical layer components for high-speed SerDes systems, ensuring their performance and reliability. Key Responsibilities: SerDes PHY DesignLead the design and development of the physical layer for SerDes systems, including transmitter and receiver architectures, equalization techniques, and signal integrity. Simulation and ValidationConduct comprehensive simulations using MATLAB and Python, along with lab testing, to validate the performance and compliance of the SerDes PHY, optimizing it for high-speed data transmission. Calibration TechniquesDevelop and implement calibration methods to enhance the performance of the SerDes PHY, ensuring high-quality data transmission. CollaborationWork closely with cross-functional teams, including digital design, hardware, and software, to ensure seamless integration of the PHY layer into the overall SerDes system. DocumentationMaintain detailed and up-to-date documentation of design specifications, test plans, and results. Problem-SolvingAddress and resolve complex technical issues related to the SerDes PHY, ensuring optimal performance. Quality AssuranceImplement quality control measures and best practices to ensure the reliability and robustness of the SerDes PHY. Qualifications: Bachelor's degree in Electrical Engineering; a Master's degree in a relevant field is preferred. Minimum of 5 years of experience in wired or wireless communication systems. Proven experience and enthusiasm for lab work, collaboration, and solution development. Prior experience in DDR/PCI/GDDR7/UCI will be added advantage. Proficiency in scripting and programming languages such as C, C#, MATLAB, and Python. Experience in silicon development and SerDes technologies is advantageous. Strong problem-solving abilities and analytical skills. Self-motivated and capable of executing tasks in uncertain environments. Demonstrated leadership skills and ability to drive initiatives in a matrix organization. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Defining and developing ASIC RTL design and verification at both chip and block levels. Writing and modifying test cases, checkers, and scoreboards in a system Verilog-based test environment. Collaborating with cross-functional teams to ensure seamless integration of analog and digital components. Conducting AMS verification, particularly for high-speed SerDes designs supporting multi-protocols. Utilizing Synopsys analog mixed-signal design tools for efficient design and verification processes. Programming and scripting using TCL, Perl, and Python to automate and streamline workflows. The Impact You Will Have: Enhancing the performance and reliability of our high-performance silicon chips. Contributing to the development of innovative technologies that drive the Era of Pervasive Intelligence. Improving the efficiency and effectiveness of our design and verification processes. Ensuring the seamless integration of analog and digital components in our products. Supporting the creation of cutting-edge solutions for self-driving cars, learning machines, and more. Driving continuous technological innovation within Synopsys and the broader industry. What You ll Need: Looking for 2+yrs experience with BTech / MTech in VLSI / Electronics/ Microelectronics Knowledge or hands-on expertise/analysis of Analog and digital CMOS circuit designs Knowledge on electrical circuit networks and analysis Knowledge or hands-on Verilog/System Verilog languages and supported methodologies like VMM, UVM Must be able write/modify testcases, checkers, scoreboards in a system Verilog based test environment AMS verification experience in high speed Serdes designs supporting multi-protocols is an advantage. Experience with the Synopsys Analog mixed-signal design tool set is an advantage. Modelling languages Verilog-a/ams can be an advantage Programming/scripting know-how e. g. tcl, perl, python Experience with Linux Good communication skills, ability to take ownership Self-organized to ensure that project timescales are met Who You Are: Excellent communicator with strong interpersonal skills. Proactive and able to take ownership of projects. Self-organized and capable of managing time effectively. Collaborative team player who thrives in a dynamic environment. Detail-oriented and committed to delivering high-quality results.

Job Requirement: We are looking to hire engineers with 5 to 10 years of experience in Analog circuit design. Candidate needs to have comprehensive knowledge of Analog design with experience in some blocks like OpAmps, Comparators, Bandgap References, LC and ring oscillator, PLLs, CDR, LDO, Tx/Rx etc Should have understanding of process technologies and device behaviour and reliability issues, ESD and latchup Should have understanding of various aspects of signal integrity. Experience in Rx, Tx, T-coil ESD, CDR, equalization techniques like CTLE/DFE in PCIE or Ethernet is preferred. Strong documentation skills and collaborative attitude are must haves

Role & responsibilities Bachelor's/Masters Degree in Electronics/Computer Engineering. 6+ years of in-depth experience in x86 architecture and hardware design. System design experience is preferred. Experience in schematics design tool like concept HDL, and supporting physical/Layout design activity, hardware bring-up and validation will be required. Knowledge and design experience of DDR3/4, PCIe, SERDES Technologies, Ethernet along with High-speed PCB design and signal integrity will be advantage. Good experience in Board Bring-up, Hardware and System level debugging Good understanding of interfaces like DDR-2/3/4, PCIe, SerDes protocols Good experience on management interface like SPI, I2C Proven experience on preparation of Functional Specifications, Production Definition and taking ownership on Documentation Hands on with the usage of design tools from Mentor Graphics and Cadence Hands on with the usage of Digital Oscilloscope, Multimeters, test and measuring equipment

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Develop the verification environment and test bench and creating testcases. Debug fails using waveform, trace tools and debug RTL code Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3 + years of experience in Functional Verification of Processors or ASICs. Minimum 2+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Multi-processor cache coherency, Memory subsystem, IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc Madhu to update ASICs specific skills Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Good object-oriented programming skills in C/C++, and any of scripting languages like Python/Perl Development experience on Linux/Unix environments and in GIT repositories and basic understanding of Continues Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in verification coverage closure Preferred technical and professional experience Verify the different functions/components in a PCI Express Controller & high speed SERDES (PHY). Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

InnoPhase Inc., DBA GreenWave Radios, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays. Based in San Diego, California, GreenWave Radios has earned a reputation for delivering power-efficient digital-to-RF solutions. Our commitment to innovation is backed by a robust team of more than 100 talented engineers spread across four R&D facilities worldwide and an extensive portfolio of over 120 global patent filings, underscoring our dedication to pushing the boundaries of radio technology. InnoPhase Inc., DBA GreenWave™ Radios and Synergic Emergence have a co-employment relationship. For over three years, GreenWave Radios has partnered with Synergic Emergence, a professional employment organization provider, to offer our employees the best benefits and services. This arrangement means that Synergic Emergence provides employee pay checks and benefits, and GreenWave Radios will provide employment, evaluation, and advancement. By outsourcing some HR functions, GreenWave Radios can focus on what we do best – developing and implementing highly innovative SOC cellular radio integrated circuit products. Job Description InnoPhase Inc., DBA GreenWave™ Radios Bangalore is looking for a Senior Engineer - Design Verification to join our fast-paced and motivated team to drive excellence in our 5G products. This role is an excellent opportunity for someone that enjoys driving the critical path and making a significant impact in launching products into the market and winning! Key Responsibilities You will be working within DV team on verifying ORAN packet processing blocks using internal developed reference Python Model. Work on high speed SERDES interface verification such as PCIE but not limited to. Develop UVM testbench environment and execute verification cases to verify RTL design in bit true and cycle accurate. Construct SoC level testbench re-using verification components developed at the IP/ Subsystem level. Test bench architecture for random/directed testing, stimulus generation, and integration of custom and off the shelf VIP/UVCs. Develop and execute verification plans based on design specifications and collaboration with architects and designers. Construct HW/SW Co-Verification environment - test-benches, use-cases, APIs, sequences. Execute and Debug use-cases. Be part of a dynamic and functionally diverse team with opportunities for gaining exposure to modelling (TLM), HW emulation/acceleration, and SW driven verification. Debug test cases and report verification result to achieve expected code/functional coverage metrics. Utilize constrained random verification, functional coverage, code coverage and assertions to achieve goals. Work with FW team to convert DV sequence to FW drivers Support emulation, FPGA, prototyping efforts. Implement and maintain automated verification flows in languages such as Python, Perl/ Shell scripts. Job Requirements Master's and/or bachelor's degree in engineering (or equivalent) in EC/ EE/ CS. 5 or more years of experience in ORAN protocol design verification using reference models. Hands-on experiences in integrating Python/C++ models to UVM environment and create Agents, Scoreboards components for network functional blocks. Experiences in Cadence vManager for DV metrics extraction and regression Good understanding of the complete verification life cycle (test plan, testbench through coverage closure). Expertise in developing testbench environment and verification components (Monitor, Scoreboard, Driver, Agent etc) from scratch. Proficient in SystemVerilog, Verilog, UVM and C; and scripting languages like Python, Perl and Tcl/Shell. Experience in developing IP/ Subsystem/ chip-level SystemVerilog and UVM based Experiences in GIT, JIRA, MS office suites Benefits: Competitive salary and stock options. Learning and development opportunities. Employer paid health Insurance. Earned, Casual, Sick & parental leaves.

Analog Mixed Signal Layout Location: Bangalore, Hyderabad, Noida Skills/Experience: Independent layout development of High Speed blocks like SerDes, Rx, Tx, , PLL, ADC, LDO, Bandgap etc Strong debug skills and good communication Experience (years) : 3 - 7 Years Education Qualification: BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or related field.

• EXP. of Analog blocks like Op-amps, BGR’s, LDO’s, PLL’s , Clocking circuits, TX / RX. • Analog circuit in PMIC domain: Design of Voltage/Current references, Amplifiers, Comparators, Filters & Voltage sensors, Oscillators, Voltage clamps. Required Candidate profile • EXP on High Speed SERDES/ Memory Circuits is PLUS • Exposure to cutting edge technology nodes like FinFets is PLUS • Hands-On atleast 2/ 3 of Blocks • Strong Analog Design Fundamentals

Job Specs : We are seeking a highly skilled and motivated Analog Circuit Designer to join the offshore development teams of our group companies. You will work with the rapidly expanding team which focuses on the research and development of Analog / Mixed Signal IPs for Silicon Lifecycle Management, driving innovation and excellence in chip design and verification. You will work alongside a talented and dedicated group of engineers, all committed to pushing the boundaries of technology and delivering top-notch solutions to our customers. Desired Profile : - Bachelor's / Master's degree in engineering from EEE / E&C with 4+ Years of work expertise in mixed-signal or CMOS circuit design- Expertise in analog blocks like power management DC-DC convertor, LDOs or- Expertise in designing ADC / DAC/ PLLs or Experience in simulation or characterization of IO cells- Design and architect CMOS analog and mixed-signal integrated circuits- Simulate designs with state-of-the-art CAD tools- Document designs and simulation results - Experience with high-speed SERDES circuits- Knowledge of layout issues- Experience with circuit simulators (HSPICE, Spectre, etc)- Experience with Cadence Design Environment is an asset- Working knowledge of PERL and UNIX shell scripting languages is an asset Work Location : Bangalore / Hubli / Kolkata / Moscow / SFO Work Expertise : 4 - 10 years Rewards and Benefits : We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. NOTE : Preferred resources holding valid regional s only Location - Bangalore,Kolkata,US,Others

Greetings from Dexcel Designs! Inviting applications for the Hardware Engineer Board Design / Circuit Design position Job Summary We are looking for a Hardware Design Engineer with 3-8 years of experience in designing embedded systems and high-performance electronics for defence, aerospace, and industrial applications . The role involves circuit design, PCB development, and system integration for platforms such as RFSoC, Agilex, Intel, TI, and AD processors/SOCs while working with industry-standard VPX, 3U, 6U, or custom form factors . Key Responsibilities Design and develop digital, analog, and power supply circuits for embedded systems. Work with high-speed and parallel interfaces including PCIe, JESD204B, Ethernet (1G/10G), USB, DDR3/DDR4, SPI, and I2C . Implement serial and parallel interfaces such as LVDS, SRIO, MIPI, and SATA/NVMe storage solutions . Develop schematics and PCB layouts , ensuring signal integrity, power integrity, and thermal efficiency . Design hardware using VPX, 3U, 6U, and custom form factors . Perform board bring-up, validation, and debugging using lab tools like oscilloscopes and logic analyzers. Ensure compliance with EMI/EMC standards, MIL-spec requirements, and ruggedized hardware designs . Collaborate with cross-functional teams including FPGA, Embedded Software, and System Engineers for seamless integration. Required Skills Strong understanding of PCB layout, power distribution, and high-speed signal design . Hands-on experience with schematic capture and PCB design tools (Allegro, Altium, or similar) . Knowledge of real-time embedded architectures and processor-based system design. Experience with board-level debugging, hardware validation, and compliance testing . Preferred Skills Experience with FPGA-based designs (Xilinx, Intel, Lattice) . Exposure to AI/ML accelerators, high-speed data converters, and RF front-end systems . Understanding of thermal management and ruggedized hardware design

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Serdes PHY Analog Design Job Function BDC SerDes Mixed-Signal design team is actively looking for experienced (4-12+ years) analog circuit designers to work on high speed SerDes PHYs . You will be directly involved in delivering next-generation custom PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-nodes - finfets & beyond. Design goals include low-power analog designs to address Qualcomm's low-power wireless products. Responsibilities Hands-on experience - Analog circuit design Experience in designing multiple analog building blocks - LDO, high speed TX and RX (Equalizer, Sampler, PI, Deserializer etc) , Bias, Reference etc. Analog and or Digital PLLs for frequency synthesis and/or SerDes applications" Charge pump, loop filter, VCO/DCO, PFD/TDC, high speed dividers. PLL Loop Dynamics, Jitter sources and modeling (RJ & DJ) Ability to take a design, perform schematic to post layout verification, integration sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Skills & Experience For lead position, candidates must have performed PHY Lead roles which include PHY integration to SOC & interaction with post silicon teams like HSIO, ATE, SVE, CE etc. Understanding of advance Finfet process effects on designs and layout is required. Experience in using SPICE simulators, adexl & virtuoso. Experience with post-Si bring-up and debug is must. Good understanding on peripheral PHYs (USBs, UFS, PCIe) protocols is added advantage. Master/Bachelor in Electronics Shell/Perl-python scripting to automate circuit design and verification work. Able to work with teams across the globe and possess good communication and presentation skills. Preferred Mixed signal design experience Keywords Analog circuit Design, Rx, Tx, PLL, SerDes, PHY, Serializer, Deserializer, VCO, High-speed Trans receiver

Senior Rust Developer Experience: 4+ years Salary : Competitive Preferred Notice Period : Within 30 Days Shift : 3:00PM to 12:00AM IST Opportunity Type: Remote Placement Type: Contractual Contract Duration: Full-Time, 03 Months (*Note: This is a requirement for one of Uplers' Partners) What do you need for this opportunity Must have skills required : Actix, Cargo, rayon, Rocket, Rust, serde, Tokio Good to have skills : NA Our Hiring Partner is Looking for: Rust Developer who is passionate about their work, eager to learn and grow, and who is committed to delivering exceptional results. If you are a team player, with a positive attitude and a desire to make a difference, then we want to hear from you. Role Overview Description About the Company Headquartered in Palo Alto, California, the company is the world's first AI-powered tech services organization. It has revolutionized the tech services industry by integrating AI into every aspect of its operationsoffering AI-vetted and matched talent, AI-driven development acceleration, and access to AI transformation experts who have played pivotal roles in building some of Silicon Valley's most iconic companies. Since its founding in 2018, the company has achieved remarkable growth, boasting a Talent Cloud of over three million developers worldwide and serving 900+ clients. Its innovative approach and impactful contributions have earned it numerous accolades, including being named one of "America's Best Startup Employers" by Forbes in 2022, securing the top spot in The Information's 2021 Annual List of most promising B2B companies, and being featured in Fast Company's "World's Most Innovative Companies" list. The companys leadership team is a blend of top-tier AI technologists from organizations like Meta, Google, Microsoft, Apple, Amazon, and Twitter, alongside seasoned consultants from prestigious firms such as Accenture, Cognizant, Capgemini, McKinsey, and Bain, as well as alumni from renowned institutions like Stanford, Caltech, and MIT. About the Role We are looking for an experienced Rust Developer to contribute to a cutting-edge project focused on evaluating AI-assisted Rust development. This role involves working on real-world Rust codebases, implementing features, debugging, refactoring, and writing comprehensive tests to ensure memory safety and correctness. Responsibilities: Navigate and modify complex Rust codebases using CLI tools like grep and ripgrep. Implement new features with a focus on memory safety, ownership rules, and type correctness. Write and execute tests using cargo test, including property-based testing (proptest or quickcheck). Refactor existing Rust code while maintaining functionality and performance. Debug and fix memory safety, ownership, and concurrency-related issues. Set up and manage Rust development environments using cargo, including handling dependencies and feature flags. Ensure best practices in Rust development, including proper error handling, concurrency safety, and efficient memory usage. Requirements: Strong experience with Rust programming language concepts, including ownership, borrowing, and lifetimes. Familiarity with Rust frameworks like Tokio, Actix, Rocket and libraries such as Serde and Rayon. Experience with Rusts testing ecosystem, including unit, integration, and property-based testing. Knowledge of multi-threading and asynchronous programming in Rust. Ability to work with complex architectural patterns and refactor code without introducing regressions. Strong debugging skills, including fixing memory and concurrency issues. Experience with performance profiling and benchmarking in Rust (cargo bench). 4+ years of work experience This role provides an opportunity to work on challenging Rust engineering problems while improving AI-assisted programming workflows. If youre passionate about Rust and eager to push the boundaries of AI-driven software development, wed love to hear from you! Nice to Have: Experience contributing to open-source Rust projects. Familiarity with writing Rust documentation and designing APIs with doc-tests. How to apply for this opportunity Register or login on our portal Click 'Apply,' upload your resume and fill in the required details. Post this click Apply Now' to submit your application. Get matched and crack a quick interview with our hiring partner. Land your global dream job and get your exciting career started! About Our Hiring Partner: The company is at the forefront of AGI infrastructure, solving the human intelligence bottleneck and empowering enterprises to harness the power of generative AItransforming complex data into actionable insights. From custom AI products to end-to-end deployment, our solutions and experts are dedicated to driving innovation and efficiency. Trusted by 1000+ companies including OpenAI, Google, and Meta. Join us in the AGI era and accelerate how businesses operate. About Uplers: Our goal is to make hiring reliable, simple, and fast. Our role will be to help all our talents find and apply for relevant opportunities and progress in their career. We will support any grievances or challenges you may face during the engagement. You will also be assigned to a dedicated Talent Success Coach during the engagement. ( Note: There are many more opportunities apart from this on the portal. Depending on the assessments you clear, you can apply for them as well). So, if you are ready for a new challenge, a great work environment, and an opportunity to take your career to the next level, don't hesitate to apply today. We are waiting for you!

Exciting Career Opportunities in Analog Design Multiple Positions Open! Open Positions: Staff Engineer, Senior Staff Engineer, Manager Key Details: Company : Leading Japanese Semiconductor Company Location : Bangalore Work Mode : Hybrid (3 days work from office) Experience : 12 to 22 years Qualification: Bachelors or Masters degree in Electrical and Computer Engineering Job Description: We are looking for professionals with expertise in: Power supply topologies: buck, boost, charge pumps, LDOs , and control architectures like voltage, current, and hysteretic mode regulation. Analog IC design with a focus on power conversion systems , using advanced design tools and methodologies. Circuit design for components like bandgap references, operational amplifiers, OTAs, bias circuits, comparators, oscillators, DACs, ADCs, level shifters, switching power stages, LDOs, charge pumps , and glue logic. If this role matches your skill set, kindly share your resume at heena.k@randstad.in Looking forward to hearing from you!