5+ years relevant experience Lead with experience in SoC Physical design across multiple technology nodes including 5nm for TSMC & Other foundries. Excellent hands-on P&R skills with expert knowledge in ICC/Innovus Expert knowledge in all aspects of PD from Synthesis to GDSII, Strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure Experience at taping out multiple chips, strong experience at the top level at the latest technology nodes. CAD, Methodology & IP team collaboration is very essential for PD implementation, must conduct regular sync-ups for deliveries. Significant knowledge and preferably hands on experience on SoC STA, Power, Physical Verification and other sign-off. Good problem-solving capabilities, proactive, hardworking with strong interpersonal skills. Bachelor's Degree in Electrical, Electronics or Computer Engineering About Compan y: 7Rays Semiconductor Private Ltd. is a provider of end to end custom SoC design solutions ranging from SoC Architecture, RTL design, Design verification, DFT, Physical Design & Analog design. We are focused on providing services to top semiconductor and system companies to help them with the design of their complex SoCs .We work closely with our clients, building effective partnerships to deliver high-quality solutions tailored to their needs. With a strong engineering team and a proven track record of successful project executions, we are committed to excellence and innovation in SoC Design, Development and deployment of customers’ products . Show more Show less
You should have at least 3+ years of relevant experience in SoC Physical design, with a focus on multiple technology nodes including 5nm for TSMC and other foundries. Your expertise should include hands-on P&R skills, particularly in ICC/Innovus. You must possess expert knowledge in all aspects of Physical Design (PD) from Synthesis to GDSII, with a strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure. Experience in taping out multiple chips and working at the top level in the latest technology nodes will be highly beneficial. Collaboration with CAD, Methodology & IP teams for PD implementation is critical, requiring regular sync-ups for deliveries. You should have significant knowledge, and preferably hands-on experience, in SoC STA, Power, Physical Verification, and other sign-off processes. Problem-solving capabilities, proactive attitude, hardworking nature, and strong interpersonal skills are essential for this role. A Bachelor's Degree in Electrical, Electronics, or Computer Engineering is required for this position. About Company: 7Rays Semiconductor Private Ltd. provides end-to-end custom SoC design solutions, including SoC Architecture, RTL design, Design verification, DFT, Physical Design & Analog design. The company focuses on offering services to top semiconductor and system companies to assist them in designing complex SoCs. The company believes in building effective partnerships with clients to deliver high-quality solutions tailored to their needs. With a dedicated engineering team and a successful track record in project execution, the company is committed to excellence and innovation in SoC Design, Development, and deployment of customers" products.,
You should have 4 to 8 years of experience in RTL to Netlist Synthesis, specifically in Genus and Design Compiler. Meeting all the DC/Genus exit criteria, including PPA meeting and constraints validation, is a basic requirement. Additionally, you must have floorplan-based synthesis knowledge like DCG, and work closely with RTL designers on constraints debug and feedback on a constant basis. Your responsibilities will include pre-layout timing analysis and reporting, post-layout timing analysis for placement, CTS & PRO, clock gating checks, and timing closure. You should also have experience in ECOs and final tapeout timing closure skills across corners and modes. Collaboration with RTL design team, PD team, and HMs team for overall timing closure for SoC is crucial. Having knowledge of Primetime and Tempus is essential, along with expertise in leakage recovery, Vmin targets, and performance versus leakage trade-off for final sign-off. Deep scripting knowledge is required, as well as soft skills for working effectively with stakeholders. About the Company: 7Rays Semiconductors (https://7rayssemi.com/) is a provider of end-to-end custom SoC design solutions, covering SoC Architecture, RTL design, Design verification, DFT, Physical Design & Analog design. The company is dedicated to assisting top semiconductor and system companies in designing their complex SoCs. At 7Rays Semiconductors, we focus on establishing strong partnerships with our clients to deliver high-quality solutions tailored to their specific needs. With a skilled engineering team and a successful track record in project execution, we prioritize excellence and innovation in SoC Design, Development, and deployment of customers" products.,
You should have at least 3+ years of relevant experience leading SoC Physical design projects across multiple technology nodes, including 5nm for TSMC and other foundries. Your expertise should include hands-on Place and Route (P&R) skills with in-depth knowledge of ICC/Innovus. You must possess expert knowledge in all phases of Physical Design (PD) from Synthesis to GDSII, with a solid background in Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure. Experience in taping out multiple chips and strong familiarity with the top level at the latest technology nodes will be beneficial. Collaboration with CAD, Methodology & IP teams is a crucial aspect of PD implementation, necessitating regular sync-ups for deliveries. You should have significant knowledge and preferably hands-on experience in SoC Static Timing Analysis (STA), Power analysis, Physical Verification, and other sign-off processes. Strong problem-solving abilities, a proactive approach, hard work ethic, and excellent interpersonal skills are essential for this role. A Bachelor's Degree in Electrical, Electronics, or Computer Engineering is required. About Company: 7Rays Semiconductor Private Ltd. provides end-to-end custom SoC design solutions, encompassing SoC Architecture, RTL design, Design verification, DFT, Physical Design, and Analog design. Our focus is on serving top semiconductor and system companies to facilitate the design of their complex SoCs. We prioritize building effective partnerships with our clients to deliver high-quality, tailored solutions. With a dedicated engineering team and a proven history of successful project execution, we are dedicated to excellence and innovation in SoC Design, Development, and deployment of customer products.,
You should have 4 to 8 years of experience in RTL to Netlist Synthesis, specifically in Genus and Design Compiler. Meeting all the DC/Genus exit criteria, including PPA meeting and constraints validation, is a basic requirement. Knowledge of floorplan-based synthesis like DCG is essential. Working closely with RTL designers on constraints debug and feedback on a constant basis is a key aspect of the role. Conducting pre-layout timing analysis and reporting out, as well as post-layout timing analysis for placement, CTS & PRO, are part of the responsibilities. You will be involved in clock gating checks, timing closure, ECOs, and final tapeout timing closure skills across corners and modes. Collaborating with the RTL design team, PD team, and HMs team for overall timing closure for SoC is crucial. Having expertise in tools like Primetime and Tempus is essential. Knowledge of leakage recovery, Vmin targets, and performance versus leakage trade-off for final sign-off is required. Deep scripting knowledge is a must, along with strong soft skills for working with stakeholders. About Company: https://7rayssemi.com/ 7Rays Semiconductors is a provider of end-to-end custom SoC design solutions, including SoC Architecture, RTL design, Design verification, DFT, Physical Design & Analog design. The company focuses on offering services to top semiconductor and system companies for the design of their complex SoCs. Collaborating closely with clients, 7Rays Semiconductors builds effective partnerships to deliver high-quality solutions tailored to their needs. With a skilled engineering team and a track record of successful project executions, the company is dedicated to excellence and innovation in SoC Design, Development, and deployment of customers" products.,
You will be responsible for designing full-custom layouts for memory components such as SRAM, ROM, CAM, Register Files, or sense amplifiers. Your role will involve working closely with circuit designers to comprehend schematics and transform them into optimized layouts. This will include tasks like floorplanning, transistor-level placement, routing, and matching to ensure compliance with electrical and physical design constraints. It will be crucial to guarantee that the layouts adhere to design rules specific to process technologies like 5nm, 7nm, 16nm, and 28nm. Additionally, you will need to implement design automation using SKILL, Python, or Tcl wherever applicable. The ideal candidate should possess experience in compiler-based memory generation or memory compilers. Familiarity with high-speed or low-power memory layout optimization techniques will be beneficial for this role. Moreover, scripting expertise in SKILL or Python for layout automation and checks is a required skill set.,
At 7Rays Semiconductors, we specialize in providing comprehensive VLSI design solutions to assist our clients in achieving excellence in execution. Our team of experts is highly skilled in various areas including architecture, RTL design, verification, validation, physical design, implementation, and post-silicon validation. We utilize the latest technologies and methodologies to deliver top-notch solutions tailored to meet our clients" specific needs. As a Design Verification Engineer specialized in protocols such as PCIe, CXL, and UCIE, you will be responsible for: - Demonstrating expertise in interconnect protocols such as PCIe, CXL, and UCIE. - Having a solid understanding of AXI/ACE/CHI protocols, with a particular emphasis on AXI. - Knowledge of DMA usage and its applications. - Strong proficiency in SystemVerilog (SV) and Universal Verification Methodology (UVM). - Experience in utilizing standard Verification IP (VIP) in Testbenches, preferably Synopsys tools. - Familiarity with AI/ML network concepts is considered beneficial. - Additional proficiency in perl/tcl scripting would be advantageous. The ideal candidate for this role should possess a Bachelor's Degree in Electrical, Electronics, or Computer Engineering, along with 5-12 years of relevant experience. If you are passionate about semiconductor design, eager to work in a collaborative environment, and committed to delivering high-quality solutions, we would love to hear from you.,
You will be joining 7Rays Semiconductors, a company that specializes in providing end-to-end VLSI design solutions to help clients achieve execution excellence. The team of experts at 7Rays Semiconductors focuses on architecture, RTL design, verification, validation, physical design, implementation, and post-silicon validation using cutting-edge technologies and methodologies. Building effective partnerships with clients, the company delivers high-quality solutions tailored to meet specific needs, showcasing a commitment to excellence and innovation in semiconductor design. Located in Bangalore, KA, this opportunity requires a minimum of 5 years of experience in the Emulation domain. As an Emulation Engineer/Validation Engineer, your responsibilities will include building emulation models from RTL for IP/SS or SOC, bringing up emulation models, developing content, and collaborating with RTL designers and Verification engineers to resolve emulation build issues. You will also work closely with customers to address emulation challenges and partner with vendors to resolve emulation build issues. Ideal candidates should hold a B.Tech/M.Tech in Electronics/VLSI or equivalent and be familiar with SV/UVM methodology. Candidates should have hands-on experience with Emulators such as Palladium, Veloce, Zebu, etc., and demonstrate proficiency in porting ASIC RTL on the Emulators and generating Emulation builds. Additionally, expertise in domains/functions including AXI, APB, AHB, SPI, I2C, UART, PCIe, USB, Ethernet, CXL, Ucie, C2C, D2D, DDR4/5/6, LPDDR3/4/5/6, and NoC/Interconnect verification is required. Desired activities that candidates should be involved in are HW-SW co-verification, Boot, Reset, Clock verification, Low Power Verification, Regression management and debug, as well as the development of Scoreboard, Checkers, and tracker. Proficiency in scripting languages like PERL and PYTHON is also beneficial for this role.,
You are an experienced Design-for-Test (DFT) Engineer with over 5 years of hands-on expertise in DFT methodologies and implementation. You should possess a solid understanding of MBIST, Scan, ATPG, and simulation concepts, along with a proven track record of executing industry-standard DFT flows. Your key responsibilities will include performing MBIST insertion, Scan insertion, and ATPG pattern generation using industry-standard EDA tools. You will be conducting MBIST simulations and analyzing results using tools from Cadence, Siemens Tessent, or Synopsys. Additionally, you will execute zero delay and SDF-based timing simulations, and efficiently debug issues using simulators such as VCS, NCSim, or Xcelium in GUI mode. Working with fault models including Stuck-at Faults and Transition Delay Faults (TDF) will be part of your role. You will also be responsible for optimizing and improving scan test coverage using established DFT techniques. The required skills and experience for this position include 5+ years of relevant experience in DFT, hands-on expertise with tools from Cadence, Siemens Tessent, and Synopsys, proficiency in debugging and analysis using VCS, NCSim, or Xcelium, strong analytical and problem-solving skills, and good communication and collaboration skills. Preferred qualifications for this role include experience in DFT automation using scripting languages like TCL, Perl, or Python, and prior exposure to automotive, networking, or high-performance computing SoCs is considered a plus.,
As a Physical Design Engineer based in Bangalore, India with over 3 years of experience, you will be responsible for various aspects of physical design for SoC using Innovus. Your key responsibilities will include floorplanning, IO ring creation, understanding ESD and latch-up requirements for foundry, and implementation strategies for placement. You will need to demonstrate expertise in hierarchical design implementation, including partitioning, push down methodologies, core/tile PG creation, and knowledge of analog components placement based on design specifications. Additionally, RDL knowledge and experience working with packaging are essential for SoC floorplan design. A critical aspect of your role will involve PV clean-up on the floorplan and ensuring compliance with Physical Verification, ESD, foundry, and analog requirements. Deep scripting knowledge is a prerequisite for this position, along with strong problem-solving capabilities, proactive attitude, hardworking nature, and excellent interpersonal skills. To qualify for this role, you must hold a Bachelor's Degree in Electrical, Electronics, or Computer Engineering. If you are looking to leverage your experience and skills in physical design within a dynamic and innovative environment, this opportunity is tailored for you.,
As a CPU Physical Design Lead at 7Rays Semiconductors, you will be responsible for the development of high-speed cores such as CPU, GPU, and DDR. With over 10 years of experience, you must possess significant knowledge in synthesis, constraints, and physical design, keeping power, performance, and area (PPA) in mind throughout the process. Collaboration with RTL designers for optimizations and feedback will be a key part of your role, ensuring efficient floorplanning for multi-core, L2 & L3, and power planning up to Bumps. Your expertise in silicon margins, VT trade-off, power, and area impact will be vital in making informed decisions. Understanding critical paths, pipelining, latency, and implementing super buffers will be within your scope, contributing to the overall efficiency and performance of the designs. Additionally, having knowledge in low power implementation will be considered an advantage in this position. At 7Rays Semiconductors, we specialize in providing custom SoC design solutions to top semiconductor and system companies. Working closely with our clients, we aim to build effective partnerships and deliver high-quality solutions tailored to their specific needs. With a dedicated engineering team and a successful track record in project executions, we are committed to excellence and innovation in SoC design, development, and deployment to support our customers" product goals.,