20 Scan Jobs

The DFX Verification Lead position is located in Bangalore and requires 4 to 8 years of experience. The ideal candidate should have a strong understanding of DFT requirements such as Scan, BIST, and JTAG Debuggers. In this role, you will collaborate with IP and integration teams to ensure the successful implementation and verification of design elements. Your responsibilities will include working closely with designers and verification engineers to guarantee functionality and design features for future projects. To excel in this role, you must have a deep knowledge of verification flows and be proficient in debugging at both SoC and system levels. Additionally, expertise in Verilog, System Verilog, or System C for test-bench/model development is required. If you are passionate about chip design and semiconductor projects, we invite you to apply for this exciting opportunity. To express your interest, please submit your resume to krishnaprasath.s@acldgitial.com.,

As a Design Manager at Texas Instruments, you will have the opportunity to lead a team of RTL front end, Digital Back end & Design verification engineers. Your primary responsibilities will include directing and guiding the activities of a research or technical design function, overseeing the design, development, modification, and evaluation of digital electronic parts, components, or integrated circuitry for electronic equipment and hardware systems. You will evaluate the final results of research and development projects to ensure the accomplishment of technical objectives. Additionally, you will be involved in preparing and presenting reports outlining the outcomes of technical projects and making recommendations for actions necessary to achieve desired results. In this role, you will play a key part in selecting, developing, and evaluating personnel to ensure the efficient operation of the function. Joining Texas Instruments as a Design Manager (RTL, P&R, Design Verification) will allow you to work with a team of enthusiastic engineers focused on developing highly complex and industry-leading devices for audio applications. You will be involved in developing new Audio converters catering to PE, Automotive, and Industrial market segments, with the digital content including a DSP for digital filters and audio signal processing blocks among various other IPs. Collaboration with various engineering teams within the product line, including analog design, layout, firmware, verification, validation, test, systems, applications, and marketing, will be a part of your role to successfully execute new products from concept to volume production and subsequent support. As a core member of the design team, you will drive flawless execution by finding innovative design architecture and solutions through out-of-the-box thinking to deliver highly differentiated products. This is an exceptional opportunity to be part of a team that is continuously seeking growth opportunities, working with leading customers globally, and developing cutting-edge solutions in consumer electronics, industrial, and automotive markets. To qualify for this position, you must hold a minimum bachelor's degree in electrical engineering and have at least 7 years of experience. Strong aptitude, hands-on experience in RTL frontend design, excellent command of RTL design concepts, and the ability to work with dynamically evolving requirements are some of the key qualifications needed for this role. You should also possess a result-driven attitude, the ability to mentor team members, and familiarity with digital backend flow and design verification flow. Preferred qualifications for this role include establishing strong relationships with key stakeholders, strong verbal and written communication skills, hands-on experience with Digital Back end tools, and the ability to quickly ramp up on new systems and processes. Demonstrated interpersonal, analytical, and problem-solving skills, ability to collaborate effectively with cross-functional teams, and strong time management skills are also desirable qualities for this position. As a Design Manager at Texas Instruments, you will be responsible for leading a team of 7+ engineers and multiple contractors, driving results while striving for excellence in the complete Digital (Front and Backend) & Design verification team. Your role will also involve overseeing the career growth of your team members. If you are passionate about engineering and shaping the future of electronics, Texas Instruments offers a collaborative environment where employees are empowered to own their career and development. Join us to work with some of the smartest people in the industry and contribute to creating a better world through affordable semiconductor technology. Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company dedicated to designing, manufacturing, and selling analog and embedded processing chips for various markets. Our core passion is to make electronics more affordable through innovative semiconductor solutions. We value diversity and inclusion in our work environment and strive to empower our employees to drive innovation forward. At Texas Instruments, we believe in creating a diverse, inclusive work environment and are an equal opportunity employer. If you are interested in this position, please apply to this requisition.,

KEY RESPONSIBILITIES: Implementation and verification of DFT features likeSCAN, MBIST, LBIST and JTAG SupportSpyglass-DFTDRC debug and coverage correlation Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning PREFERRED EXPERIENCE: Experience in scan-stitching; and has good knowledge of scan-stitching related concepts Exposure to MBIST/BISR implementation and with the Tessent flow of mbist-insertion Excellent hands-on ATPG; and is we'll conversed with the files required to run ATPG Knowledge/experience with Tessent ATPG (mentor) is a plus Knowledge on Spyglass-DFT Excellent hands-on debug skills and scripting skills are critical Knowledge on automation scripts like TCL/AWK/SED is a plus Understands the basics of JTAG Experience with post-silicon bring up is a plus ACADEMIC CREDENTIALS: Bachelors degree w/7+ years or Masters degree w/5+ years in Electronics engineering/Electrical Engineering

The Common Hardware Group (CHG) at Cisco is responsible for delivering silicon, optics, and hardware platforms for core Switching, Routing, and Wireless products. As a part of this team, you will contribute to designing networking hardware for Enterprises, Service Providers, the Public Sector, and Non-Profit Organizations globally. Cisco Silicon One is a groundbreaking silicon architecture that allows customers to utilize top-of-the-line silicon in various network environments. Join us in shaping innovative solutions by working on the design, development, and testing of complex ASICs. In this role, you will collaborate with the team on Verilog RTL and scripted flow implementation of Hardware Design-for-Test (DFT) features to support ATE, in-system test, debug, and diagnostics requirements. You will also be involved in Verilog testbench implementation for verification tests and automation scripts to enhance implementation quality and efficiency. **Minimum Qualifications:** - Bachelor's or Master's Degree in Electrical or Computer Engineering with a minimum of 2 years of experience. - Proficiency in DFT, test, and silicon engineering trends. - Familiarity with JTAG protocols, Scan and BIST architectures, ATPG, and EDA tools. - Verification skills in System Verilog Logic Equivalency checking and Test-timing validation. **Preferred Qualifications:** - Understanding of VLSI circuit physical behaviors in silicon. - Knowledge of timing concepts and EDA tools usage. - Strong verbal communication skills and adaptability in a dynamic environment. - Proficiency in scripting/coding languages such as Tcl, Python, Perl, or C/C++. Cisco is committed to embracing diversity, fostering innovation, and driving digital transformation. With a focus on inclusive teamwork and a culture of creativity, we encourage individuality and support continuous learning and growth. At Cisco, we value accountability, boldness, and diversity of thought. Join us in our journey to create a future where technology drives positive change and equality for all.,

The Common Hardware Group (CHG) at Cisco is responsible for delivering silicon, optics, and hardware platforms for the core Switching, Routing, and Wireless products. We design networking hardware for Enterprises, Service Providers, the Public Sector, and Non-Profit Organizations worldwide. Cisco Silicon One is a unique silicon architecture that allows customers to utilize top-of-the-line silicon in TOR switches, web-scale data centers, and across various networks with a unified routing and switching portfolio. Join our team and contribute to shaping Cisco's innovative solutions by participating in the design, development, and testing of cutting-edge ASICs. As a member of our team, you will be involved in the Verilog RTL and scripted flow implementation of Hardware Design-for-Test (DFT) features supporting ATE, in-system test, debug, and diagnostics requirements. Additionally, you will collaborate on Verilog testbench implementation for verification tests related to DFT features and use cases. Your role will also include contributing to automation scripts aimed at enhancing implementation quality and efficiency. **Minimum Qualifications:** - Bachelor's or Master's Degree in Electrical or Computer Engineering with a minimum of 2 years of experience - Knowledge of the latest trends in DFT, test, and silicon engineering - Proficiency in JTAG protocols, Scan and BIST architectures, including memory BIST and boundary scan - Familiarity with ATPG and EDA tools such as TestMax, Tetramax, Tessent tool sets, and PrimeTime - Verification skills encompass System Verilog Logic Equivalency checking and validating the Test-timing of designs **Preferred Qualifications:** - Understanding of VLSI circuit physical behaviors in silicon, including electrical migration and temperature/voltage effects - Knowledge of basic timing concepts like setup and hold, metastability - Experience with EDA tools - Strong verbal communication skills and ability to excel in a dynamic environment - Proficiency in scripting/coding languages like Tcl, Python, Perl, or C/C++ Cisco is a diverse and inclusive environment where individuality is celebrated, and collaborative teamwork drives meaningful change for an inclusive future. Embracing digital transformation, we assist our customers in implementing digital changes in their businesses, showcasing our expertise as both a hardware and software company. Our innovative network solutions adapt, predict, learn, and protect, setting us apart as a company that defies traditional categorization. At Cisco, we value accountability, boldness, and diversity of thought. We foster a culture of innovation, creativity, and learning from failures, all while promoting equality for all individuals. Our inclusive environment encourages employees to be themselves, whether it's through unique personal styles or a passion for technology and positive change. Join us at Cisco, where your individuality and dedication to excellence are celebrated.,

We are seeking a highly experienced Senior DFT Engineer with 8+ years of hands-on expertise in developing and implementing DFT architectures for complex SoCs. The ideal candidate should have a solid background in scan insertion, ATPG, BIST, and silicon debug. Key Responsibilities: Define and implement DFT architecture for digital and mixed-signal SoCs Perform scan insertion, boundary scan, and ATPG pattern generation Integrate Memory BIST (MBIST) and Logic BIST (LBIST) Drive DFT verification and post-silicon validation/debug Collaborate with RTL, synthesis, STA, and backend teams to ensure testability Ensure high test coverage, test time optimization, and compliance with ATE requirements Requirements: 8+ years of experience in DFT implementation and verification Hands-on experience with tools like Tetramax, TestMax, Fastscan, or MBISTArchitect Strong understanding of scan/ATPG, JTAG, BIST, and IEEE 1149.x standards Experience in silicon bring-up, failure analysis, and debug Familiarity with industry-standard flows and ATE constraints Excellent problem-solving and team collaboration skills How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future of DFT.

You will be expected to independently execute mid-sized customer projects in the field of VLSI Frontend, Backend, or Analog design with minimal supervision. As an individual contributor, you will own a specific task related to RTL Design/Module and provide support and guidance to engineers in various areas such as Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. Your role will involve anticipating, diagnosing, and resolving problems while coordinating with cross-functional teams as necessary. It is essential to ensure on-time quality delivery that meets the approval of the project manager and the client. Additionally, you will be responsible for automating design tasks flows, writing scripts to generate reports, and proposing innovative ideas to reduce design cycle time and cost, which should be accepted by UST Manager and the client. Your performance will be measured based on the quality of deliverables, timely delivery, reduction in cycle time and cost through innovative approaches, the number of papers published, the number of patents filed, and the number of mandatory trainings attended. You should aim to deliver high-quality work by ensuring zero bugs in the design/circuit design, clean delivery of the design/module for easy integration at the top level, meeting functional specifications/design guidelines without any deviation, and documenting tasks and work performed. Timely delivery is crucial, and you must adhere to project timelines, deliver intermediate tasks to support team progress, and seek help and support if there are delays in task delivery. Continuous skills development is encouraged through participation in training sessions, upskilling in newer technologies, and taking on new areas of project development to enhance your knowledge and deliver results. Teamwork is essential, and you should actively participate, support team members when needed, take on additional tasks in the absence of team members, and assist junior team members in understanding project tasks. Going beyond the call of duty to meet deadlines and maintain quality standards is expected. Innovation and creativity are valued, and you should automate tasks to save design cycle time, participate in technical discussions, training forums, and contribute to white papers. Your skills should include proficiency in languages and programming such as System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, and Makefile. Experience with EDA tools like Cadence, Synopsys, Mentor tool sets, simulators, and various technical knowledge areas is required. Strong communication, analytical reasoning, problem-solving skills, attention to detail, and the ability to deliver tasks on time are essential. You should be well-versed in EDA tools, have the necessary technical skills, and be willing to learn new skills as required for project execution. Knowledge of project execution in various design areas, understanding design flow and methodologies, and the ability to execute project tasks as per known skills are key. Specific experience in DFT ATPG, Mbist, and SCAN is preferred, along with expertise in SOC or Subsystems designs, DFT methodologies, and standard DFT tools. Familiarity with SoC style DFT architectures, low power design practices, test mode timing constraint development, and analysis will be beneficial. Hands-on experience in ATPG, SCAN, MBIST, JTAG implementation, and knowledge of test compression and ATE debug are valuable assets. Your role will involve utilizing your skills and knowledge to contribute effectively to project success.,

MD/DNB/DMRD Radiology Consultant with the relevant Exp. (any), procedures & knowledge of CT/USG in a corporate chain of path labs in different parts of Mumbai, Pune & Thane @ best CTC subject to Exp. Shruti (HRM) T: 9819454343 E: cv@sarajobs.com Perks and benefits Family Accommodation may get subject to Location

The role involves independently executing mid-sized customer projects in the field of VLSI Frontend, Backend, or Analog design with minimal supervision. As an individual contributor, you will be responsible for owning a task in RTL Design/Module and providing support and guidance to engineers in various areas like Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. You will need to anticipate, diagnose, and resolve problems by coordinating with cross-functional teams, ensuring on-time quality delivery approved by the project manager and client. One of the key aspects of the role is to automate design tasks flows and write scripts to generate reports while also coming up with innovative ideas to reduce design cycle time and cost, which should be accepted by the UST Manager and client. Measures of success will include quality verification, timely delivery, reduction in cycle time cost through innovative approaches, number of papers published, number of patents filed, and attending mandatory trainings to meet training goals. The expected outputs include ensuring zero bugs in the design, clean delivery of the design/module for easy integration at the top level, meeting functional specifications and design guidelines without deviation, and documenting tasks and work performed. Timely delivery is crucial, meeting project timelines set by the client or program manager, delivering intermediate tasks to enable team progress, and seeking help and support in case of task delays. Continuous skill development is encouraged through participation in training, skilling others, acquiring new technologies, and taking up new areas of project development. Teamwork is essential, involving participation in team activities, supporting team members, taking up additional tasks when needed, and mentoring junior team members. Innovation and creativity are valued, with a focus on automating tasks to save design cycle time, participating in technical discussions, training, forums, white papers, etc. Skills required include proficiency in languages like System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, and EDA tools like Cadence, Synopsys, Mentor tool sets, simulators, and technical knowledge in IP Spec, Bus Protocols, Physical Design, Synthesis, DFT, etc. Strong communication, analytical reasoning, problem-solving skills, attention to detail, ability to understand specs and functional documents, and deliver tasks on time with quality are essential. Familiarity with EDA tools, willingness to learn new skills, and prior design knowledge are also necessary for successful project execution. Experience in DFT ATPG, Mbist, SCAN, and knowledge of SOC or Subsystems designs, DFT methodologies, low power design practices, scan methodologies, ATPG, MBIST, JTAG implementation, and test mode timing constraint development will be advantageous for the role.,

As a member of the Common Hardware Group (CHG) at Cisco, you will be part of a team that delivers cutting-edge silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. Our work involves designing networking hardware for Enterprises, Service Providers, Public Sector, and Non-Profit Organizations worldwide. Join us in shaping Cisco's groundbreaking solutions by participating in the design, development, and testing of advanced ASICs that are at the forefront of the industry. Your role will involve implementing Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug, and diagnostics requirements of the designs. You will collaborate with multi-functional teams to develop innovative DFT IP and play a crucial role in integrating testability features in the RTL. Working closely with design and PD teams, you will ensure the seamless integration and validation of test logic throughout all phases of implementation and post-silicon validation flows. Your team will contribute to the creation of innovative Hardware DFT and physical design aspects for new silicon device models, bare die, and stacked die. You will drive re-usable test and debug strategies while showcasing your ability to craft solutions and debug with minimal mentorship. To excel in this role, you are required to have a Bachelor's or Master's Degree in Electrical or Computer Engineering along with a minimum of 10 years of relevant experience. Your expertise should encompass knowledge of the latest trends in DFT, test, and silicon engineering. Proficiency in Jtag protocols, Scan and BIST architectures, ATPG, EDA tools, and verification skills like System Verilog Logic Equivalency checking will be essential. Preferred qualifications include experience in Verilog design, DFT CAD development, Test Static Timing Analysis, and Post-silicon validation using DFT patterns. Your background in developing custom DFT logic and IP integration, familiarity with functional verification, and scripting skills like Tcl, Python, or Perl will be advantageous. At Cisco, we value diversity, innovation, and collaboration. We empower our employees to bring their unique talents to work, driving positive change and powering an inclusive future for all. As a company that embraces digital transformation, we encourage creativity, innovation, and a culture that supports learning and growth. Join us at Cisco, where every individual is valued for their contributions, and together, we make a difference in the world of technology and networking.,

Who We Are The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With ~2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Who You'll Work With You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in Bangalore India with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL. Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows. Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies. The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship. Who You Are You are an ASIC Design for Test Hardware Engineer with 10+ years of related work experience with a broad mix of technologies. Minimum Qualifications: Bachelor's or a Masters Degree in Electrical or Computer Engineering required with at least 10 years of experience. Knowledge of the latest innovative trends in DFT, test and silicon engineering. Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design Knowledge of the latest innovative trends in DFT, test and silicon engineering. Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Experience working with Gate level simulation, debugging with VCS and other simulators. Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687 Strong verbal skills and ability to thrive in a multifaceted environment Scripting skills: Tcl, Python/Perl. Preferred Skills: Verilog design experience developing custom DFT logic & IP integration; familiarity with functional verification DFT CAD development Test Architecture, Methodology and Infrastructure Test Static Timing Analysis Post silicon validation using DFT patterns. Why Cisco #WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference powering an inclusive future for all. We embrace digital, and help our customers implement change in their digital businesses. Some may think were "old" (36 years strong) and only about hardware, but were also a software company. And a security company. We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do - you cant put us in a box! But "Digital Transformation" is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it). Day to day, we focus on the give and take. We give our best, give our egos a break, and give of ourselves (because giving back is built into our DNA.) We take accountability, bold steps, and take difference to heart. Because without diversity of thought and a dedication to equality for all, there is no moving forward. So, you have colorful hair Dont care. Tattoos Show off your ink. Like polka dots Thats cool. Pop culture geek Many of us are. Passion for technology and world changing Be you, with us!,

• Should have worked hands-on extensively on full chip DFT design, • implementation, vector generation/verification, JTAG, Boundary scan & Simulation. • Experience with Scan, Compression, ATPG & Simulations with Mentor/Synopsys/ Cadence tools. Required Candidate profile • Participated in Successful Tapeouts of SoC/ASIC chips at 14nm or below. • Develop/Automate flows & scripts in Perl/Tcl to enhance the DFT methodologies & process. • Logic BIST knowledge is a plus.

As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world-class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Key Responsibilities & Expertise Minimum of 3+ years experience in the area of DFT (Design-for-Test) , including ATPG (Automatic Test Pattern Generation), Scan Insertion, MBIST (Memory Built-In Self-Test), JTAG . In-depth knowledge of DFT concepts . In-depth knowledge and hands-on experience in DFT (scan/MBIST) insertion, ATPG pattern generation/verification, MBIST verification, and post-silicon bring-up/yield analysis . Expertise in test mode timing constraints definition , knowledge in providing timing fixes/corrective actions for timing violations. Ability to analyze and devise new tests for new technologies/custom RAM design/RMA (Return Material Authorization) etc. Expertise in scripting languages such as Perl, Shell, etc. Experience in simulating test vectors . Knowledge of equivalence check and RTL lint tool (like Spyglass). Ability to work in an international team, dynamic environment. Ability to learn and adapt to new tools and methodologies. Ability to do multi-tasking & work on several high priority designs in parallel. Excellent problem-solving skills. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Like Requirements: 5 to 10 years of hands-on experience in DFT methodologies , with expertise in Scan & ATPG, MBIST Strong knowledge of DFT tools such as Synopsys, Mentor Graphics, or Cadence. Experience in fault modeling, pattern generation, and coverage analysis . Proficiency in scripting (TCL, Python, Perl, or Shell) for automation. Excellent problem-solving skills and ability to work in a fast-paced environment. Job Responsibilities: Implement and validate DFT architectures for complex SoCs. Perform scan insertion and ensure proper integration into the design. Develop and optimize ATPG patterns to achieve high fault coverage. Work closely with RTL, verification, and physical design teams to resolve DFT-related issues. Support post-silicon bring-up, debug, and ATE (Automated Test Equipment) testing.

Job Title: Ab Initio Developer Location: Gurugram Experience: 4-5 years Employment Type: Full Time Job Summary: We are seeking an experienced Ab Initio Developer to design, develop, and maintain high-volume, enterprise-grade ETL solutions for our data warehouse environment. The ideal candidate will have strong technical expertise in Ab Initio components, SQL, UNIX scripting, and the ability to work collaboratively with both business and technical teams to deliver robust data integration solutions. Key Responsibilities: Analyze, design, implement, and maintain large-scale, multi-terabyte data warehouse ETL applications that operate 24/7 with high performance and reliability. Develop logical and physical data models to support data warehousing and business intelligence initiatives. Lead and participate in complex ETL development projects using Ab Initio, ensuring quality and efficiency. Translate business requirements into system and data flows, mappings, and transformation logic. Create detailed design documentation, including high-level (HLD) and low-level design (LLD) specifications. Conduct design reviews, capture feedback, and facilitate additional sessions as required. Develop, test, and deploy ETL workflows using Ab Initio components such as Rollup, Scan, Join, Partition, Gather, Merge, Interleave, Lookup, etc. Perform SQL database programming and optimize SQL queries for performance. Develop and maintain UNIX shell scripts to automate ETL workflows and system processes. Collaborate with Release Management, Configuration Management, Quality Assurance, Architecture, Database Support, and other development teams. Ensure adherence to source control standards using EME or similar tools. Provide ongoing support and maintenance of ETL processes and troubleshoot issues as needed. Required Skills & Qualifications: Hands-on development experience with Ab Initio components (Rollup, Scan, Join, Partition by key, Round Robin, Gather, Merge, Interleave, Lookup, etc.) Strong background in designing and delivering complex, large-volume data warehouse applications Experience with source-code control tools such as EME Proficient in SQL database programming, including query optimization and performance tuning Good working knowledge of UNIX scripting and Oracle SQL/PL-SQL Strong technical expertise in preparing detailed design documents (HLD, LLD) and unit testing Ability to understand and communicate effectively with both business and technical stakeholders Strong problem-solving skills and attention to detail Ability to work independently as well as part of a team

Job Title: Ab Initio Developer Location: Gurugram Experience: 4-5 years Employment Type: Full Time Job Summary: We are seeking an experienced Ab Initio Developer to design, develop, and maintain high-volume, enterprise-grade ETL solutions for our data warehouse environment. The ideal candidate will have strong technical expertise in Ab Initio components, SQL, UNIX scripting, and the ability to work collaboratively with both business and technical teams to deliver robust data integration solutions. Key Responsibilities: Analyze, design, implement, and maintain large-scale, multi-terabyte data warehouse ETL applications that operate 24/7 with high performance and reliability. Develop logical and physical data models to support data warehousing and business intelligence initiatives. Lead and participate in complex ETL development projects using Ab Initio, ensuring quality and efficiency. Translate business requirements into system and data flows, mappings, and transformation logic. Create detailed design documentation, including high-level (HLD) and low-level design (LLD) specifications. Conduct design reviews, capture feedback, and facilitate additional sessions as required. Develop, test, and deploy ETL workflows using Ab Initio components such as Rollup, Scan, Join, Partition, Gather, Merge, Interleave, Lookup, etc. Perform SQL database programming and optimize SQL queries for performance. Develop and maintain UNIX shell scripts to automate ETL workflows and system processes. Collaborate with Release Management, Configuration Management, Quality Assurance, Architecture, Database Support, and other development teams. Ensure adherence to source control standards using EME or similar tools. Provide ongoing support and maintenance of ETL processes and troubleshoot issues as needed. Skills and Qualifications 4-5 years of experience in Ab Initio development. Ab Initio: Proficient in using Ab Initio tools, such as GDE and Enterprise Metadata Environment (EME). ETL Concepts: Understanding of ETL processes, data transformations, and data warehousing. SQL: Knowledge of SQL for data retrieval and manipulation. Unix/Linux Shell Scripting: Familiarity with Unix/Linux shell scripting for automation and scripting tasks. Problem-Solving: Ability to identify and solve technical issues related to Ab Initio application

Roles & Responsibilities: Analyze, design, implement and maintain high volume, multi-terabyte 24/7 data warehouse robust and fast ETL applications Develop logical and physical data models; advanced ETL development using Ab Initio Be a technical player on complex ETL development projects with multiple team members Develop relevant functional and technical documentation. Lead, design and develop data warehouse solutions using different architecture, design and modeling techniques Work with business users to translate requirements into system flows, data flows, data mappings etc., and develop solutions to complex business problems. Lead the creation of all design review artifacts during project design phase, facilitate design reviews, capture review feedback and schedule additional detailed design sessions as necessary. Interact with Release Management, Configuration Management, Quality Assurance, Architecture Support Database Support, other Development teams and Operations as required

Revit Modeling & Detailing, Family creation, Report generation. Modeling & Coordination: Develop and manage detailed 3D/4D/5D BIM models for architecture, structure, and MEP systems. Ensure models are compliant with project BIM standards, LOD requirements, and naming conventions. Perform clash detection and coordinate across disciplines using tools like Navisworks or Revit. Documentation & Drawings: Generate and update construction drawings, shop drawings, and as-built documentation from BIM models. Support the creation of BOQs, schedules, and quantity take-offs using BIM data. Project Collaboration: Collaborate with architects, structural engineers, MEP consultants, and contractors for model inputs and updates. Participate in BIM coordination meetings and communicate design/modeling changes effectively

MD/DNB/DMRD Radiology Consultant with the relevant Exp. (any), procedures & knowledge of CT/USG in a corporate chain of path labs in different parts of Mumbai, Pune & Thane @ best CTC subject to Exp. Shruti (HRM) T: 9819454343 E: cv@sarajobs.com Perks and benefits Family Accommodation may get subject to Location

• Should have worked hands-on extensively on full chip DFT design, • implementation, vector generation/verification, JTAG, Boundary scan & Simulation. • Experience with Scan, Compression, ATPG & Simulations with Mentor/Synopsys/ Cadence tools. Required Candidate profile • Participated in Successful Tapeouts of SoC/ASIC chips at 14nm or below. • Develop/Automate flows & scripts in Perl/Tcl to enhance the DFT methodologies & process. • Logic BIST knowledge is a plus.