16 Scan Jobs

Job Title: Ab Initio Developer Location: Gurugram Experience: 4-5 years Employment Type: Full Time Job Summary: We are seeking an experienced Ab Initio Developer to design, develop, and maintain high-volume, enterprise-grade ETL solutions for our data warehouse environment. The ideal candidate will have strong technical expertise in Ab Initio components, SQL, UNIX scripting, and the ability to work collaboratively with both business and technical teams to deliver robust data integration solutions. Key Responsibilities: Analyze, design, implement, and maintain large-scale, multi-terabyte data warehouse ETL applications that operate 24/7 with high performance and reliability. Develop logical and physical data models to support data warehousing and business intelligence initiatives. Lead and participate in complex ETL development projects using Ab Initio, ensuring quality and efficiency. Translate business requirements into system and data flows, mappings, and transformation logic. Create detailed design documentation, including high-level (HLD) and low-level design (LLD) specifications. Conduct design reviews, capture feedback, and facilitate additional sessions as required. Develop, test, and deploy ETL workflows using Ab Initio components such as Rollup, Scan, Join, Partition, Gather, Merge, Interleave, Lookup, etc. Perform SQL database programming and optimize SQL queries for performance. Develop and maintain UNIX shell scripts to automate ETL workflows and system processes. Collaborate with Release Management, Configuration Management, Quality Assurance, Architecture, Database Support, and other development teams. Ensure adherence to source control standards using EME or similar tools. Provide ongoing support and maintenance of ETL processes and troubleshoot issues as needed. Required Skills & Qualifications: Hands-on development experience with Ab Initio components (Rollup, Scan, Join, Partition by key, Round Robin, Gather, Merge, Interleave, Lookup, etc.) Strong background in designing and delivering complex, large-volume data warehouse applications Experience with source-code control tools such as EME Proficient in SQL database programming, including query optimization and performance tuning Good working knowledge of UNIX scripting and Oracle SQL/PL-SQL Strong technical expertise in preparing detailed design documents (HLD, LLD) and unit testing Ability to understand and communicate effectively with both business and technical stakeholders Strong problem-solving skills and attention to detail Ability to work independently as well as part of a team

Job Title: Ab Initio Developer Location: Gurugram Experience: 4-5 years Employment Type: Full Time Job Summary: We are seeking an experienced Ab Initio Developer to design, develop, and maintain high-volume, enterprise-grade ETL solutions for our data warehouse environment. The ideal candidate will have strong technical expertise in Ab Initio components, SQL, UNIX scripting, and the ability to work collaboratively with both business and technical teams to deliver robust data integration solutions. Key Responsibilities: Analyze, design, implement, and maintain large-scale, multi-terabyte data warehouse ETL applications that operate 24/7 with high performance and reliability. Develop logical and physical data models to support data warehousing and business intelligence initiatives. Lead and participate in complex ETL development projects using Ab Initio, ensuring quality and efficiency. Translate business requirements into system and data flows, mappings, and transformation logic. Create detailed design documentation, including high-level (HLD) and low-level design (LLD) specifications. Conduct design reviews, capture feedback, and facilitate additional sessions as required. Develop, test, and deploy ETL workflows using Ab Initio components such as Rollup, Scan, Join, Partition, Gather, Merge, Interleave, Lookup, etc. Perform SQL database programming and optimize SQL queries for performance. Develop and maintain UNIX shell scripts to automate ETL workflows and system processes. Collaborate with Release Management, Configuration Management, Quality Assurance, Architecture, Database Support, and other development teams. Ensure adherence to source control standards using EME or similar tools. Provide ongoing support and maintenance of ETL processes and troubleshoot issues as needed. Skills and Qualifications 4-5 years of experience in Ab Initio development. Ab Initio: Proficient in using Ab Initio tools, such as GDE and Enterprise Metadata Environment (EME). ETL Concepts: Understanding of ETL processes, data transformations, and data warehousing. SQL: Knowledge of SQL for data retrieval and manipulation. Unix/Linux Shell Scripting: Familiarity with Unix/Linux shell scripting for automation and scripting tasks. Problem-Solving: Ability to identify and solve technical issues related to Ab Initio application

Roles & Responsibilities: Analyze, design, implement and maintain high volume, multi-terabyte 24/7 data warehouse robust and fast ETL applications Develop logical and physical data models; advanced ETL development using Ab Initio Be a technical player on complex ETL development projects with multiple team members Develop relevant functional and technical documentation. Lead, design and develop data warehouse solutions using different architecture, design and modeling techniques Work with business users to translate requirements into system flows, data flows, data mappings etc., and develop solutions to complex business problems. Lead the creation of all design review artifacts during project design phase, facilitate design reviews, capture review feedback and schedule additional detailed design sessions as necessary. Interact with Release Management, Configuration Management, Quality Assurance, Architecture Support Database Support, other Development teams and Operations as required

Revit Modeling & Detailing, Family creation, Report generation. Modeling & Coordination: Develop and manage detailed 3D/4D/5D BIM models for architecture, structure, and MEP systems. Ensure models are compliant with project BIM standards, LOD requirements, and naming conventions. Perform clash detection and coordinate across disciplines using tools like Navisworks or Revit. Documentation & Drawings: Generate and update construction drawings, shop drawings, and as-built documentation from BIM models. Support the creation of BOQs, schedules, and quantity take-offs using BIM data. Project Collaboration: Collaborate with architects, structural engineers, MEP consultants, and contractors for model inputs and updates. Participate in BIM coordination meetings and communicate design/modeling changes effectively

MD/DNB/DMRD Radiology Consultant with the relevant Exp. (any), procedures & knowledge of CT/USG in a corporate chain of path labs in different parts of Mumbai, Pune & Thane @ best CTC subject to Exp. Shruti (HRM) T: 9819454343 E: cv@sarajobs.com Perks and benefits Family Accommodation may get subject to Location

• Should have worked hands-on extensively on full chip DFT design, • implementation, vector generation/verification, JTAG, Boundary scan & Simulation. • Experience with Scan, Compression, ATPG & Simulations with Mentor/Synopsys/ Cadence tools. Required Candidate profile • Participated in Successful Tapeouts of SoC/ASIC chips at 14nm or below. • Develop/Automate flows & scripts in Perl/Tcl to enhance the DFT methodologies & process. • Logic BIST knowledge is a plus.

Roles and Responsibilities Conduct CT scans, MRI scans, ultrasound examinations, and other diagnostic imaging procedures to diagnose medical conditions. Interpret scan results accurately and efficiently to provide accurate diagnoses. Collaborate with referring physicians to discuss patient care plans and treatment options. Stay up-to-date with latest advancements in radiology technology and techniques. Participate in quality improvement initiatives to enhance departmental efficiency. Desired Candidate Profile 2-7 years of experience as a Radiologist or equivalent role. Medical degree (MS/MD) or DM (Other Specialization). Strong knowledge of radiology principles, including CT scan, MRI, radio diagnosis, ultrasound, USG.

Revit Modeling & Detailing, Family creation, Report generation. Modeling & Coordination: Develop and manage detailed 3D/4D/5D BIM models for architecture, structure, and MEP systems. Ensure models are compliant with project BIM standards, LOD requirements, and naming conventions. Perform clash detection and coordinate across disciplines using tools like Navisworks or Revit. Documentation & Drawings: Generate and update construction drawings, shop drawings, and as-built documentation from BIM models. Support the creation of BOQs, schedules, and quantity take-offs using BIM data. Project Collaboration: Collaborate with architects, structural engineers, MEP consultants, and contractors for model inputs and updates. Participate in BIM coordination meetings and communicate design/modeling changes effectively

We are seeking a passionate and dynamic Lead Engineer Design for Test (DFT) to join our team. If you have extensive expertise in ATPG, SCAN, JTAG, and MBIST, and are eager to lead and mentor a talented team, this is the perfect opportunity for you! Key Responsibilities Lead and guide a team of engineers in the implementation of advanced DFT methodologies. Architect, implement, and validate DFT techniques, including ATPG, SCAN, JTAG, and MBIST, ensuring efficient and scalable design solutions. Collaborate closely with design, verification, and backend teams to deliver high-quality silicon solutions. Drive design reviews, debug issues, and ensure successful tape-out. Optimize and innovate DFT strategies for cutting-edge semiconductor designs. Required Skills and Experience 5+ years of experience in Design for Test (DFT) implementation and methodologies. Strong expertise in ATPG, SCAN, JTAG, MBIST , or at least one DFT technique with hands-on experience. Experience with industry-standard DFT tools such as Synopsys Tetramax, Mentor Tessent, Cadence Modus, or similar tools. Proven ability to debug DFT-related issues in pre-silicon and post-silicon environments. Excellent communication and leadership skills to lead and mentor a team. Proactive and adaptable with a problem-solving mindset. Preferred Qualifications Experience in SOC-level DFT implementation. Familiarity with RTL design and verification methodologies. Knowledge of silicon bring-up and testing processes. Why Join Us? Best Salary in the Market for the right candidate. Attractive bonus plan to reward your contributions. Be part of a fast-growing, innovative team driving next-generation semiconductor solutions. Opportunities to lead and shape projects with cutting-edge technology. A supportive and collaborative work environment that values your expertise and contributions. How to Apply? Please submit your application through prabhu.p@acldigital.com . For any queries, feel free to reach out me

We are seeking a passionate and dynamic Lead Engineer Design for Test (DFT) to join our team. If you have extensive expertise in ATPG, SCAN, JTAG, and MBIST, and are eager to lead and mentor a talented team, this is the perfect opportunity for you! Key Responsibilities Lead and guide a team of engineers in the implementation of advanced DFT methodologies. Architect, implement, and validate DFT techniques, including ATPG, SCAN, JTAG, and MBIST, ensuring efficient and scalable design solutions. Collaborate closely with design, verification, and backend teams to deliver high-quality silicon solutions. Drive design reviews, debug issues, and ensure successful tape-out. Optimize and innovate DFT strategies for cutting-edge semiconductor designs. Required Skills and Experience 9+ years of experience in Design for Test (DFT) implementation and methodologies. Strong expertise in ATPG, SCAN, JTAG, MBIST , or at least one DFT technique with hands-on experience. Experience with industry-standard DFT tools such as Synopsys Tetramax, Mentor Tessent, Cadence Modus, or similar tools. Proven ability to debug DFT-related issues in pre-silicon and post-silicon environments. Excellent communication and leadership skills to lead and mentor a team. Proactive and adaptable with a problem-solving mindset. Preferred Qualifications Experience in SOC-level DFT implementation. Familiarity with RTL design and verification methodologies. Knowledge of silicon bring-up and testing processes. Why Join Us? Best Salary in the Market for the right candidate. Attractive bonus plan to reward your contributions. Be part of a fast-growing, innovative team driving next-generation semiconductor solutions. Opportunities to lead and shape projects with cutting-edge technology. A supportive and collaborative work environment that values your expertise and contributions. How to Apply? Please submit your application through prabhu.p@acldigital.com . For any queries, feel free to reach out me

Like Requirements: 3 to 6 years of hands-on experience in DFT methodologies , with expertise in Scan & ATPG . Strong knowledge of DFT tools such as Synopsys, Mentor Graphics, or Cadence. Experience in fault modeling, pattern generation, and coverage analysis . Proficiency in scripting (TCL, Python, Perl, or Shell) for automation. Excellent problem-solving skills and ability to work in a fast-paced environment. Job Responsibilities: Implement and validate DFT architectures for complex SoCs. Perform scan insertion and ensure proper integration into the design. Develop and optimize ATPG patterns to achieve high fault coverage. Work closely with RTL, verification, and physical design teams to resolve DFT-related issues. Support post-silicon bring-up, debug, and ATE (Automated Test Equipment) testing.

MD/DNB/DMRD Radiology Consultant with the relevant Exp. (any), procedures & knowledge of CT/USG in renowned Hospitals in Bahadurgarh(NCR), Kanpur (UP), Mumbai (MH) @ CTC best. Shruti (HRM) T: 9819454343 Email: cv@sarajobs.com Perks and benefits Family Accommodation may get subject to Location

In this role, you would be responsible for Developing and implementing DFT architectures and methodologies, including Scan, ATPG, MBIST, and JTAG.

Experience - 3-5 years of experience in HR, with a focus on social audits and security compliance. Qualifications: Bachelor's degree in Human Resources, Business Administration, or a related field. Job Summary: The HR Assistant Manager will play a crucial role in ensuring the company's compliance with social audit standards (SEDEX), security requirements (CTPAT & SCAN), and other relevant regulations. This position will be responsible for coordinating and supporting all aspects of these audits, including documentation, training, implementation of corrective actions, and maintaining strong relationships with auditors and relevant stakeholders. The ideal candidate will have a strong understanding of HR principles, audit processes, and a commitment to ethical and compliant workplace practices. Responsibilities: Social Audit (SEDEX): Audit Coordination: Schedule and coordinate SEDEX audits, including pre-audit preparations, on-site audits, and post-audit follow-ups. Act as the primary point of contact for SEDEX auditors. Manage and maintain all SEDEX documentation, including self-assessment questionnaires (SAQs), corrective action plans (CAPs), and audit reports. Compliance & Implementation: Ensure compliance with SEDEX requirements related to labor standards, health and safety, environment, and business ethics. Implement and maintain policies and procedures to meet SEDEX standards. Conduct internal audits and risk assessments to identify potential non-compliance issues. Develop and deliver training programs on SEDEX requirements for employees and management. Corrective Actions: Develop and implement corrective action plans to address audit findings. Monitor and track the progress of corrective actions and ensure timely completion. Analyze audit data and identify trends to improve overall compliance. Security Audits (CTPAT & SCAN): Audit Management: Coordinate and support CTPAT (Customs Trade Partnership Against Terrorism) and SCAN (Supplier Compliance Audit Network) audits. Maintain accurate records of security-related documentation, including risk assessments, security procedures, and training records. Ensure compliance with CTPAT and SCAN security requirements. Security Procedures: Implement and maintain security procedures related to physical security, access control, personnel security, and information security. Conduct regular security assessments and identify potential security vulnerabilities. Develop and deliver security awareness training programs for employees. Documentation and Reporting: Maintain detailed records of all security related activities. Generate reports on security performance and compliance. Work with relevant departments to assure all required documentation is available. General HR Responsibilities: Policy Development & Implementation: Assist in the development and implementation of HR policies and procedures related to social compliance and security. Ensure that all policies and procedures are communicated effectively to employees. Employee Training: Develop and deliver training programs on relevant HR topics, including labor laws, ethical conduct, and workplace safety. Maintain accurate training records. Documentation & Record Keeping: Maintain accurate and up-to-date HR records, including employee files, audit documentation, and training records. Ensure compliance with data privacy regulations. Stakeholder Communication: Communicate effectively with internal and external stakeholders, including auditors, employees, and management. Act as a liaison between HR and other departments regarding audit-related matters. Continuous Improvement: Stay up-to-date on changes in social audit standards, security regulations, and HR best practices. Identify opportunities for process improvement and implement changes to enhance efficiency and effectiveness.

MD/DNB/DMRD Radiology Consultant with the relevant Exp. (any), procedures & knowledge of CT/USG in a corporate chain of path labs in different parts of Mumbai & Thane @ best CTC subject to Exp. Shruti (HRM) T: 9819454343 Email: cv@sarajobs.com Perks and benefits Family Accommodation may get subject to Location

• Should have worked hands-on extensively on full chip DFT design, • implementation, vector generation/verification, JTAG, Boundary scan & Simulation. • Experience with Scan, Compression, ATPG & Simulations with Mentor/Synopsys/ Cadence tools. Required Candidate profile • Participated in Successful Tapeouts of SoC/ASIC chips at 14nm or below. • Develop/Automate flows & scripts in Perl/Tcl to enhance the DFT methodologies & process. • Logic BIST knowledge is a plus.