49 Scan Jobs

• In Depth of DFT concepts including Analog IP block testing. • EXP in DFT Insertion, includes SCAN, MBIST, BSCAN, IJTAG. • Well versed with RTL level or Netlist level Insertion (Block level/Top level). • ATPG Coverage Analysis & improvement. Required Candidate profile • Strong fundamentals in DFT • Exp in SCAN, MBIST, BSCAN, IP test modes & Post silicon support. • Equivalence check & RTL lint tool (spyglass). • Exp with ATE Pattern Development & ATE support

You are seeking highly skilled and motivated DFT-DV Engineers to join the dynamic team in Bangalore. As a DFT-DV Engineer, you will play a pivotal role in ensuring the quality and reliability of digital designs through Design for Test (DFT) and Design Verification (DV) methodologies. The ideal candidates should possess a minimum of 4 to 7+ years of experience in the field, with a strong background in DFT DV flow, JTAG, MBIST, SCAN, PG, PHY-LP, and BSCAN. - DFT Implementation: Collaborate with design and verification teams to define and implement DFT strategies and methodologies that enable efficient testing of complex digital designs. - Scan and ATPG: Develop and maintain scan insertion, Aut...

Role Overview: Sandisk is looking for a highly skilled and experienced DFT Engineer to join their dynamic team of engineers in developing the next-generation Flash Controllers. As an SoC DFT Engineer, you will be responsible for defining and implementing industry-leading DFT solutions, with a focus on SCAN, MBIST, BSDL, and more. The ideal candidate should have a deep understanding of DFT Architecture, Implementation flow, MBIST, SCAN ATPG, and Simulation expertise. Key Responsibilities: - Define DFT Architecture for SoC development - Lead complex activities and provide solutions for intricate DFT problems - Collaborate with cross-functional teams to define and refine SoC DFT requirements, e...

DFT Lead Engineer ASIC/SoC About the Company: Aevas mission is to bring the next wave of perception to a broad range of applications — from automated driving to industrial robotics, consumer electronics, and beyond. Aeva’s groundbreaking 4D LiDAR technology integrates key LiDAR components onto a single silicon photonics chip, enabling devices to sense both position and instant velocity for safer, smarter decision-making. Role Overview: As a DFT Lead Engineer , you will define, develop, and optimize Design-For-Test architecture for Aeva’s high-performance LiDAR SoCs . You’ll own the end-to-end DFT strategy — from planning and insertion to verification, silicon bring-up, and yield improvement....

We are looking for an experienced and motivated ATE Test Engineer with hands-on expertise in the Advantest V93000 ATE platform. In this key role, you will be responsible for developing, debugging, and deploying high-quality test solutions for next-generation semiconductor devices. This is an exciting opportunity to join our engineering team and contribute to the advancement of test programs for cutting-edge ICs. The position is well-suited for software engineers with a strong electronics background or semiconductor test engineers experienced in ATE development. Key Responsibilities Develop and maintain automated test programs on ATE platforms such as Advantest V93000, using C++ / Java in a L...

Develop & maintain test programs on ATE platforms such as Advantest V93000, using C++ / Java in a Linux-based environment Debug & optimize functional, parametric &performance tests across all test phases engineering, characterization, and production Accessible workspace Work from home Accidental insurance Health insurance Relocation bonus Gratuity Provident fund

As a DFT Design Engineer at our company, your role will involve working on DFT design from unit level to chip level, encompassing all aspects of DFT design functions such as scan, MBIST, and ATPG. You will have opportunities to contribute in the areas of CPU and SOC DFT design and verification. Key Responsibilities: - Define DFT strategy and methodologies - Design the DFT features - Define test structures, debug structures, and test plans - Create test vectors or oversee their creation - Collaborate with the physical design team to meet requirements - Validate DFT requirements are being fulfilled - Work with designers to enhance test coverage, debug observability, and flexibility - Verify po...

Eximietas Design is expanding its team and we are currently looking for DFT Engineers to join us at our Bangalore, Ahmedabad, Pune and Hyderabad locations. If you have 5+ years of experience in DFT (ASIC/SoC) , this could be a great opportunity for you. Role: DFT Engineer Experience: 5+ years Locations: Bangalore, Ahmedabad, Pune and Hyderabad Key Responsibilities: Develop and implement DFT architecture and methodologies for ASIC/SoC designs Scan insertion, ATPG, scan stitching, MBIST/Logic BIST implementation Boundary scan (IEEE 1149.1), JTAG implementation & validation Test pattern creation & validation (stuck-at, transition, path delay faults) Collaborate with RTL, synthesis, and physical...

As a Digital Circuit Designer at our company, you will be responsible for designing and testing digital circuits using Verilog HDL. Your role will involve ensuring the testability of designs through DFT techniques such as JTAG, ATPG, Scan, and MBIST. Your expertise in programming languages like Perl, TCL, or Python will be crucial for automation purposes. Moreover, your familiarity with Unix and Linux operating systems will add value to your responsibilities. Key Responsibilities: - Strong Knowledge in Digital Design & Verilog HDL. - Hands-on experience in DFT (Design for Testability) including JTAG, ATPG, Scan, and MBIST. - Programming skill in Perl, TCL, or Python. - Familiarity with Unix ...

As a DFT engineer, you will play a crucial role in planning, implementing, and verifying DFT features for multiple SoCs. Your responsibilities will include working on various aspects of IP and SoC DFT, such as DFT Architecture, Spyglass DFT, RTL implementation, Verification, Scan, ATPG, SCAN insertion, ATPG, pattern simulation/debug, MBIST, Repair implementation, TOP DFT architecture Design, ATE vector setup, and Yield improvement. You will be driving the DFT implementation for features like Scan, MBIST, TAP, and should have experience in executing at least 3 full SoC end to end. Key Responsibilities: - Work on various aspects of IP and SoC DFT including DFT Architecture, Spyglass DFT, RTL i...

Role Overview: You will be part of the Client Development Group (CDG) as a Design for Test engineer, responsible for developing logic design, RTL coding, simulation, DFT timing closure support, test content generation, and delivery to manufacturing for various DFx content. Your role will involve participating in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed. You will apply various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT. Additionally, you will optimize logic to qualify the design for power, performance, area, timing, and design integrity for physical implementation....

As a Synthesis & STA engineer, you will be responsible for performing RTL Synthesis to optimize the Performance/Power/Area of the designs. Your role will involve DFT insertions such as MBIST and SCAN, setting up Timing Constraints for functional and Test Modes, and Validation. You will be expected to create Power Intent for the designs, verify power intent on RTL, run static Low-Power checks on gate level netlists, and ensure Logic Equivalency Checks between RTL to Gates and Gates to Gates. Collaborating with the Design/DFT/PD teams, you will set up signoff Static Timing Analysis and ECO flows to achieve timing closure. Additionally, you will be involved in Power Analysis, estimating power a...

Reviewing scans obtained by radiology technologists using various modalities. Writing detailed reports that explain the findings from medical images to other physicians. Collaborating with other healthcare professionals Required Candidate profile If you are interested for this role kindly share your resume on WhatsApp - 8650633739 Ashana with the following details Ctc Ectc Notice period Current Location Interview Availibality

About Us: Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, and spec to the product. With 3200+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution, from design to packaged parts. Tessolves design services include solutions on advanced process nodes with a healthy eco-system relationship with EDA, IP, and foundries. Our front-end design strengths integrated with the knowledge from the backend flow, allows Tessolve to catch design flaws ahead ...

As the candidate for the position at Ceremorphic AI hardware, you will be responsible for owning and driving the physical implementation of next-generation SOCs. Your role will involve understanding requirements and defining physical implementation methodologies. You will collaborate with architecture, design, front end, and CAD teams to ensure the delivery of high-quality physical designs. Additionally, you will be responsible for implementing and verifying designs at all levels of hierarchy in the SOC. Your role will also entail interacting with the foundry on matters related to technology, schedule, and signoff, as well as supervising resource allocation and scheduling. Key Responsibiliti...

Role Overview: As a member of the Common Hardware Group (CHG) at Cisco, you will be part of a team that delivers cutting-edge silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. Your work will involve designing networking hardware for Enterprises, Service Providers, Public Sector, and Non-Profit Organizations worldwide. Join the team in shaping Cisco's groundbreaking solutions by participating in the design, development, and testing of advanced ASICs that are at the forefront of the industry. Key Responsibilities: - Implement Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug, and diagnostics requirements of the des...

Revit Modeling & Detailing, Family creation, Report generation. Modeling & Coordination: Develop and manage detailed 3D/4D/5D BIM models for architecture, structure, and MEP systems. Ensure models are compliant with project BIM standards, LOD requirements, and naming conventions. Perform clash detection and coordinate across disciplines using tools like Navisworks or Revit. Documentation & Drawings: Generate and update construction drawings, shop drawings, and as-built documentation from BIM models. Support the creation of BOQs, schedules, and quantity take-offs using BIM data. Project Collaboration: Collaborate with architects, structural engineers, MEP consultants, and contractors for mode...

We are seeking a highly experienced Senior DFT Engineer with 8+ years of hands-on expertise in developing and implementing DFT architectures for complex SoCs. The ideal candidate should have a solid background in scan insertion, ATPG, BIST, and silicon debug. Key Responsibilities: Define and implement DFT architecture for digital and mixed-signal SoCs Perform scan insertion, boundary scan, and ATPG pattern generation Integrate Memory BIST (MBIST) and Logic BIST (LBIST) Drive DFT verification and post-silicon validation/debug Collaborate with RTL, synthesis, STA, and backend teams to ensure testability Ensure high test coverage, test time optimization, and compliance with ATE requirements Req...

• Should have worked hands-on extensively on full chip DFT design, • implementation, vector generation/verification, JTAG, Boundary scan & Simulation. • Experience with Scan, Compression, ATPG & Simulations with Mentor/Synopsys/ Cadence tools. Required Candidate profile • Participated in Successful Tapeouts of SoC/ASIC chips at 14nm or below. • Develop/Automate flows & scripts in Perl/Tcl to enhance the DFT methodologies & process. • Logic BIST knowledge is a plus.

Eximietas Design is expanding its team and we are currently looking for DFT Engineers to join us at our Bangalore and Ahmedabad locations. If you have 5+ years of experience in DFT (ASIC/SoC) , this could be a great opportunity for you. Role: DFT Engineer Experience: 5+ years Locations: Bangalore / Ahmedabad Key Responsibilities: Develop and implement DFT architecture and methodologies for ASIC/SoC designs Scan insertion, ATPG, scan stitching, MBIST/Logic BIST implementation Boundary scan (IEEE 1149.1), JTAG implementation & validation Test pattern creation & validation (stuck-at, transition, path delay faults) Collaborate with RTL, synthesis, and physical design teams to ensure DFT complian...

• Should have worked hands-on extensively on full chip DFT design, • implementation, vector generation/verification, JTAG, Boundary scan & Simulation. • Experience with Scan, Compression, ATPG & Simulations with Mentor/Synopsys/ Cadence tools. Required Candidate profile • Participated in Successful Tapeouts of SoC/ASIC chips at 14nm or below. • Develop/Automate flows & scripts in Perl/Tcl to enhance the DFT methodologies & process. • Logic BIST knowledge is a plus.

The role at Ceremorphic AI hardware involves owning and driving the physical implementation of next-generation SOCs. The responsibilities include understanding requirements, defining physical implementation methodologies, collaborating with various teams, implementing and verifying designs, interacting with foundry, and supervising resource allocation and scheduling. The ideal candidate should have hands-on expertise in floorplanning, power planning, logic and clock tree synthesis, placement, timing closure, routing, extraction, physical verification (DRC & LVS), crosstalk analysis, and EM/IR. Additionally, full chip/top-level expertise in multiple chip tape-outs, understanding of SCAN, BIST...

You are an experienced Design-for-Test (DFT) Engineer with over 5 years of hands-on expertise in DFT methodologies and implementation. You should possess a solid understanding of MBIST, Scan, ATPG, and simulation concepts, along with a proven track record of executing industry-standard DFT flows. Your key responsibilities will include performing MBIST insertion, Scan insertion, and ATPG pattern generation using industry-standard EDA tools. You will be conducting MBIST simulations and analyzing results using tools from Cadence, Siemens Tessent, or Synopsys. Additionally, you will execute zero delay and SDF-based timing simulations, and efficiently debug issues using simulators such as VCS, NC...

As a Territory Service Representative (Bikers), your responsibilities include handling both delivery and pickup operations efficiently. For the delivery aspect, your tasks involve unloading bags from the vehicle, scanning shipments, sorting them primarily and secondarily, and scanning out shipments in accordance with the delivery route. It is crucial to deliver shipments solely to the designated package addresses. You must obtain acknowledgments from customers using a device (BYOD) and accurately update the status code for undelivered shipments at customer addresses. You will receive training on the delivery process, and it is essential to hand over the COD amount to the supervisor on the sa...

You are invited to join our team at Sandisk as a DFT Engineer, where you will play a crucial role in developing the next-generation Flash Controllers. As an SoC DFT Engineer, your primary responsibility will be to define and implement cutting-edge DFT solutions, focusing on SCAN, MBIST, BSDL, and other key aspects. The ideal candidate should possess a profound understanding of DFT Architecture, Implementation flow, MBIST, SCAN ATPG, and Simulation expertise. As a DFT Engineer at Sandisk, you will be involved in various essential duties and responsibilities, including: - Defining DFT Architecture for SoC development. - Leading complex activities and offering solutions for intricate DFT proble...