49 Scan Jobs - Page 2

You will be joining Cloudnine Hospital in Sahakarnagar, Bengaluru as a Fetal Medicine Expert, providing evening coverage. The ideal candidate should have a qualification in OBG with Fetal Medicine Fellowship OR Radiology with Fetal Medicine Fellowship and relevant experience. Your primary responsibility will be conducting scans and providing expertise in the field of Fetal Medicine.,

As a Territory Service Representative (Bikers), your primary responsibility will be to ensure timely and efficient delivery and pickup of shipments. Your tasks will include unloading bags from the vehicle, scanning the shipments, and performing primary and secondary sorting of the items. It is crucial to outscan the shipments according to the delivery route and deliver them to the specified package address. During the delivery process, you will be required to interact with customers and obtain acknowledgments through a device (BYOD). It is essential to update the correct status code for undelivered shipments at the customer's address. You will receive training on the delivery process to ensu...

The DFX Verification Lead position is located in Bangalore and requires 4 to 8 years of experience. The ideal candidate should have a strong understanding of DFT requirements such as Scan, BIST, and JTAG Debuggers. In this role, you will collaborate with IP and integration teams to ensure the successful implementation and verification of design elements. Your responsibilities will include working closely with designers and verification engineers to guarantee functionality and design features for future projects. To excel in this role, you must have a deep knowledge of verification flows and be proficient in debugging at both SoC and system levels. Additionally, expertise in Verilog, System V...

As a Design Manager at Texas Instruments, you will have the opportunity to lead a team of RTL front end, Digital Back end & Design verification engineers. Your primary responsibilities will include directing and guiding the activities of a research or technical design function, overseeing the design, development, modification, and evaluation of digital electronic parts, components, or integrated circuitry for electronic equipment and hardware systems. You will evaluate the final results of research and development projects to ensure the accomplishment of technical objectives. Additionally, you will be involved in preparing and presenting reports outlining the outcomes of technical projects a...

KEY RESPONSIBILITIES: Implementation and verification of DFT features likeSCAN, MBIST, LBIST and JTAG SupportSpyglass-DFTDRC debug and coverage correlation Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning PREFERRED EXPERIENCE: Experience in scan-stitching; and has good knowledge of scan-stitching related concepts Exposure to MBIST/BISR implementation and with the Tessent flow of mbist-insertion Excellent hands-on ATPG; and is we'll conversed with the files required to run ATPG Knowledge/experience with Tessent ATPG (mento...

The Common Hardware Group (CHG) at Cisco is responsible for delivering silicon, optics, and hardware platforms for core Switching, Routing, and Wireless products. As a part of this team, you will contribute to designing networking hardware for Enterprises, Service Providers, the Public Sector, and Non-Profit Organizations globally. Cisco Silicon One is a groundbreaking silicon architecture that allows customers to utilize top-of-the-line silicon in various network environments. Join us in shaping innovative solutions by working on the design, development, and testing of complex ASICs. In this role, you will collaborate with the team on Verilog RTL and scripted flow implementation of Hardware...

The Common Hardware Group (CHG) at Cisco is responsible for delivering silicon, optics, and hardware platforms for the core Switching, Routing, and Wireless products. We design networking hardware for Enterprises, Service Providers, the Public Sector, and Non-Profit Organizations worldwide. Cisco Silicon One is a unique silicon architecture that allows customers to utilize top-of-the-line silicon in TOR switches, web-scale data centers, and across various networks with a unified routing and switching portfolio. Join our team and contribute to shaping Cisco's innovative solutions by participating in the design, development, and testing of cutting-edge ASICs. As a member of our team, you will ...

We are seeking a highly experienced Senior DFT Engineer with 8+ years of hands-on expertise in developing and implementing DFT architectures for complex SoCs. The ideal candidate should have a solid background in scan insertion, ATPG, BIST, and silicon debug. Key Responsibilities: Define and implement DFT architecture for digital and mixed-signal SoCs Perform scan insertion, boundary scan, and ATPG pattern generation Integrate Memory BIST (MBIST) and Logic BIST (LBIST) Drive DFT verification and post-silicon validation/debug Collaborate with RTL, synthesis, STA, and backend teams to ensure testability Ensure high test coverage, test time optimization, and compliance with ATE requirements Req...

You will be expected to independently execute mid-sized customer projects in the field of VLSI Frontend, Backend, or Analog design with minimal supervision. As an individual contributor, you will own a specific task related to RTL Design/Module and provide support and guidance to engineers in various areas such as Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. Your role will involve anticipating, diagnosing, and resolving problems while coordinating with cross-functional teams as necessary. It is essential to ensure on-time quality delivery that meets the approval of the project manager and the client. Additionally, you will be responsible f...

MD/DNB/DMRD Radiology Consultant with the relevant Exp. (any), procedures & knowledge of CT/USG in a corporate chain of path labs in different parts of Mumbai, Pune & Thane @ best CTC subject to Exp. Shruti (HRM) T: 9819454343 E: cv@sarajobs.com Perks and benefits Family Accommodation may get subject to Location

The role involves independently executing mid-sized customer projects in the field of VLSI Frontend, Backend, or Analog design with minimal supervision. As an individual contributor, you will be responsible for owning a task in RTL Design/Module and providing support and guidance to engineers in various areas like Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. You will need to anticipate, diagnose, and resolve problems by coordinating with cross-functional teams, ensuring on-time quality delivery approved by the project manager and client. One of the key aspects of the role is to automate design tasks flows and write scripts to generate repo...

As a member of the Common Hardware Group (CHG) at Cisco, you will be part of a team that delivers cutting-edge silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. Our work involves designing networking hardware for Enterprises, Service Providers, Public Sector, and Non-Profit Organizations worldwide. Join us in shaping Cisco's groundbreaking solutions by participating in the design, development, and testing of advanced ASICs that are at the forefront of the industry. Your role will involve implementing Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug, and diagnostics requirements of the designs. You will collabora...

Who We Are The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With ~2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfoli...

• Should have worked hands-on extensively on full chip DFT design, • implementation, vector generation/verification, JTAG, Boundary scan & Simulation. • Experience with Scan, Compression, ATPG & Simulations with Mentor/Synopsys/ Cadence tools. Required Candidate profile • Participated in Successful Tapeouts of SoC/ASIC chips at 14nm or below. • Develop/Automate flows & scripts in Perl/Tcl to enhance the DFT methodologies & process. • Logic BIST knowledge is a plus.

As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world-class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Key Responsibilities & Expertise Minimum of 3+ years experience in the area of DFT (Design-for-Test) , including ATPG (Automatic Test Pattern Generation), Scan Insertion, MBIST (Memory Built-In Self-Test), JTAG . In-depth knowledge of DFT concepts . In-depth knowledge and hands-o...

Like Requirements: 5 to 10 years of hands-on experience in DFT methodologies , with expertise in Scan & ATPG, MBIST Strong knowledge of DFT tools such as Synopsys, Mentor Graphics, or Cadence. Experience in fault modeling, pattern generation, and coverage analysis . Proficiency in scripting (TCL, Python, Perl, or Shell) for automation. Excellent problem-solving skills and ability to work in a fast-paced environment. Job Responsibilities: Implement and validate DFT architectures for complex SoCs. Perform scan insertion and ensure proper integration into the design. Develop and optimize ATPG patterns to achieve high fault coverage. Work closely with RTL, verification, and physical design teams...

Job Title: Ab Initio Developer Location: Gurugram Experience: 4-5 years Employment Type: Full Time Job Summary: We are seeking an experienced Ab Initio Developer to design, develop, and maintain high-volume, enterprise-grade ETL solutions for our data warehouse environment. The ideal candidate will have strong technical expertise in Ab Initio components, SQL, UNIX scripting, and the ability to work collaboratively with both business and technical teams to deliver robust data integration solutions. Key Responsibilities: Analyze, design, implement, and maintain large-scale, multi-terabyte data warehouse ETL applications that operate 24/7 with high performance and reliability. Develop logical a...

Job Title: Ab Initio Developer Location: Gurugram Experience: 4-5 years Employment Type: Full Time Job Summary: We are seeking an experienced Ab Initio Developer to design, develop, and maintain high-volume, enterprise-grade ETL solutions for our data warehouse environment. The ideal candidate will have strong technical expertise in Ab Initio components, SQL, UNIX scripting, and the ability to work collaboratively with both business and technical teams to deliver robust data integration solutions. Key Responsibilities: Analyze, design, implement, and maintain large-scale, multi-terabyte data warehouse ETL applications that operate 24/7 with high performance and reliability. Develop logical a...

Roles & Responsibilities: Analyze, design, implement and maintain high volume, multi-terabyte 24/7 data warehouse robust and fast ETL applications Develop logical and physical data models; advanced ETL development using Ab Initio Be a technical player on complex ETL development projects with multiple team members Develop relevant functional and technical documentation. Lead, design and develop data warehouse solutions using different architecture, design and modeling techniques Work with business users to translate requirements into system flows, data flows, data mappings etc., and develop solutions to complex business problems. Lead the creation of all design review artifacts during project...

Revit Modeling & Detailing, Family creation, Report generation. Modeling & Coordination: Develop and manage detailed 3D/4D/5D BIM models for architecture, structure, and MEP systems. Ensure models are compliant with project BIM standards, LOD requirements, and naming conventions. Perform clash detection and coordinate across disciplines using tools like Navisworks or Revit. Documentation & Drawings: Generate and update construction drawings, shop drawings, and as-built documentation from BIM models. Support the creation of BOQs, schedules, and quantity take-offs using BIM data. Project Collaboration: Collaborate with architects, structural engineers, MEP consultants, and contractors for mode...

MD/DNB/DMRD Radiology Consultant with the relevant Exp. (any), procedures & knowledge of CT/USG in a corporate chain of path labs in different parts of Mumbai, Pune & Thane @ best CTC subject to Exp. Shruti (HRM) T: 9819454343 E: cv@sarajobs.com Perks and benefits Family Accommodation may get subject to Location

• Should have worked hands-on extensively on full chip DFT design, • implementation, vector generation/verification, JTAG, Boundary scan & Simulation. • Experience with Scan, Compression, ATPG & Simulations with Mentor/Synopsys/ Cadence tools. Required Candidate profile • Participated in Successful Tapeouts of SoC/ASIC chips at 14nm or below. • Develop/Automate flows & scripts in Perl/Tcl to enhance the DFT methodologies & process. • Logic BIST knowledge is a plus.

We are seeking an experienced Full-Chip STA Engineer to drive timing closure and sign-off across the entire SoC/ASIC design. The role requires expertise in multi-block integration, multi-mode/multi-corner analysis, and sign-off methodology for advanced technology nodes. Key Responsibilities: Perform full-chip static timing analysis for all functional and test modes across multiple PVT corners. Own SDC constraint generation, validation, and refinement at top-level. Collaborate with block-level STA, physical design, synthesis, and clock teams to achieve timing closure . Debug and resolve full-chip setup/hold violations through ECOs, floorplan changes, and clock optimizations. Conduct MMMC (Mul...

• Should have worked hands-on extensively on full chip DFT design, • implementation, vector generation/verification, JTAG, Boundary scan & Simulation. • Experience with Scan, Compression, ATPG & Simulations with Mentor/Synopsys/ Cadence tools. Required Candidate profile • Participated in Successful Tapeouts of SoC/ASIC chips at 14nm or below. • Develop/Automate flows & scripts in Perl/Tcl to enhance the DFT methodologies & process. • Logic BIST knowledge is a plus.