This is a great opportunity to work as a part of a highly regarded team delivering leading-edge solutions. We are seeking an experienced engineer for an exciting role to enhance the core Linux embedded team by working on the latest platforms and software. In this role, you will collaborate closely with key technical experts to ensure optimal performance and results on the SoC platforms. Your responsibilities will include embedded Linux software application/driver or kernel development, porting, customization, performance benchmarking, and optimization. Additionally, you will work with the team to build and support system software subsystems, own system software development and debugging, and implement functional safety features for embedded platforms. Key Qualifications: - Possess strong C/C++ development skills with a solid understanding of object-oriented design - Have a robust background in Microprocessor/Microcontroller/DSP based embedded systems development - Experience in engaging with the Linux community and contributing to Open-Source projects is preferred - Proficient in system knowledge and system debugging - Strong written and verbal communication skills - Self-motivated with the ability to take the lead in mastering new technologies - Capable of working both independently and as a team member - Conduct testing of developed modules through running tests - Provide regular progress reports to various stakeholders involved - Experience in FPGA-based system development is preferred - Exposure to RISC-V processors is advantageous - Functional Safety Certification is a bonus If you meet the above qualifications and are looking to be a part of a dynamic team working on cutting-edge solutions, we encourage you to apply for this role.,
As an FPGA Engineer at our company, you will be responsible for owning and driving the design, implementation, and verification of FPGA prototypes for next-generation SOCs. Your main responsibilities will include: - FPGA integration and implementation of all interfaces such as PCIe, DDR, etc. - FPGA implementation and timing closure. - Providing emulation platform solutions for FW development. - Offering emulation platforms for pre-silicon validation. - FPGA validation and debug. To excel in this role, you should meet the following key requirements: - Hands-on design experience using Verilog, System Verilog, and porting large designs to FPGA, including a combination of custom RTL and proven IP cores. - FPGA experience involving implementation, synthesis (Synplify/Vivado), and timing closure using Vivado. - Ability to partition a big ASIC design into multiple FPGA sub-systems and implement modules for interconnection between these sub-systems. - Proficiency in Perl and Tcl languages. - Good hardware debug skills using FPGA debug tools like Chipscope and lab debug equipment such as Oscilloscopes and Logic Analyzers to root cause issues at silicon or board level. - Hands-on experience with PCIe controller, DMA, working knowledge of AXI protocols, and ARM. - Ability to collaborate closely with the software team and engage in hardware-software co-debug. Join us in this exciting opportunity to work on cutting-edge FPGA designs and contribute to the development of next-generation SOCs.,
As the candidate for the position at Ceremorphic AI hardware, you will be responsible for owning and driving the physical implementation of next-generation SOCs. Your role will involve understanding requirements and defining physical implementation methodologies. You will collaborate with architecture, design, front end, and CAD teams to ensure the delivery of high-quality physical designs. Additionally, you will be responsible for implementing and verifying designs at all levels of hierarchy in the SOC. Your role will also entail interacting with the foundry on matters related to technology, schedule, and signoff, as well as supervising resource allocation and scheduling. Key Responsibilities: - Understand requirements and define physical implementation methodologies. - Collaborate with architecture, design, front end, and CAD teams to deliver high-quality physical designs. - Implement and verify designs at all levels of hierarchy in the SOC. - Interact with the foundry over matters of technology, schedule, and signoff. - Supervise resource allocation and scheduling. Qualifications Required: - Hands-on expertise in Floorplanning, Power planning, Logic and clock tree synthesis, Placement, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR. - Full chip/top-level expertise in multiple chip tape-outs. - Good understanding of SCAN, BIST, and ATPG. - Strong background in TCL/Perl programming is a must. - Expertise in double patterning process nodes is desirable. - Expertise in Cadence RTL-to-GDSII flow is preferred.,