Basics nand , nor , latches , flops , building blocks , tools - finesim , spectre; DRAM/ SRAM is Mandatory Simulation tools: Cadence/Spectre/ primesim - Must Have Experience: 3-5 Yrs Onsite: Hyderabad
Strong knowledge in SV,UVM Skills: SOC/IP Verification Protocol: Ethernet/PCIe Experience: 4+ Years Should have Scripting knowledge Need experience in 2 tape outs projects
Tech node: 7nm and below Tools: Cadence - Innovus and Tempus, Genus
UVM/SV Any protocol: USB, DDR, PCIe, Ethernet SOC/IP
As a Synthesis & STA engineer, you will be responsible for performing RTL Synthesis to optimize the Performance/Power/Area of the designs. Your role will involve DFT insertions such as MBIST and SCAN, setting up Timing Constraints for functional and Test Modes, and Validation. You will be expected to create Power Intent for the designs, verify power intent on RTL, run static Low-Power checks on gate level netlists, and ensure Logic Equivalency Checks between RTL to Gates and Gates to Gates. Collaborating with the Design/DFT/PD teams, you will set up signoff Static Timing Analysis and ECO flows to achieve timing closure. Additionally, you will be involved in Power Analysis, estimating power at the RTL level, performing Sign off Power Analysis on the P&R data, supporting DV team with gate level simulations, and assisting in functional eco rollout with automated ECO flows. Key Responsibilities: - Perform RTL Synthesis to optimize Performance/Power/Area - Implement DFT insertions including MBIST and SCAN - Set up Timing Constraints for functional and Test Modes - Create Power Intent for designs and verify power intent on RTL - Run static Low-Power checks on gate level netlists - Ensure Logic Equivalency Checks between RTL to Gates and Gates to Gates - Collaborate with Design/DFT/PD teams for signoff Static Timing Analysis and ECO flows - Support DV team with gate level simulations and functional eco rollout Qualification Requirements: - Minimum 3 years of experience - Experience with Synopsys tools for ASIC Synthesis, Timing Constraints, and DFT implementation - Familiarity with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks - Proficiency in Verilog and System Verilog - Strong RTL design experience with Perl/TCL/Makefile scripting - Hands-on experience with Power Analysis using Power Artist and PTPX - Experience in full-chip static timing analysis, gate level simulations, and Functional ECO implementation with Automated flows Education Requirements: - Required: Bachelor's in Electronics and Communications Engineering, Electrical Engineering, or related field - Preferred: Master's in VLSI or related field Location: Bangalore/Hyderabad (Note: Additional details about the company were not provided in the job description.),
Proven experience in CAD software development, including scripting and automation using Perl and Python Strong understanding of CAD systems and their integration with scripting languages. Basic knowledge on LSF interface with CAD Tools
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