• Design Methodology, Micro-architecture, RTL.• Work with the architecture team to develop the uArch & Subsequently write RTL.• Develop Design Methodology, starting with the machine learning architecture.• Synthesis, STA, Equivalence checking.Required Candidate profile* EXP in SOC design methodology, Micro-architecture, Emulation & back-end DEV., & Chip Bring-up.* EXP in Developing ARM CPU based SoCs, Network-on-Chip & interfaces such as MIPI-CSI, Ethernet & PCIe

• Should have worked hands-on extensively on full chip DFT design, • implementation, vector generation/verification, JTAG, Boundary scan & Simulation. • Experience with Scan, Compression, ATPG & Simulations with Mentor/Synopsys/ Cadence tools.Required Candidate profile• Participated in Successful Tapeouts of SoC/ASIC chips at 14nm or below. • Develop/Automate flows & scripts in Perl/Tcl to enhance the DFT methodologies & process.• Logic BIST knowledge is a plus.

• Hands –On EXP. on atleast 2/ 3 of Analog Blocks• Good Understanding of Analog blocks like Op-amps, BGR’s, LDO’s, PLL’s , Clocking circuits, TX / RX.• EXP. on High Speed SERDES/ Memory Circuits is a PlusRequired Candidate profile• Exposure to cutting edge technology nodes like FinFets is a Plus• Strong Analog Design Fundamentals

• Well versed with the Timing Closure (STA), Timing closure methodologies• Pre/Post-layout constraint development to Timing Closure• Handshake with the Design team & Develop functional/DFT constraints• Abstraction expertise like Hyperscale/ILM/ETMRequired Candidate profile• RC Balancing & scaling analysis of critical data paths of full chip clock• Automation in PERL, TCL and EDA tool-specific scripting• DMSA @ full chip and custom scripts for timing fixes

• 5+ years of EXP. in Analog Layout• Hands-On with CAD tools like Cadence Virtuoso XL, PVS/Calibre or Synopsys IC Validator, StarRC• Proficient at debugging/fixing LVS/DRC errors• EXP. with synthesis/advanced P&R (Innovus) is a plusRequired Candidate profile• Work with circuit designers to complete the Physical Layout & Verification of High-Performance, Low-Power AMS CMOS IC's.• Solid understanding of semiconductor manufacturing process & DFM techniques

• Proficient in CPU architecture (ARM knowledge is desirable), Verilog, SystemVerilog and possess strong debugging skills.• Experience on CPU unit/microarchitecture verification• Should have worked on complex coverage driven verification projectsRequired Candidate profile• Experience - 8-15 Years• Experience of collaborating with cross-functional teams

• Experience in IP verification.• Main EDA Verification tools platforms for both simulation & Formal verification;• Competence in Python and TCL/TK scripting languages, Object Orienting Programming languagesRequired Candidate profile• Knowledge Bus protocols like AMBA AXI/AHB, & Common communication protocols.• Knowledge of Formal verification methodologies & SVA will be plus• Skills: AMBA AXI/AHB, Verification, System Verilog

• Experience in IP verification.• Main EDA Verification tools platforms for both simulation & Formal verification;• Competence in Python and TCL/TK scripting languages, Object Orienting Programming languagesRequired Candidate profile• Knowledge Bus protocols like AMBA AXI/AHB, & Common communication protocols.• Knowledge of Formal verification methodologies & SVA will be plus• Skills: AMBA AXI/AHB, Verification, System Verilog

• EXP. of Analog blocks like Op-amps, BGR’s, LDO’s, PLL’s , Clocking circuits, TX / RX.• Analog circuit in PMIC domain: Design of Voltage/Current references, Amplifiers, Comparators, Filters & Voltage sensors, Oscillators, Voltage clamps.Required Candidate profile• EXP on High Speed SERDES/ Memory Circuits is PLUS• Exposure to cutting edge technology nodes like FinFets is PLUS• Hands-On atleast 2/ 3 of Blocks• Strong Analog Design Fundamentals