• Physical Design of blocks & handle Complex block implementation. • Floorplan optimization for area, Power & Timing. • Block-level PnR & close Design to meet Timing, area & Power constraints. • Implement ECOs to fix timing, noise & EM-IR violations. Required Candidate profile * Exp in RTL Synthesis for PnR using small geometry FinFET. * Strong in Physical Design incl. physically aware Synthesis, floor-planning, PnR * Logic equivalency RTL2Synthesis & Synthesis2APR netlist.
• Should have worked hands-on extensively on full chip DFT design, • implementation, vector generation/verification, JTAG, Boundary scan & Simulation. • Experience with Scan, Compression, ATPG & Simulations with Mentor/Synopsys/ Cadence tools. Required Candidate profile • Participated in Successful Tapeouts of SoC/ASIC chips at 14nm or below. • Develop/Automate flows & scripts in Perl/Tcl to enhance the DFT methodologies & process. • Logic BIST knowledge is a plus.
• Drive Area estimation, Floor Planning, Placement, Routing, Power planning, Verification, EMIR, ESD-LUP Verification & Tape out. • Understanding of low parasitic, high frequency design techniques. • Finfet process & Lower nodes; 2nm/3nm/5nm/7nm Required Candidate profile • Exp with Cadence (Virtuoso), Synopsys (CC), Calibre & ICV verification tools like LVS, DRC, Extraction. • Debugging/fixing LVS/DRC errors • Experience with EMIR, PERC tools. • Skill/TCL scripting.
1. 10-15 Yrs in DV full-chip Exp. 2. Experience in SV/UVM testbench verification 3. Experience in ARM Coresight Debug subsystem 4. CSI/ DSI protocol expertise 5. Memory controller or cache expertise 6. Hands-on RAL model development (UVM) Required Candidate profile • EXP in verifying successful IPs, Subsystems & or SoCs. • PC System Architecture: PCI Express, USB, Ethernet, HyperTransport, DDR. • Standard bus/interface protocols (i.e. AXI, AHB, AMBA, OCP, PIPE).
• Should have worked hands-on extensively on full chip DFT design, • implementation, vector generation/verification, JTAG, Boundary scan & Simulation. • Experience with Scan, Compression, ATPG & Simulations with Mentor/Synopsys/ Cadence tools. Required Candidate profile • Participated in Successful Tapeouts of SoC/ASIC chips at 14nm or below. • Develop/Automate flows & scripts in Perl/Tcl to enhance the DFT methodologies & process. • Logic BIST knowledge is a plus.
• Should have worked hands-on extensively on full chip DFT design, • implementation, vector generation/verification, JTAG, Boundary scan & Simulation. • Experience with Scan, Compression, ATPG & Simulations with Mentor/Synopsys/ Cadence tools. Required Candidate profile • Participated in Successful Tapeouts of SoC/ASIC chips at 14nm or below. • Develop/Automate flows & scripts in Perl/Tcl to enhance the DFT methodologies & process. • Logic BIST knowledge is a plus.
1. 12-18 Yrs in DV full-chip Exp. 2. Experience in SV/UVM testbench verification 3. Experience in ARM Coresight Debug subsystem 4. CSI/ DSI protocol expertise 5. Memory controller or cache expertise 6. Hands-on RAL model development (UVM) Required Candidate profile • EXP in verifying successful IPs, Subsystems & or SoCs. • PC System Architecture: PCI Express, USB, Ethernet, HyperTransport, DDR. • Standard bus/interface protocols (i.e. AXI, AHB, AMBA, OCP, PIPE).
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