Lead DFT Engineer

About Us:

Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, and spec to the product. With 3200+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs.

Tessolve offers a Turnkey ASIC Solution, from design to packaged parts. Tessolves design services include solutions on advanced process nodes with a healthy eco-system relationship with EDA, IP, and foundries. Our front-end design strengths integrated with the knowledge from the backend flow, allows Tessolve to catch design flaws ahead in the cycle, thus reducing expensive re-design costs, and risks. We actively invest in the R&D center of excellence initiatives such as 5G, mmWave, Silicon photonics, HSIO, HBM/HPI, system-level test, and others. Tessolve also offers end-to-end product design services in the embedded domain from concept to manufacturing under an ODM model with application expertise in Avionics, Automotive, Industrial and Medical segments. Tessolves Embedded Engineering services enable customers a faster time-to-market through deep domain expertise, innovative ideas, diverse embedded hardware & software services, and built-in infrastructure with world-class lab facilities.

Tessolves clientele includes Tier 1 clients across multiple market segments, 9 of the top 10 semiconductor companies, start-ups, and government entities. We have a global presence over 12 countries with office locations in the United States, India, Singapore, Malaysia, Germany, United Kingdom, Canada, UK, Japan, Taiwan, Philippines, and Test Labs in India, Singapore, Malaysia, Austin, San Jose. For more details, visit www.tessolve.com.

Job Overview

Role & responsibilities

• Leading DFT ATPG implementation, integration and verification of System-on-Chip (SoC) from initial specification till tapeout and production.
• Ensure Test Coverage Goals are met at SoC Level.
• Addressing test quality targets in DFT architecture and test pattern generation.
• Leading various aspects of Test architecture including MBIST, Scan & ATPG.
• Work with different functions like front-end design, verification and physical design to ensure production quality silicon.

Specific Knowledge/Skills

• Master/Bachelors Degree in Electrical/Electronic Engineering.
• Experience of 6 to 10 Years in DFT with successful delivery of production quality chips.
• Senior SoC DFT engineers, with experiences in all aspects of DFT, including MBIST, scan & ATPG, logic BIST.
• Good understanding of design flow from specification / micro-architecture definition to design and verification, timing analysis, and physical design.
• Self-motivated. Excellent written and verbal communication skill.
• Creative problem-solving skills, logic analysis skills, ability to logically break complex problems down to manageable components.
• Should be a team player and willing to work with cross functional teams in issues resolution.