95 Mbist Jobs

As a Design Manager at Texas Instruments, you will have the opportunity to lead a team of RTL front end, Digital Back end & Design verification engineers. Your primary responsibilities will include directing and guiding the activities of a research or technical design function, overseeing the design, development, modification, and evaluation of digital electronic parts, components, or integrated circuitry for electronic equipment and hardware systems. You will evaluate the final results of research and development projects to ensure the accomplishment of technical objectives. Additionally, you will be involved in preparing and presenting reports outlining the outcomes of technical projects and making recommendations for actions necessary to achieve desired results. In this role, you will play a key part in selecting, developing, and evaluating personnel to ensure the efficient operation of the function. Joining Texas Instruments as a Design Manager (RTL, P&R, Design Verification) will allow you to work with a team of enthusiastic engineers focused on developing highly complex and industry-leading devices for audio applications. You will be involved in developing new Audio converters catering to PE, Automotive, and Industrial market segments, with the digital content including a DSP for digital filters and audio signal processing blocks among various other IPs. Collaboration with various engineering teams within the product line, including analog design, layout, firmware, verification, validation, test, systems, applications, and marketing, will be a part of your role to successfully execute new products from concept to volume production and subsequent support. As a core member of the design team, you will drive flawless execution by finding innovative design architecture and solutions through out-of-the-box thinking to deliver highly differentiated products. This is an exceptional opportunity to be part of a team that is continuously seeking growth opportunities, working with leading customers globally, and developing cutting-edge solutions in consumer electronics, industrial, and automotive markets. To qualify for this position, you must hold a minimum bachelor's degree in electrical engineering and have at least 7 years of experience. Strong aptitude, hands-on experience in RTL frontend design, excellent command of RTL design concepts, and the ability to work with dynamically evolving requirements are some of the key qualifications needed for this role. You should also possess a result-driven attitude, the ability to mentor team members, and familiarity with digital backend flow and design verification flow. Preferred qualifications for this role include establishing strong relationships with key stakeholders, strong verbal and written communication skills, hands-on experience with Digital Back end tools, and the ability to quickly ramp up on new systems and processes. Demonstrated interpersonal, analytical, and problem-solving skills, ability to collaborate effectively with cross-functional teams, and strong time management skills are also desirable qualities for this position. As a Design Manager at Texas Instruments, you will be responsible for leading a team of 7+ engineers and multiple contractors, driving results while striving for excellence in the complete Digital (Front and Backend) & Design verification team. Your role will also involve overseeing the career growth of your team members. If you are passionate about engineering and shaping the future of electronics, Texas Instruments offers a collaborative environment where employees are empowered to own their career and development. Join us to work with some of the smartest people in the industry and contribute to creating a better world through affordable semiconductor technology. Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company dedicated to designing, manufacturing, and selling analog and embedded processing chips for various markets. Our core passion is to make electronics more affordable through innovative semiconductor solutions. We value diversity and inclusion in our work environment and strive to empower our employees to drive innovation forward. At Texas Instruments, we believe in creating a diverse, inclusive work environment and are an equal opportunity employer. If you are interested in this position, please apply to this requisition.,

Strong on Digital Design, SV, UVM. Hands-on experience in any of the DV protocols like PCIe, USB 3.0, DDR 3/4/5, AMBA, Ethernet (10G/100G), SATA, and MIPI (CSI/DSI), UFS, CXL Also Hiring PD, RTL, DFT Apply& Share resume to mansoor@hisoltech.com

KEY RESPONSIBILITIES: Implementation and verification of DFT features likeSCAN, MBIST, LBIST and JTAG SupportSpyglass-DFTDRC debug and coverage correlation Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning PREFERRED EXPERIENCE: Experience in scan-stitching; and has good knowledge of scan-stitching related concepts Exposure to MBIST/BISR implementation and with the Tessent flow of mbist-insertion Excellent hands-on ATPG; and is we'll conversed with the files required to run ATPG Knowledge/experience with Tessent ATPG (mentor) is a plus Knowledge on Spyglass-DFT Excellent hands-on debug skills and scripting skills are critical Knowledge on automation scripts like TCL/AWK/SED is a plus Understands the basics of JTAG Experience with post-silicon bring up is a plus ACADEMIC CREDENTIALS: Bachelors degree w/7+ years or Masters degree w/5+ years in Electronics engineering/Electrical Engineering

We are seeking an experienced and highly skilled Senior SOC Design for Test Engineer with aminimum of 5 years of hands-on experience in SOC Design for Test. As a key member of our team, you will play a pivotal role in ensuring the testability, manufacturability, and quality of our cutting-edge System on Chip designs Key Responsibilities Lead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution coverage, manufacturability, and quality plans. Develop full chip and block level DFT implementation from the DFx Specifications and product coverage, quality, and manufacturability goals. Define and implement Test controllers at top level and block level, fuse controllers, test clocking strategy, chip I/O test strategy and HSIO test strategy. Define JTAG TAP, boundary scan, I/O Test JTAG access, IEEE1687 iJTAG network and instrument design and implementation. Define the Test Interface for each of the P&R IP blocks for Scan, MBIST and other test interfaces. Define hierarchical block isolation, Test clocking and On Chip Clock controllers and reset methodology. Define scan and MBIST timing at the top level and block level timing. Analyse block level RTL or gates to ensure that scalability and coverage is satisfied as per the design goals. Ensure that DFT is provided to fix the DFT violations to ensure that the design goals are meet. Analyse compression requirements for each of the blocks, define Intest and Extest compression requirements and define the requirements for compression engines. Synthesize compression engines for each of the blocks. Create the collaterals for compression for the IPs. Block level scan insertion as well as development of the scan wrappers for the blocks. Do scan insertion on the blocks, analyse scan DRC, implement DFT fixes. Create scan protocol files for designs, create scan inserted netlist, create scan definitions as well as scan definition files for PD. Perform ATPG on the scan inserted netlist, analyse DRC and coverage violations. Deep knowledge of different scan models Stuck-at, transition test, path-delay, bridging, cell aware, small-delay transition, IDDQ test etc. Ability to analyse coverage for each of the model types. Running GLS with or without timing for the scan vectors. Ability to debug the failures and working with timing and PD teams to fix the timing issues. Understanding of pattern delivery to the post-silicon test engineering teams. Delivering to the Test engineering the Test pin muxing and other full chip requirements for the Test Engineering Team. Understanding tester requirements and delivering the patterns in the formats that the tester teams needs. Implement pattern retargeting. Create grey box models for blocks. Coverage analysis of full chip consolidating Intest and Extest patterns. Knowledge of Top level scan architecture and creating flow to create pattern retargeting. Knowledge of Streaming Scan Network and other Top level scan pin sharing and implementing the block to top level pattern generation for this flow. Implementing Memory Testing and MBIST. Knowledge of Memory defect models and test algorithms. Knowledge of memory bit mapping and redundancy analysis. Implementing memory repair and fuse sharing among various memory. Knowledge of LogicBIST with Test point insertion, X-blocking. Full chip DFT delivery for tapeout including but not limited to DFT netlist verification, pattern delivery, Tester requirements. Debug DFT patterns post silicon, ability to analyse chain test patterns for failures, scan pattern failures. Analyse MBIST pattern failures, yield and repair debug. Ability to perform volume diagnostics on the parts to isolate and improve the patterns. Requirements Bachelors degree in computer science, Electrical/Electronics Engineering, or related field. OR masters degree in computer science, Electrical/Electronics Engineering, or related field. OR PhD in Computer Science, Electrical/Electronics Engineering, or related field. 5+ years of hands-on experience in SOC Design for Test. Expertise in DFT tools and flows in scan intertion, ATPG, GLS simulation, diagnosis flows. Prior experience working on IP level and SOC level DFT projects. Proficient in DFT tools from Siemens (Tessent), Synopsys DFTmax, Tetramax, Spyglass DFT advisor, Genius DFT, Modus, VCS, Xcelium etc. Worked in full chip design or complex IP delivery in the area of DFT. Experience in post silicon debug, diagnosis and yield enhancements is a plus.

Location :- Bangalore Experience :- 12-20 years Required Skills And Experience: This role is for a Principal DFT engineer with 15 years plus experience Technical leadership in DFT and ability to train/work with junior team members Experience with Perl, TCL, and/or python with ability to build and deploy generic DFT flows Proficient in Unix/Linux environments One or more core DFT skills are considered crucial for this position including some of the following Knowledge of at-speed testing, test insertion and test coverage assessment, test pattern development, scan compression, Memory BIST, Logic BIST, JTAG, IJTAG, fault simulation, debug, verification, SSN, designing and conducting experiments/tool evaluations. Experience with Siemens, Cadence and/or Synopsys DFT tools Qualified candidates will have a university degree (or equivalent) in Electronic Engineering, Computer Engineering, or other relevant technical subject area.

You will be expected to independently execute mid-sized customer projects in the field of VLSI Frontend, Backend, or Analog design with minimal supervision. As an individual contributor, you will own a specific task related to RTL Design/Module and provide support and guidance to engineers in various areas such as Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. Your role will involve anticipating, diagnosing, and resolving problems while coordinating with cross-functional teams as necessary. It is essential to ensure on-time quality delivery that meets the approval of the project manager and the client. Additionally, you will be responsible for automating design tasks flows, writing scripts to generate reports, and proposing innovative ideas to reduce design cycle time and cost, which should be accepted by UST Manager and the client. Your performance will be measured based on the quality of deliverables, timely delivery, reduction in cycle time and cost through innovative approaches, the number of papers published, the number of patents filed, and the number of mandatory trainings attended. You should aim to deliver high-quality work by ensuring zero bugs in the design/circuit design, clean delivery of the design/module for easy integration at the top level, meeting functional specifications/design guidelines without any deviation, and documenting tasks and work performed. Timely delivery is crucial, and you must adhere to project timelines, deliver intermediate tasks to support team progress, and seek help and support if there are delays in task delivery. Continuous skills development is encouraged through participation in training sessions, upskilling in newer technologies, and taking on new areas of project development to enhance your knowledge and deliver results. Teamwork is essential, and you should actively participate, support team members when needed, take on additional tasks in the absence of team members, and assist junior team members in understanding project tasks. Going beyond the call of duty to meet deadlines and maintain quality standards is expected. Innovation and creativity are valued, and you should automate tasks to save design cycle time, participate in technical discussions, training forums, and contribute to white papers. Your skills should include proficiency in languages and programming such as System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, and Makefile. Experience with EDA tools like Cadence, Synopsys, Mentor tool sets, simulators, and various technical knowledge areas is required. Strong communication, analytical reasoning, problem-solving skills, attention to detail, and the ability to deliver tasks on time are essential. You should be well-versed in EDA tools, have the necessary technical skills, and be willing to learn new skills as required for project execution. Knowledge of project execution in various design areas, understanding design flow and methodologies, and the ability to execute project tasks as per known skills are key. Specific experience in DFT ATPG, Mbist, and SCAN is preferred, along with expertise in SOC or Subsystems designs, DFT methodologies, and standard DFT tools. Familiarity with SoC style DFT architectures, low power design practices, test mode timing constraint development, and analysis will be beneficial. Hands-on experience in ATPG, SCAN, MBIST, JTAG implementation, and knowledge of test compression and ATE debug are valuable assets. Your role will involve utilizing your skills and knowledge to contribute effectively to project success.,

The role involves independently executing mid-sized customer projects in the field of VLSI Frontend, Backend, or Analog design with minimal supervision. As an individual contributor, you will be responsible for owning a task in RTL Design/Module and providing support and guidance to engineers in various areas like Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. You will need to anticipate, diagnose, and resolve problems by coordinating with cross-functional teams, ensuring on-time quality delivery approved by the project manager and client. One of the key aspects of the role is to automate design tasks flows and write scripts to generate reports while also coming up with innovative ideas to reduce design cycle time and cost, which should be accepted by the UST Manager and client. Measures of success will include quality verification, timely delivery, reduction in cycle time cost through innovative approaches, number of papers published, number of patents filed, and attending mandatory trainings to meet training goals. The expected outputs include ensuring zero bugs in the design, clean delivery of the design/module for easy integration at the top level, meeting functional specifications and design guidelines without deviation, and documenting tasks and work performed. Timely delivery is crucial, meeting project timelines set by the client or program manager, delivering intermediate tasks to enable team progress, and seeking help and support in case of task delays. Continuous skill development is encouraged through participation in training, skilling others, acquiring new technologies, and taking up new areas of project development. Teamwork is essential, involving participation in team activities, supporting team members, taking up additional tasks when needed, and mentoring junior team members. Innovation and creativity are valued, with a focus on automating tasks to save design cycle time, participating in technical discussions, training, forums, white papers, etc. Skills required include proficiency in languages like System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, and EDA tools like Cadence, Synopsys, Mentor tool sets, simulators, and technical knowledge in IP Spec, Bus Protocols, Physical Design, Synthesis, DFT, etc. Strong communication, analytical reasoning, problem-solving skills, attention to detail, ability to understand specs and functional documents, and deliver tasks on time with quality are essential. Familiarity with EDA tools, willingness to learn new skills, and prior design knowledge are also necessary for successful project execution. Experience in DFT ATPG, Mbist, SCAN, and knowledge of SOC or Subsystems designs, DFT methodologies, low power design practices, scan methodologies, ATPG, MBIST, JTAG implementation, and test mode timing constraint development will be advantageous for the role.,

As a Senior Member of Technical Staff (SMTS) Silicon Design Engineer at AMD, you will be an integral part of the Circuit Technology team, focusing on DFT Methodology/Architect/RTL execution for high-speed SERDES Phys, Next-gen Memory Phys, and Die-to-Die interconnect IPs. Your responsibilities will include defining the DFX architecture for high-speed PHYs and die-to-die connectivity IP designs, RTL coding, supporting scan stitching, developing timing constraints, assisting with ATPG, and post-silicon bringup. Join a dynamic team that delivers cutting-edge IPs crucial for every SOC developed by AMD. The ideal candidate possesses strong analytical and problem-solving skills with keen attention to detail. You must demonstrate the ability to work hands-on, be a self-starter, a leader, and independently drive tasks to completion. Key Responsibilities: - Lead and define Design for Test/Debug/Yield Features specific to PHYs. - Implement DFX features into RTL using Verilog. - Comprehend DFX Architectures and micro-architectures. - Utilize JTAG (1149.1/1687/1500)/IJTAG, Scan Compression (EDT, SSH), and at-speed scan testing implementation. - Conduct gate-level simulation using Synopsys VCS and Verdi. - Perform Spyglass bringup and analysis for scan readiness/test coverage gaps. - Plan, implement, and verify MBIST. - Assist Test Engineering in planning, patterns, and debug. - Support silicon bring-up and debug. - Develop efficient DFx flows and methodology compatible with front-end and physical design flows. Preferred Experience: - Proficiency in industry-standard ATPG and DFx insertion CAD tools. - Familiarity with industry-standard DFX methodology: e.g., Streaming Scan Network (SSN), IJTAG, ICL/PDL, etc. - Knowledge of SystemVerilog and UVM. - Expertise in RTL coding for DFx logic, including lock-up latches, clock gates, and scan anchors. - Understanding of low-power design flows such as power gating, multi-Vt, and voltage scaling. - Strong grasp of high-performance, low-power design fundamentals. - Familiarity with fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware. - Exposure to post-silicon testing and tester pattern debug is advantageous. - Excellent problem-solving and debug skills across various design hierarchies. Academic Credentials: - BS/MS/PhD in EE/ECE/CE/CS with industry experience in advanced DFx techniques. Join AMD and be a part of a culture that values innovation, problem-solving, and collaboration. Together, we can advance technology and shape the future of computing.,

Solid Experience in DFT Architecture. The candidate should have experience with ATPG, JTAG, BSCAN, BIST and MBIST flows. Experience on Hierarchical DFT techniques using Pattern Retargeting in Tessent flow Strong knowledge of the Tessent Shell environment and Tessent tools The desired candidate must have specific emphasis on the following tools Test Kompress / Fastscan ATPG, MBIST, Boundary scan. Hands on experience in simulating scan patterns and debugging pattern mismatches during verification process Experience in helping to debug failing scan patterns on the ATE is highly desirable. Hands on knowledge in state-of-the-art EDA tools for DFT, design and verification.(Mentor, Cadence, Synopsys) Must be able to simulate and debug MBIST testbenches. Ability to come up with a detailed test plan based on the Arch specs Should be knowledgeable in all SOC functions such as Digital design, STA, Synthesis, PnR, DV and ATE test. The candidate should have prior experience in managing and developing teams Required Qualification B.E / B.Tech / M.E / M.Tech in Electrical / Electronic Engineering.experience-10-16 years Preferred experience of handling 10+ team members. Good understanding and exposure to SoC design and architecture Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects Comfortable with VCS / Verdi and excellent debugging skills Logical in thinking and ability to gel well within a team and be a proactive member of the team. Good communication and leadership skills Excellent team player High Integrity Job Type Full Time Job Location Hubballi

SR. DFT ENGINEER SmartSoC is looking for expert DFT engineers for the development, support, maintenance, Implementation, and Testing of complex components of an ASIC/SOC/FPGA/Board. Desired Skills and Experience- 3 – 10year’s experience in DFT Good experience/concept on all aspects of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan. DFT logic integration and verification. Experience in debugging low coverage and DRC fixes Gate Level ATPG simulation with and without timing. Pattern generation, verification, and delivery to ATE team. Post silicon debug and support on failing patterns. Good experience with tools from Mentor/Synopsis/Cadence. LBIST experience is plus. DFT mode STA and timing closure support. Familiarity with Verilog and RTL simulation Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas

TECHNICAL LEAD – DFT SmartSoC is looking for a smart and enterprising leader with expert knowledge in DFT to come and technically lead a Team. We are looking for someone who is very strong technically and very good at multi-tasking. You will be responsible for leading and managing a team, client communication, and project execution. Job Responsibilities- Lead an internal DFT team, executing projects for an offshore client Manage the team and their technical and leadership growth Manage all interactions with the client Desired Skills and Experience- 7+ years of experience in DFT, mainly Scan Architecture, ATPG & MBIST Experience in planning scan chains, running scan insertion flow Experience in latest Cadence tool set Genus & Modus Experience in ATPG for Stuck@, TFT, IDDQ & Path delay faults with tough coverage targets Experience in MBIST architecture, generation and implementation Experience in AECQ100 requirement standard is a big plus Experience in working with a multi-site team is a big plus Experience in working on critical time-bound projects is a big plus Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas

Candidates need to have good experience in Tessant tools Candidates need to have good experience in ATPG pattern generation and simulation(both timing and no timing) Candidates need to have good experience in Scan insertion Experience should be more than 6+ years Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Experience: 5 to 12 years Location: Bangalore : We are seeking a highly experienced Design Verification Engineer to join our team in Bangalore. The ideal candidate will have 5 to 12 years of experience in IP and SOC verification, with a strong foundation in SystemVerilog (SV) and Universal Verification Methodology (UVM). In addition to standard verification skills, this role requires expertise in CDP (Compressed Data Pattern), GDP (Generic Data Pattern), and DFT DV (Design for Test in Design Verification) methods, including JTAG, MBIST (Memory Built-In Self-Test), SCAN, PG (Pattern Generator), and PM (Pattern Memory). Key Responsibilities: IP and SOC Verification Perform comprehensive IP and SOC verification to ensure the reliability and functionality of integrated circuits. SystemVerilog (SV) and UVM Proficiency Demonstrate a strong understanding of SystemVerilog and Universal Verification Methodology for efficient verification processes. CDP, GDP, DFT DV Expertise Possess expertise in Compressed Data Pattern (CDP) and Generic Data Pattern (GDP) methodologies. Proficiency in Design for Test in Design Verification (DFT DV) techniques, including JTAG, MBIST, SCAN, PG, and PM. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 5 to 12 years of relevant industry experience in IP and SOC verification. Strong knowledge of SystemVerilog (SV) and Universal Verification Methodology (UVM). Expertise in CDP (Compressed Data Pattern), GDP (Generic Data Pattern), and DFT DV (Design for Test in Design Verification) methods, including JTAG, MBIST, SCAN, PG, and PM. If you are a talented Design Verification Engineer with a deep understanding of IP and SOC verification, as well as specialized expertise in CDP, GDP, and DFT DV methodologies, we encourage you to apply. Join our dynamic team and contribute to the advancement of cutting-edge technology. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Qualifications: Bachelor’s or Master’s degree in Electrical Engineering or related field (BE/BTech/M.E/M.Tech) Excellent communication skills, both verbal and written Experience: Minimum of 7 years of experience in the field Proficiency in DVT pattern experience Experience with ATE and functional vectors generation Understanding of Stimgen flow Prior experience with AMD is preferred Skills: Strong debugging skills Experience with MBIST, JTAG, and Phy-loopback NoteCandidates are encouraged to provide a detailed resume showcasing their relevant experience and skills. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore IndiaHyderabad

Number of Open Positions: 7 Experience: 4 to 7+ years Location: Bangalore : We are seeking highly skilled and motivated DFT-DV Engineers to join our dynamic team in Bangalore. As a DFT-DV Engineer, you will play a pivotal role in ensuring the quality and reliability of our digital designs through Design for Test (DFT) and Design Verification (DV) methodologies. The ideal candidates should possess a minimum of 4 to 7+ years of experience in the field, with a strong background in DFT DV flow, JTAG, MBIST, SCAN, PG, PHY-LP, and BSCAN. Key Responsibilities: DFT Implementation: Collaborate with design and verification teams to define and implement DFT strategies and methodologies that enable efficient testing of complex digital designs. Scan and ATPG: Develop and maintain scan insertion, Automatic Test Pattern Generation (ATPG), and compression methodologies to achieve high test coverage. Memory BIST: Implement and verify Memory Built-In Self-Test (MBIST) solutions for embedded memories in the design. JTAG and Boundary Scan: Develop JTAG and Boundary Scan solutions to facilitate efficient testing and debugging of digital designs. Power Management: Work on Power Gating (PG) techniques to optimize power consumption during testing. PHY-LP Integration: Collaborate with PHY teams to ensure seamless integration of low-power features into the design. BSCAN Integration: Implement Boundary Scan (BSCAN) infrastructure to enhance testability and debug capabilities. Verification: Verify DFT features and ensure their correctness through simulation and formal verification. Documentation: Prepare detailed documentation, including DFT specifications, test plans, and reports. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or related field. 4 to 7+ years of experience in DFT-DV engineering. Strong expertise in DFT methodologies, including scan, ATPG, MBIST, JTAG, BSCAN, and PG. Proficiency in industry-standard EDA tools for DFT implementation. Experience with low-power design and PHY-LP integration is a plus. Excellent problem-solving skills and attention to detail. Strong communication and teamwork skills. If you are a proactive and results-oriented engineer with a passion for ensuring the quality and reliability of digital designs, we encourage you to apply. Join us in our mission to develop cutting-edge technology and make a significant impact in the semiconductor industry. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

1.DV 2.PD 3.DFT 4.RTL 5.PD(VLCP)/(EMIR) 6.PV 7.STA/Synthesis

Sr. Staff/ Manager, DFT Responsibilities: Responsible for implementing the hardware Memory BIST (MBIST) features that support ATE, in-system test, debug and diagnostics needs of the memories in design. Work closely with the design, design-verification, and backend teams to enable the integration an validation of the test logic in all phases of the design, and backend implementation flow. The job requires the candidate to have good scripting skills and the ability to design and debug with minimal oversight. Involve in high quality pattern release to test team and support silicon bring-up and yield improvement. Requirement: ASIC Design DFT engineer with related work experience with a broad mix of technologies including: Knowledge of the latest state of the art trends in Memory testing and silicon engineering Hands on experience in JTAG & IJTAG protocols, MBIST and scan architectures. Verification skills including System Verilog, LEC and validating test timing of the design Experience working with gate-level simulations, and debug with VCS and other simulators Understanding the testbench in System Verilog, UVM/VMM is addon Post-silicon validation and debug experience, ability to work with ATE patterns Strong verbal communication skills and ability to thrive in a dynamic environment Scripting skills: Python/Perl

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Be a member of the team that plays a significant role in ensuring the quality of Connectivity SoCs through structured DFT, Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST) techniques. Primary responsibilities will include , Interfac e with design team to ensure DFT design rules and coverages are met. Generating high quality manufacturing ATPG test patterns for stuck-at (SAF) , transition fault (TDF ) models through the use of on-chip test compression techniques. M BIST verification (including repair), test pattern generation through Mentor tool. ATPG (SAF, TDF) and MBI ST verification using unit delay and min/max timing corner s imulations . Work with the P roduct /Test engineering teams on the delivery of manufacturi ng test patterns for ATE . Responsible for supporting post silicon debug effort, issue resolution . Responsible for Diagnostic Tool generation for ATPG , MBIST and bring-up on ATE. Developing, enhancing and maintaining scripts as necessary Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 1-6 year s experience in ASIC/DFT - simulation and Silicon validation Detailed knowledge on DFT concepts, pattern simulation, Silicon debug and yield enhancement In depth knowledge and hands-on experience in ATPG - coverage analysis. In depth knowledge of Memory verification, repair and failure root-cause analysis. Experience with any of these tools is required ATPG - TestKompress MBIST - Mentor ETVerify Simulation - VCS (preferred), modelsim . Expertise in scripting languages such as Perl , shell, etc. is an added advantage Ability to work in an international team, dynamic environment with good communication skills Ability to learn and adapt to new tools , methodologies. Ability to do multi-tasking & work on several high priority designs in parallel Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Be a member of the team that plays a significant role in ensuring the quality of Connectivity SoCs through structured DFT, Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST) techniques. Primary responsibilities will include, Interface with design team to ensure DFT design rules and coverages are met. Generating high quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models through the use of on-chip test compression techniques. MBIST verification (including repair), test pattern generation through Mentor tool. ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations. Work with the Product/Test engineering teams on the delivery of manufacturing test patterns for ATE. Responsible for supporting post silicon debug effort, issue resolution. Responsible for Diagnostic Tool generation for ATPG, MBIST and bring-up on ATE. Developing, enhancing and maintaining scripts as necessary Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 2-6 years experience in ASIC/DFT-simulation and Silicon validation Detailed knowledge on DFT concepts, pattern simulation, Silicon debug and yield enhancement In depth knowledge and hands-on experience in ATPG -coverage analysis. In depth knowledge of Memory verification, repair and failure root-cause analysis. Experience with any of these tools is required ATPG - TestKompress MBIST - Mentor ETVerify Simulation - VCS (preferred), modelsim. Expertise in scripting languages such as Perl, shell, etc. is an added advantage Ability to work in an international team, dynamic environment with good communication skills Ability to learn and adapt to new tools, methodologies. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement. Roles and Responsibilities o Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. o Work closely with design/verification teams within CPU to develop comprehensive test plan. o Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. o Verify power intent through use of methodologies like UPF. o Work closely with system architects, software teams and Soc team to validate system use cases. o Work closely with emulation team to enable verification on emulators and FPGA platforms. o Debug and triage failures in simulation, emulation and/or Silicon. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. o BE/BTech degree in CS/EE with 3+ years experience. o Experience in power management verification. o Implementation of assembly and C language embedded firmware. o Experience in C/C++, scripting languages, Verilog/system Verilog. o Strong understanding of power management features in CPUs and CPU based Socs. o Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc. Preferred Requirements: o Good Understanding of CPU architectures and CPU micro-architectures. o In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture o Experience with advanced verification techniques such as formal and assertions is a plus o Knowledge and verification experience in DFT and structural debug concepts and methodologiesJTAG, IEEE1500, MBIST, scan dump, memory dump is a plus Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Minimum 4 to 6 years of work experience in ASIC RTL Design. Strong expertise in MBIST insertion, Scan insertion, and ATPG. Proficiency with SMS MBIST insertion tool is mandatory. Must have hands-on experience with handling sub systems with multiple memory types and grouping. Additional experience in memory redundancy, BIRA analysis, and repair solutions is highly desirable. Solid understanding of multi-memory bus interfaces and functional safety BIST requirements is a strong advantage. Exposure to Automotive System Designs, Memory Controller Designs, and Microprocessors is a plus. Experience in low power design and synthesis/timing concepts for ASICs is preferred Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Additional Qualcomm Global CAD Organization is looking for DFT/ATPG Methodology development lead to develop DFTCAD methodologies for Qualcomms 5G products in advanced FinFET semiconductor process nodes. In this role, you will be a member of a global technical team working with SOC Design, DFT, Product and Test, and Diagnostics teams, as well as EDA Tool vendors to develop world-class DFT methodology solutions. Key Responsibilities Lead DFT ATPG flow development, integration, and deployment efforts independently, collaborating with DFT teams, EDA vendors Drive new ATPG methodology, new tool evaluation, design DoEs, both within Qualcomm and partnering with EDA vendors. Develop optimized recipes for improving test quality, reducing test cost, DFT cycle time, pattern simulation runtimes. Qualifications/Experience BE/B.Tech, ME/MTech/MS in Electrical/Electronics/Computer science Engineering 4-6 years demonstrated experience in VLSI EDA/CAD methodology development in areas of DFT, Scan/ATPG Skills Required Strong knowledge of DFT domain specifically on Scan, ATPG and ATPG pattern simulations Strong development skills in TCL, Python Good understanding of SOC DFT Flow, ATE Flow and practices. Familiarity with standard software development process, systems including Configuration Management, QA, Release and Support Ability to plan and execute formal projects, deliverables. Ability to work with multiple WW teams in a fast paced and dynamic environment. Must be a team player, ability to multi-task, with attention to details. Keywords : DFT, ATPG, Scan, VLSI Test, Tessent, TetraMAX, TestMAX, MBIST, SMS Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 3+ years experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG -In depth knowledge of DFT concepts. -In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. -Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors. -Knowledge of equivalence check and RTL lint tool (like spyglass). -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem-solving skills Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Primary skills: ASIC / DFT / Simulation / Validation Mandatory skills: VLSI Design For Testability - DFT & worked in at least one Full chip DFT Experience with tools: ATPG - TestKompress, MBIST - MentorETVerify, Simulation - VCS (preferred), ModelSim

Required Technical and Professional Expertise inDFT Minimum 9 to 13 years of relevant experience . Proficient inDFTarchitectures & methodologies that includes Scan insertions, ATPG, MBIST, JTAG, etc. Sound knowledge ofDFTtools/methodology from cadence /Synopsys/Mentor tools Good Experience in Python/Perl/TCL scripting