155 Mbist Jobs

About Marvell Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Data Center Engineering Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. This group provides technology development, EDA/methodology development and IP/Chip design development. India DFT team is a key part of Global DFT community with global ownership and responsibility for delivering generic and more advanced custom DFT architecture solutions, methodology and design. You will be working with this team to directly enable customer DFT requirements for Custom and Compute Businesses. What You Can Expect The position will be responsible for Architecting, Leading and implementing DFT / Test on complex IP and SOC for multiple Custom/Compute ASIC/SoC designs The execution involves Design-for-Test Architecture definition, Implementation of various DFT/DFX features, Validation , IP-DFT, STA, pattern generation & Post-Silicon Bringup and Debug for various designs/IPs in Custom/Compute space. In this position, the responsibility also includes mentoring, guiding and driving a small team of engineers enabling them for scaling across multiple designs. The position also involves definition and enhancement of DFT methodologies and tools to be able to benchmark them and enable new methodologies in the domain of DFT/Test. What We&aposre Looking For Bachelors degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience. Masters degree and/or PhD in Computer Science, Electrical Engineering or related fields with 13+ years of experience. Hands on working experience in various stages of DFT-Execution SCAN-Insertion/MBIST/ATPG/Validation/STA/IP-DFX/Post-Silicon Bringup/Debug Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at-least couple of Designs. Strong fundamentals in Digital Circuit Design and Logic Design is required Understanding of DFT Flows and Methodologies and Experience with Cadence/Mentor/Synopsys Tool set (Genus,Modus,NCSim / DC,Tessent,Spyglass/Tmax) Prior experience in ASIC design is a plus Scripting skills using PERL, Tcl and C-Shell is plus Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. Were dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what its like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Show more Show less

1. Minimum of three years of hands-on Test Development experience (DFT, EDA tools, etc..) 2. Solid knowledge & experience in defining test solutions for multi-million gate SOC (Scan & MBIST) with Mixed Signal IPs (PLL, High Speed SERDES, DDR) 3. Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test 4. Strong understanding of relationships between Hardware, Firmware and Software in FPGA and/or multi-processors SOC. Past experience in leading the team to successful silicon bring-up and problem solving in a complex system 5. Strong planning, project, and people management skills required. Must have experience developing managers and individual contributors 6. Experienced hands-on technical manager not afraid to dig into details to provide technical direction Proven track record of delivering results and meeting quality, cost, and time-to-market objectives 7. Ability to collaborate with overseas colleagues to define strategy, plan, and execute across the larger, global organization 8. Stakeholder influencing and people skills must be excellent. 9. Needs to be able to set aggressive goals and manage risks effectively 10. Must have a thorough understanding of tool development methodology. 11. Ability to manage software development tasks associated with specifying, developing, scheduling, and debugging according to current and future tool requirements. 12. MS or Ph.D. Engineering degree (EE or equivalent) with 3-7 years semiconductor industry experience.

About MIPS MIPS is a leader in high-performance RISC-V CPU IP, enabling innovation across automotive, AI, data center, and embedded markets Our engineering teams are building the next generation of compute solutions, and we are looking for passionate talent to join us in shaping the future of semiconductors, Position Overview The DFT Manager leads and develops the engineering team responsible for designing and deploying advanced Design-for-Test solutions in semiconductor chip development This role focuses on building robust DFT architectures?including ATPG, MBIST, LBIST, analog test solutions?and implements repeatable methodologies and flows that ensure rapid, optimized test pattern generation and efficient project execution, Key Responsibilities Lead, mentor, and manage the DFT engineering team, overseeing daily operations and technical development, Define and deploy DFT architecture for chips with features such as Automatic Test Pattern Generation (ATPG), Memory Built-In Self-Test (MBIST), Logic Built-In Self-Test (LBIST), and analog test solutions, Develop and optimize test pattern generation methodologies, prioritizing test time reduction and manufacturing efficiency, Establish and maintain standardized, repeatable DFT methodologies and flows to consistently achieve fast turnaround and reliable results across projects, Collaborate cross-functionally to integrate DFT features and requirements throughout the silicon development lifecycle, Automate test program, script development for maximum coverage and reduced test cost, Continuously analyze test performance data and apply lessons learned for iterative improvement, Promote innovation and continuous improvement by evaluating new trends, tools, and best practices, Document DFT specifications, standards, and re-use strategies for knowledge sharing and future use, Required Qualifications Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field, 8+ years of hands-on DFT experience plus proven leadership of DFT teams on SoCs, Expertise in test pattern generation, ATPG, MBIST, LBIST, analog test development, and scan insertion, Significant experience optimizing test time through efficient DFT strategies and tool use, Proven ability to design and implement repeatable DFT flows and reusable test IP, Proficiency with EDA tools (Synopsys, Cadence, Mentor Graphics), and scripting (Python, Perl, TCL), Strong analytical, organizational, leadership, and communication skills, Desired Attributes Strategic thinker who translates customer, product requirements into practical, innovative test solutions, Inspirational leader focused on team growth, technical excellence, and methodology re-use, Proactive, detail-oriented professional committed to efficiency, quality, and process improvement, Why Join MIPS Be part of a team driving innovation in RISC-V CPU IP and SoC development, Work on cutting-edge semiconductor designs with global impact, Collaborative, growth-focused environment with opportunities for innovation and leadership, Show more Show less

Minimum of ten years of hands-on Test Development experience (DFT, EDA tools, etc..) Solid knowledge & experience in defining test solutions for multi-million gate SOC (Scan & MBIST) with Mixed Signal IPs (PLL, High Speed SERDES, DDR) Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test Strong understanding of relationships between Hardware, Firmware and Software in FPGA and/or multi-processors SOC. Past experience in leading the team to successful silicon bring-up and problem solving in a complex system Strong planning, project, and people management skills required. Must have experience developing managers and individual contributors Experienced hands-on technical manager not afraid to dig into details to provide technical direction Proven track record of delivering results and meeting quality, cost, and time-to-market objectives Ability to collaborate with overseas colleagues to define strategy, plan, and execute across the larger, global organization Stakeholder influencing and people skills must be excellent. Needs to be able to set aggressive goals and manage risks effectively Must have a thorough understanding of tool development methodology. Ability to manage software development tasks associated with specifying, developing, scheduling, and debugging according to current and future tool requirements. MS or Ph.D. Engineering degree (EE or equivalent) with 3-10 years semiconductor industry experience.

• Should have worked hands-on extensively on full chip DFT design, • implementation, vector generation/verification, JTAG, Boundary scan & Simulation. • Experience with Scan, Compression, ATPG & Simulations with Mentor/Synopsys/ Cadence tools. Required Candidate profile • Participated in Successful Tapeouts of SoC/ASIC chips at 14nm or below. • Develop/Automate flows & scripts in Perl/Tcl to enhance the DFT methodologies & process. • Logic BIST knowledge is a plus.

About The Role About The Role Will be responsible for Designing and Implementing DFT techniques. Should hava a good understanding of Memory BIST/Scan /OnChip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/LogicBIST on complex SOCs to improve testability. Test Modes implementation and verification, scan insertion including on-chip compression. Implementing, integrating and verifying memory BIST and boundary scan. ATPG Test vector (Stuck-at/At-speed/Path delay/SDD/IDDQ/Bridging fault) generation with high test Coverage and simulations at gate level with timing (SDF). Basic understanding of complete SOC design and flow. Cross functional teams interaction for issue resolution. Participate in driving new DFT methodology and solutions to improve quality, reliability and insystem test and debug capability. Hiring candidate with these specific personal characteristic and qualifications. Mentoring junior engineers and drive innovation/automation. Excellent in problem solving and analytical skills. Excellent communication, team work and networking skills. Primary Skills Should Have Good understanding of Design and DFT Architecture. Should have been part of atlest 3 Tapeout SoC. Well Versed with ATPG Tools & MBIST Tools. Secondary Skills Team Player, Strong Business Acumen with understanding of organizational issues (conflict resolution between stakeholders). Familiarity with Desired Flexibility and adaptability with respect to project management.

Job Description: We are looking for DFT Engineers with 3+ years of experience in Scan, MBIST, and ATPG. The role involves developing and implementing advanced DFT methodologies to ensure testability and high-quality silicon. Key Responsibilities: Hands-on experience with Scan insertion and Scan DRC/Coverage debug. Strong background in ATPG pattern generation and fault coverage analysis. Expertise in Gate-level simulations (Zero delay / Timing delay simulations). Worked on JTAG protocols. Experience in MBIST insertion, verification, and debug. Proficiency in Perl/Tcl scripting for automation of flows. Familiarity with timing verification, formal verification, and PD flow (a plus). Ability to debug and optimize DFT implementation for quality silicon.

Hiring DFT Engineers (412 yrs) for full-chip ATPG, MBIST, silicon debug & ATE delivery. Skills: TestKompress, ETVerify, VCS, Perl/Shell. Locations: Bangalore, Hyderabad, Cochin, Pune. Join a global ASIC design team driving quality silicon!

Job Description Will be responsible for Designing and Implementing DFT techniques. Should hava a good understanding of Memory BIST/Scan /OnChip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/LogicBIST on complex SOCs to improve testability. Test Modes implementation and verification, scan insertion including on-chip compression. Implementing, integrating and verifying memory BIST and boundary scan. ATPG Test vector (Stuck-at/At-speed/Path delay/SDD/IDDQ/Bridging fault) generation with high test Coverage and simulations at gate level with timing (SDF). Basic understanding of complete SOC design and flow. Cross functional teams interaction for issue resolution. Participate in driving new DFT methodology and solutions to improve quality, reliability and insystem test and debug capability. Hiring candidate with these specific personal characteristic and qualifications. Mentoring junior engineers and drive innovation/automation. Excellent in problem solving and analytical skills. Excellent communication, team work and networking skills. Primary Skills Should Have Good understanding of Design and DFT Architecture. Should have been part of atlest 3 Tapeout SoC. Well Versed with ATPG Tools & MBIST Tools. Secondary Skills Team Player, Strong Business Acumen with understanding of organizational issues (conflict resolution between stakeholders). Familiarity with Desired Flexibility and adaptability with respect to project management

General Summary: Minimum 4 to 6 years of work experience in ASIC RTL Design. Strong expertise in MBIST insertion, Scan insertion, and ATPG. Proficiency with SMS MBIST insertion tool is mandatory. Must have hands-on experience with handling sub systems with multiple memory types and grouping. Additional experience in memory redundancy, BIRA analysis, and repair solutions is highly desirable. Solid understanding of multi-memory bus interfaces and functional safety BIST requirements is a strong advantage. Exposure to Automotive System Designs, Memory Controller Designs, and Microprocessors is a plus. Experience in low power design and synthesis/timing concepts for ASICs is preferred Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

You have a great opportunity as a DFT Lead Engineer with 6+ years of experience at a work location in Bangalore or Hyderabad. As a DFT Lead Engineer, you will be responsible for the DFT implementation of the latest products, including scan insertion, ATPG, LBIST, and MBIST. Your role will involve verifying the DFT implementation and delivering test patterns for production testing. Additionally, you will support Silicon bring-up activities to ensure the highest stability of the test pattern. In this position, you will contribute to the overall microcontroller DFT methodology and coordinate DFT work packages. You will be required to engage in hands-on work, provide status reports, and collaborate with project management, layout team, and test engineering. Proficiency with Synopsys tools such as TetraMAX, Verdi, and DFT Compiler is essential for this role. The ideal candidate should have a solid understanding of scan chains, stuck-at/fault models, and test coverage. If you are looking for a challenging role that allows you to showcase your DFT expertise and work on cutting-edge technologies, this position is perfect for you.,

We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBM’s chip design team. As a member of DFT team, you will be required but not restricted to insertion, pattern generation, simulation, validation, characterization, delivery to TAE, IBM’s Hardware Bring-up and Silicon Debug Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Hands-on experience in DFT on complex designs involving scan insertion, compression, MBIST, ATPG, simulations and IP integration and validation. Proven expertise in analysing and resolving DRCs/TSVs . Hands-on experience in pattern generation for various fault models, pattern retargeting and debugging techniques to address low coverage issues. Hands-on experience with Gate-Level DFT verification, both with and without timing annotations. Well versed with industry standard test techniques and advanced DFT features like SSN, IJTAG, IEEE 1500, Boundary scan , LBIST and STA constraint delivery . Hands on experience on industry standard tools used for DFT features Proficiency in scripting languages such as TCL, Perl or Python to automate design and testing tasks. Worked with cross functional teams like design, STA & tester teams for ensuring top quality of DFT deliverables and DFT support and hand offs. Excellent analytical and problem-solving skills, with a keen attention to detail. Strong communication and collaboration skills, with the ability to work effectively within cross-functional teams Preferred technical and professional experience Fundamentals in micro controller architecture, embedded firmware, functional verification and RTL design Experience working with ATE engineers for silicon bring up, silicon debug and validation. Experience in Asics/processor flow and post silicon validation

Role & responsibilities Handling hierarchical scan insertion ATPG flow. Integration and Verification of MBIST at RTL level. RTL Integration, Verification, gate level Coverage and GLS enablement for LBIST. Implementation and Verification of IEEE1149.1 JTAG, IJTAG standards. Post silicon debug activities for DFT patterns. Collaboration with RTL design, Physical design and verification teams will be a daily aspect of the role. Preferred candidate profile Degree/PG in Electrical/Electronic Engineering, Computer Engineering or Computer Science. At least 12+ years of experience in related domains and have working knowledge of industry standard digital EDA toolkits. Must be conversant on EDA tools such Tessent, Genus, FC, VCS and Conformal/Formality etc. Strong scripting skills for Automation and Flow development using PERL/TCL/Python. Cando attitude, openness to new environment, people and culture. Strong communication skills (written and verbal), problem solving, attention to detail, commitment to task, and quality focus. Ability to work independently and as part of a team. Mentor and guide junior engineers in DFT.

We are seeking an experienced and highly skilled Senior SOC Design for Test Engineer with aminimum of 5 years of hands-on experience in SOC Design for Test. As a key member of our team, you will play a pivotal role in ensuring the testability, manufacturability, and quality of our cutting-edge System on Chip designs Key Responsibilities Lead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution coverage, manufacturability, and quality plans. Develop full chip and block level DFT implementation from the DFx Specifications and product coverage, quality, and manufacturability goals. Define and implement Test controllers at top level and block level, fuse controllers, test clocking strategy, chip I/O test strategy and HSIO test strategy. Define JTAG TAP, boundary scan, I/O Test JTAG access, IEEE1687 iJTAG network and instrument design and implementation. Define the Test Interface for each of the P&R IP blocks for Scan, MBIST and other test interfaces. Define hierarchical block isolation, Test clocking and On Chip Clock controllers and reset methodology. Define scan and MBIST timing at the top level and block level timing. Analyse block level RTL or gates to ensure that scalability and coverage is satisfied as per the design goals. Ensure that DFT is provided to fix the DFT violations to ensure that the design goals are meet. Analyse compression requirements for each of the blocks, define Intest and Extest compression requirements and define the requirements for compression engines. Synthesize compression engines for each of the blocks. Create the collaterals for compression for the IPs. Block level scan insertion as well as development of the scan wrappers for the blocks. Do scan insertion on the blocks, analyse scan DRC, implement DFT fixes. Create scan protocol files for designs, create scan inserted netlist, create scan definitions as well as scan definition files for PD. Perform ATPG on the scan inserted netlist, analyse DRC and coverage violations. Deep knowledge of different scan models Stuck-at, transition test, path-delay, bridging, cell aware, small-delay transition, IDDQ test etc. Ability to analyse coverage for each of the model types. Running GLS with or without timing for the scan vectors. Ability to debug the failures and working with timing and PD teams to fix the timing issues. Understanding of pattern delivery to the post-silicon test engineering teams. Delivering to the Test engineering the Test pin muxing and other full chip requirements for the Test Engineering Team. Understanding tester requirements and delivering the patterns in the formats that the tester teams needs. Implement pattern retargeting. Create grey box models for blocks. Coverage analysis of full chip consolidating Intest and Extest patterns. Knowledge of Top level scan architecture and creating flow to create pattern retargeting. Knowledge of Streaming Scan Network and other Top level scan pin sharing and implementing the block to top level pattern generation for this flow. Implementing Memory Testing and MBIST. Knowledge of Memory defect models and test algorithms. Knowledge of memory bit mapping and redundancy analysis. Implementing memory repair and fuse sharing among various memory. Knowledge of LogicBIST with Test point insertion, X-blocking. Full chip DFT delivery for tapeout including but not limited to DFT netlist verification, pattern delivery, Tester requirements. Debug DFT patterns post silicon, ability to analyse chain test patterns for failures, scan pattern failures. Analyse MBIST pattern failures, yield and repair debug. Ability to perform volume diagnostics on the parts to isolate and improve the patterns. Requirements Bachelors degree in computer science, Electrical/Electronics Engineering, or related field. OR masters degree in computer science, Electrical/Electronics Engineering, or related field. OR PhD in Computer Science, Electrical/Electronics Engineering, or related field. 5+ years of hands-on experience in SOC Design for Test. Expertise in DFT tools and flows in scan intertion, ATPG, GLS simulation, diagnosis flows. Prior experience working on IP level and SOC level DFT projects. Proficient in DFT tools from Siemens (Tessent), Synopsys DFTmax, Tetramax, Spyglass DFT advisor, Genius DFT, Modus, VCS, Xcelium etc. Worked in full chip design or complex IP delivery in the area of DFT. Experience in post silicon debug, diagnosis and yield enhancements is a plus.

You are an experienced Design-for-Test (DFT) Engineer with over 5 years of hands-on expertise in DFT methodologies and implementation. You should possess a solid understanding of MBIST, Scan, ATPG, and simulation concepts, along with a proven track record of executing industry-standard DFT flows. Your key responsibilities will include performing MBIST insertion, Scan insertion, and ATPG pattern generation using industry-standard EDA tools. You will be conducting MBIST simulations and analyzing results using tools from Cadence, Siemens Tessent, or Synopsys. Additionally, you will execute zero delay and SDF-based timing simulations, and efficiently debug issues using simulators such as VCS, NCSim, or Xcelium in GUI mode. Working with fault models including Stuck-at Faults and Transition Delay Faults (TDF) will be part of your role. You will also be responsible for optimizing and improving scan test coverage using established DFT techniques. The required skills and experience for this position include 5+ years of relevant experience in DFT, hands-on expertise with tools from Cadence, Siemens Tessent, and Synopsys, proficiency in debugging and analysis using VCS, NCSim, or Xcelium, strong analytical and problem-solving skills, and good communication and collaboration skills. Preferred qualifications for this role include experience in DFT automation using scripting languages like TCL, Perl, or Python, and prior exposure to automotive, networking, or high-performance computing SoCs is considered a plus.,

6 to 12 years' experience in ASIC/DFT - simulation and Silicon validation, DFT concepts, pattern simulation, Silicon debug and yield enhancement ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations

We are looking for a skilled DFT design engineer with strong expertise in scan insertion, MBIST, JTAG, ATPG, and boundary scan.

The Manager, DFT will be responsible for implementing the hardware Memory BIST (MBIST) features that support ATE, in-system test, debug, and diagnostics needs of the memories in design. You will work closely with the design, design-verification, and backend teams to enable the integration and validation of the test logic in all phases of the design and backend implementation flow. The job requires you to have good scripting skills and the ability to design and debug with minimal oversight. You will also be involved in high-quality pattern release to the test team and support silicon bring-up and yield improvement. The ideal candidate for this role should be an ASIC Design DFT engineer with 10+ years of related work experience encompassing a broad mix of technologies. You should have knowledge of the latest state-of-the-art trends in Memory testing and silicon engineering. Hands-on experience in JTAG & IJTAG protocols, MBIST, and scan architectures is essential. Your verification skills should include System Verilog, LEC, and validating test timing of the design. Experience working with gate-level simulations, and debug with VCS and other simulators is required. Understanding the testbench in System Verilog, UVM/VMM is considered an addon. Post-silicon validation and debug experience, along with the ability to work with ATE patterns, is a crucial aspect of this role. Additionally, you should possess strong verbal communication skills and the ability to thrive in a dynamic environment. Proficiency in scripting skills such as Python/Perl is also required for this position.,

Career Opportunity with Burckhardt Compression We are seeking motivated and experienced professional who can effectively contribute to the role deliverables connected with position below In this position you can actively participate to our growth and make a significant impact in a fast-paced environment as: Position: Manager Other IT Applications Location: Pune Your contributions to organisation's growth: Manage the Other IT Applications team across geographies and time zones, Support strategic recruitment and role alignment, while collaborating with HR and matrix managers to define role requirements, conduct interviews, and onboard talent aligned with project needs, Be responsible for our Other IT Applications solution: daily operations, roadmap and strategy, Act as a delivery manager for all delivered solutions: change requests, projects, incident management, process optimization/automation, user support, etc Provide leadership and strategy to the Other IT Applications team, Overlook and monitor team delivery Review, secure, and monitor operational performance in collaboration with other functional managers, Develop and maintain functional and personal competencies of the team, Monitor team morale, conduct regular check-ins, and support initiatives like recognition programs, and career progression plans, Establish solid working relationships with business stakeholders and an understanding of segment business models, Advise senior stakeholders of capabilities and possible solutions to business challenges, Represent the team perspective within the GSC, Global Architecture, Business Process Ecosystem, User community, relevant Boards, and Projects, Apply industry best practices around solutions' demand management, change management, agile operations, and contribute to the establishment of a group wide efficient operating model, Raise standards and promote the Other IT Applications landscape to the function heads for broad buy-in, Drive cultural change towards user adoption of digital processes and tools, Manage suppliers, contracts, and budget allocated to the Other IT Appl landscape, in close collaboration with other delivery managers, the architecture team, Procurement, Legal, etc Actively support the transformation of the Other IT Applications architecture to cloud Expertise you have to bring in along with; Degree in relevant field such as computer science or business administration or equivalent professional qualification, Built, led and developed an application management team, In depth knowledge in application management, Significant experience of managing IT applications, incorporating support and project management, including a number of implementations, Proven track record in system design, setup, implementation and rollout in a multi-geography setup, Significant experience managing teams comprising permanent staff, consultants, and contractors (onand possibly offshore), Leadership experience with globally distributed cross-functional teams, Experience working with senior leadership and confidence in communication at all levels Special requirements: Ability to define key questions and provide answers on optimization of processes and applications, Ability to thrive in a dynamic and changeable industrial environment, Strong business partner, good understanding of the company's business and processes We Offer We have a very free culture, inspiring employees to involve in various activities of their interests, Our flexible working models will allow you to combine private interests with work, Employee Connect, Engagement events and feedback culture enhances our reach and gives us an opportunity to continuously improve, Performance and appreciation awards, Sports activities and Klib Library to energize you, We proudly do encourage diversity and inclusion in thoughts and in spirit, A winner of GreenCo Gold and other various ISO certifications, we encourage you to inhibit the same to contribute in a much greener tomorrow! We do aspire to be Great Place to Work soon to provide you an enticing career with us, HR Team Burckhardt Compression India Burckhardt Compression creates leading compression solutions for a sustainable energy future and the long-term success of its customers The Group is the only global manufacturer that covers a full range of reciprocating compressor technologies and services Since 1844, its passionate, customer-oriented and solution-driven workforce has set the benchmark in the gas compression industry,

As an Engineer (DFT) at eInfochips located in Bangalore, India, you will be responsible for hands-on experience in various DFT aspects including Scan insertion, MBIST and JTAG, ATPG, and Pattern validation at both block level and Fullchip level. You will be proficient in the usage of Synopsys tools such as DFT MAX and TetraMAX, as well as Cadence tools like RTL Compiler, Encounter Test, modus, and Janus. Additionally, experience with Mentor Graphics tools like Tessent tool chain, TestKompress, Debussy, VCS/Questa/IUS, and PT tool from Synopsys will be advantageous. This is a full-time position falling under the category of Engineering Services.,

We are seeking a Negotiator, Global Contract Services to join our Markets Legal master agreement negotiation team (Global Contract Services) in Pune, India In this role, you will be responsible for drafting, negotiating and executing master and collateral agreements and ancillary documentation (e g , ISDAs, GMRAs, GMSLAs, Futures Agreements) in support of our global Markets client-facing franchise You will conduct diligence, negotiate with clients directly and engage extensively with internal stakeholders such as credit risk, sales and trading, collateral management, treasury, tax and client onboarding This is an exciting opportunity to join the largest team within Barclays Legal, To be successful as a ,Negotiator Global Contract Services you should have: Experience within the financial industry, with a focus on derivatives master agreements Strong negotiation and portfolio management skills Familiarity with collateral arrangements and credit support annexes Familiarity with industry netting and collateral opinions Strong grasp of regulatory requirements and jurisdictional nuances, e g Initial Margin requirements/Variation Margin requirements under the various regulatory regimes Ability to manage risk and controls effectively for the team, by applying applicable risk frameworks and embedding a positive risk culture We are looking for someone flexible to work UK hours Basic /Essential Qualifications Tertiary/University or bachelors degree (LLB or equivalent), Strong legal analytical and drafting skills, communication, time management and organizational skills You may be assessed on the key critical skills relevant for success in role, such as risk and controls, change and transformation, business acumen strategic thinking and digital and technology, as well as job-specific technical skills, The location is Pune , Purpose of the role To ensure that the operations in the country or region are conducted in compliance with applicable laws and regulations, and to help the bank manage legal and reputational risks associated with these activities, Accountabilities Development and implementation of best practice legal strategies for risk management and compliance, Legal advice and support to the bank's country coverage teams on a wide range of legal issues, including regulatory compliance, risk management, project management and transactional matters, Representation of the bank in legal proceedings related to its operations in the country or region, such as litigation, arbitration, and regulatory investigations, Creation and review of legal documents such as loan agreements, security documents, and other financing documents to ensure compliance with applicable laws and regulations, Legal research and analysis to stay up to date on changes in laws and regulations that may impact the bank's operations in the country or region, Developing and delivering training programmes to educate employees on legal and regulatory requirements related to the bank's operations in the country or region, Pro-active identification, communication, and provision of legal advice on applicable laws, rules and regulations (LRRs) Keeping up to date with regards to changes to LRRs in the relevant coverage area Ensuring that LRRs are effectively allocated to, and adequately reflected within, the relevant policies, standards and controls, Assistant Vice President Expectations To advise and influence decision making, contribute to policy development and take responsibility for operational effectiveness Collaborate closely with other functions/ business divisions, Lead a team performing complex tasks, using well developed professional knowledge and skills to deliver on work that impacts the whole business function Set objectives and coach employees in pursuit of those objectives, appraisal of performance relative to objectives and determination of reward outcomes If the position has leadership responsibilities, People Leaders are expected to demonstrate a clear set of leadership behaviours to create an environment for colleagues to thrive and deliver to a consistently excellent standard The four LEAD behaviours are: L Listen and be authentic, E Energise and inspire, A Align across the enterprise, D Develop others, OR for an individual contributor, they will lead collaborative assignments and guide team members through structured assignments, identify the need for the inclusion of other areas of specialisation to complete assignments They will identify new directions for assignments and/ or projects, identifying a combination of cross functional methodologies or practices to meet required outcomes, Consult on complex issues; providing advice to People Leaders to support the resolution of escalated issues, Identify ways to mitigate risk and developing new policies/procedures in support of the control and governance agenda, Take ownership for managing risk and strengthening controls in relation to the work done, Perform work that is closely related to that of other areas, which requires understanding of how areas coordinate and contribute to the achievement of the objectives of the organisation sub-function, Collaborate with other areas of work, for business aligned support areas to keep up to speed with business activity and the business strategy, Engage in complex analysis of data from multiple sources of information, internal and external sources such as procedures and practises (in other areas, teams, companies, etc) to solve problems creatively and effectively, Communicate complex information 'Complex' information could include sensitive information or information that is difficult to communicate because of its content or its audience, Influence or convince stakeholders to achieve outcomes, All colleagues will be expected to demonstrate the Barclays Values of Respect, Integrity, Service, Excellence and Stewardship our moral compass, helping us do what we believe is right They will also be expected to demonstrate the Barclays Mindset to Empower, Challenge and Drive the operating manual for how we behave,

You should have a minimum of 9 to 13 years of relevant experience in Design for Testability (DFT). Your expertise should include knowledge of DFT architectures and methodologies such as Scan insertions, ATPG, MBIST, JTAG, etc. It is essential to be proficient in DFT tools and methodologies from Cadence, Synopsys, or Mentor tools. Additionally, you should have experience in scripting languages like Python, Perl, or TCL.,

| Location :Bangalore Note : These are fulltime roles and Notice can go from immediate -60 Days Max Job Descriptions for DFT: Required Technical and Professional Expertise in DFT Minimum 9 to 13 years of relevant experience. Proficient in DFT architectures & methodologies that includes Scan insertions, ATPG, MBIST, JTAG, etc. Sound knowledge of DFT tools/methodology from cadence /Synopsys/Mentor tools Good Experience in Python/Perl/TCL scriptingRole & responsibilities Preferred candidate profile

You have an exciting opportunity as a DFT Lead with Synopsys Tools in Bangalore. With over 10 years of experience in DFT, you are well-versed in all aspects including SCAN/ATPG, MBIST, and Boundary Scan. Your expertise lies in DFT logic integration and verification, along with debugging low coverage issues and DRC fixes. You have hands-on experience in gate-level ATPG simulation with and without timing, as well as pattern generation, verification, and delivery to the ATE team. Post silicon, you excel in debug and support on failing patterns, ensuring smooth operations. Your proficiency in tools like TestMAX from Synopsys is commendable. You have a knack for developing and automating flows and scripts in Perl/Tcl to enhance DFT methodologies and processes. Your problem-solving and debugging skills are top-notch, and your proactive nature sets you apart. In addition to technical skills, you have experience in leading junior teams, mentoring/training, and project leadership. Your extensive experience of over 10 years makes you a valuable asset to the team. If you are ready to take on this challenging role, please share your resume or refer a suitable candidate to krishnaprasath.s@acldigital.com. You can also reach out at 6380023419 for further details.,

The Opportunity We&aposre looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrows future by accelerating the critical data communication at the heart of our digital world from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. Role Summary: As a DFT engineer at Alphawave Semi, you will be working on end-to-end Custom Silicon Design cycle, from DFT-architecture planning to delivering qualified Si parts to our customers. You will be using some the best industry-standard tools and Alphawave specific workflows to implement full chip level advanced Scan and MBIST insertion, verification, and pattern generation. Your role will involve collaborating closely with customers, working hand-in-hand with RTL/PD teams and supporting Test/Product Engineering teams. What you&aposll do : Develop and implement comprehensive DFT architectures, collaborating on early planning stages. Serves as the primary point of contact for DFT-related inquiries and leads the implementation efforts, ensuring alignment with customer requirements. Implement scan and MBIST using industry-standard EDA tools. Develop and execute DFT verification plans (pattern generation, fault simulation). Collaborate with cross-functional teams to resolve DFT-related issues. Document DFT architecture and verification results. What you&aposll need: Proven leadership in complete DFT implementation and team guidance. Experience driving DFT implementation on large designs. Silicon debug experience related to DFT. BTech/MTech in EE or related field, 15+ years DFT experience. Nice to have: Familiarity with advanced DFT techniques (e.g. In-system test, SSN, multi-die testing). Tool and methodology development related to DFT. '' We have a flexible work environment to support and help employees thrive in personal and professional capacities " As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process. Show more Show less