Basic Job Deliverable Silicon Design Engineer (RTL Design and Development) Responsible for RTL design and development Responsible for generating documents, such as requirements specification, design, user-guide, etc., Experience: Experience in FPGA VHDL and/or Verilog design, Xilinx technology and tools Experience with Ethernet/PCIe/SPI/I2C/USB/GPIO/Memory architectures /DDR/SDRAM/DMA technologies Experience in HW testing, including working with test equipment – logic and traffic analysers, test generators, etc. Strong debugging skills at device and board level Scripting language experience like Perl, Python or TCL Excellent interpersonal, written and verbal communication skills Excellent communication, problem solving and analytical skills Qualification: B.Tech/M.Tech (CSE/ECE/EEE) - Track record of high academic achievement Interested candidates, please share your updated resume to althia.pereira@smartsocs.com

Role : Physical Design Experience : 2 - 20 yrs. Strong background of ASIC Physical Design : Floor planning, P&R, Extraction, IR Drop Analysis, Static Timing and Signal Integrity.. Hands-on experience on technology nodes like 7nm, 14nm, 10nm.. Good knowledge of EDA tools from Synopsys , Cadence and Mentor. Hands-on experience in floor planning, placement optimizations, CTS and routing.. Hands-on experience in cadence or Synopsys tool (Encounter, ICC, PT/PTSI, TEMPUS, DC, RC, VOLTAS). Skills : Static timing analysis, Application Specific Integrated Circuit (ASIC), Floorplan Manager, Extraction, Synopsys and Physical Design. We are looking for a highly skilled Physical Design Engineer with a strong background in ASIC physical design. The ideal candidate should have hands-on experience in advanced technology nodes (7nm, 10nm, 14nm), and deep expertise in P&R, STA, IR drop analysis, and EDA tools such as Synopsys, Cadence, and Mentor. You will be responsible for all aspects of physical design implementation from RTL to GDSII. Key Responsibilities Execute complete RTL-to-GDSII physical design flow for complex ASICs. Perform floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification. Conduct timing closure using Static Timing Analysis (STA) with tools like PrimeTime (PT/PTSI) or Tempus. Perform IR drop and EM analysis, including extraction and signal integrity verification. Optimize physical designs for power, performance, and area (PPA). Run physical verification checks such as LVS, DRC, and Antenna. Collaborate with logic designers, verification, DFT, and packaging teams to drive design convergence. Debug and resolve physical design issues during implementation and tape-out phases. Utilize scripting (TCL, Perl, Python, etc.) to automate flows and improve efficiency. Key Skills Required Solid background in ASIC physical design, including floorplanning, P&R, extraction, STA, IR/EM analysis, and signal integrity. Hands-on experience with advanced process nodes like 7nm, 10nm, and 14nm. Proficiency In EDA Tools, Such As Synopsys : ICC, DC, PrimeTime (PT/PTSI) Cadence : Innovus, Tempus Mentor : Calibre Experience with floorplan managers, placement optimization, CTS, and final routing. Familiarity with parasitic extraction and delay modeling. Proficient in scripting using TCL, Perl, Python, or Shell for tool automation and flow management. Bachelor's or Master's degree in Electronics Engineering, VLSI, or related field. Knowledge of DFT, DFM, and low-power design techniques. Experience working on full-chip or block-level implementation. Experience with multi-voltage and multi-corner designs. Exposure to 3D-IC, chiplet-based architecture, or advanced packaging flows. Knowledge of RTL synthesis and constraints development. (ref:hirist.tech)