Basic Job Deliverable Silicon Design Engineer (RTL Design and Development) Responsible for RTL design and development Responsible for generating documents, such as requirements specification, design, user-guide, etc., Experience: Experience in FPGA VHDL and/or Verilog design, Xilinx technology and tools Experience with Ethernet/PCIe/SPI/I2C/USB/GPIO/Memory architectures /DDR/SDRAM/DMA technologies Experience in HW testing, including working with test equipment – logic and traffic analysers, test generators, etc. Strong debugging skills at device and board level Scripting language experience like Perl, Python or TCL Excellent interpersonal, written and verbal communication skills Excellent communication, problem solving and analytical skills Qualification: B.Tech/M.Tech (CSE/ECE/EEE) - Track record of high academic achievement Interested candidates, please share your updated resume to althia.pereira@smartsocs.com
Role : Physical Design Experience : 2 - 20 yrs. Strong background of ASIC Physical Design : Floor planning, P&R, Extraction, IR Drop Analysis, Static Timing and Signal Integrity.. Hands-on experience on technology nodes like 7nm, 14nm, 10nm.. Good knowledge of EDA tools from Synopsys , Cadence and Mentor. Hands-on experience in floor planning, placement optimizations, CTS and routing.. Hands-on experience in cadence or Synopsys tool (Encounter, ICC, PT/PTSI, TEMPUS, DC, RC, VOLTAS). Skills : Static timing analysis, Application Specific Integrated Circuit (ASIC), Floorplan Manager, Extraction, Synopsys and Physical Design. We are looking for a highly skilled Physical Design Engineer with a strong background in ASIC physical design. The ideal candidate should have hands-on experience in advanced technology nodes (7nm, 10nm, 14nm), and deep expertise in P&R, STA, IR drop analysis, and EDA tools such as Synopsys, Cadence, and Mentor. You will be responsible for all aspects of physical design implementation from RTL to GDSII. Key Responsibilities Execute complete RTL-to-GDSII physical design flow for complex ASICs. Perform floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification. Conduct timing closure using Static Timing Analysis (STA) with tools like PrimeTime (PT/PTSI) or Tempus. Perform IR drop and EM analysis, including extraction and signal integrity verification. Optimize physical designs for power, performance, and area (PPA). Run physical verification checks such as LVS, DRC, and Antenna. Collaborate with logic designers, verification, DFT, and packaging teams to drive design convergence. Debug and resolve physical design issues during implementation and tape-out phases. Utilize scripting (TCL, Perl, Python, etc.) to automate flows and improve efficiency. Key Skills Required Solid background in ASIC physical design, including floorplanning, P&R, extraction, STA, IR/EM analysis, and signal integrity. Hands-on experience with advanced process nodes like 7nm, 10nm, and 14nm. Proficiency In EDA Tools, Such As Synopsys : ICC, DC, PrimeTime (PT/PTSI) Cadence : Innovus, Tempus Mentor : Calibre Experience with floorplan managers, placement optimization, CTS, and final routing. Familiarity with parasitic extraction and delay modeling. Proficient in scripting using TCL, Perl, Python, or Shell for tool automation and flow management. Bachelor's or Master's degree in Electronics Engineering, VLSI, or related field. Knowledge of DFT, DFM, and low-power design techniques. Experience working on full-chip or block-level implementation. Experience with multi-voltage and multi-corner designs. Exposure to 3D-IC, chiplet-based architecture, or advanced packaging flows. Knowledge of RTL synthesis and constraints development. (ref:hirist.tech)
You should have a strong background in x86 Board design with a solid foundation and experience in the analysis of Digital and Power Electronic circuits. It is important to have an understanding of signal integrity, EMI/EMC concepts for both Digital and Power Electronics. You should have experience in at least one complete project, from high-level design to final validation. Your responsibilities will include independently handling schematic design, design analysis, coordinating reviews with peer designers, Layout, SI, and EMC teams. Experience in board bring-up, issue investigation & triage, in coordination with firmware and software teams is essential. You should also be proficient in preparing and reviewing hardware design documentation and issue investigation reports. You must be capable of developing the board bring-up plan, identifying required test equipment, and executing tasks independently. Strong communication and interpersonal skills are necessary to effectively collaborate with various cross-functional teams, including post-silicon IP Validation, BIOS, and Driver Development/QA teams.,
This is a full-time on-site role for a Vendor Manager - VLSI located in Bangalore. The Vendor Manager will be responsible for Workforce Management, Staff Augmentation, contract negotiation, procurement, contract management, and maintaining communication with vendors on a day-to-day basis. Requirements Workforce Management/Staff Augmentation Expertise. Contract Negotiation and Contract Management skills. Strong Communication abilities. Experience in Vendor Management in the Semiconductor or related industry. Bachelor's degree in Engineering or a relevant field. This job was posted by Raj Sekhar from SmartSoC Solutions.
This is a full-time on-site role for a Vendor Manager - VLSI located in Bangalore. You will be responsible for Workforce Management, Staff Augmentation, contract negotiation, procurement, contract management, and maintaining communication with vendors on a day-to-day basis. Requirements include expertise in Workforce Management/Staff Augmentation, skills in Contract Negotiation and Contract Management, strong Communication abilities, experience in Vendor Management in the Semiconductor or related industry, and a Bachelor's degree in Engineering or a relevant field. This job opportunity was posted by Raj Sekhar from SmartSoC Solutions.,
As a High-Speed Analog Layout Engineer at our company, you will be responsible for designing and implementing high-speed analog and mixed-signal layouts, focusing on advanced FinFET nodes such as TSMC 2nm, 3nm, 5nm, and 7nm. With your 3+ years of experience in this field, you will play a crucial role in ensuring the success of our projects. Your main responsibilities will include: - Creating custom layouts for high-speed IPs like PLLs, SERDES, clock buffers, and data paths, utilizing your strong hands-on experience in this area. - Utilizing tools such as Cadence Virtuoso, Calibre DRC/LVS, and PEX flows to ensure accurate and efficient layout designs. - Demonstrating a proven track record of delivering clean layouts with successful DRC/LVS/EM/IR sign-offs through multiple tapeouts. - Applying expertise in layout techniques for matching, shielding, parasitic control, and achieving GHz-speed performance. - Having a solid understanding of floorplanning, symmetry, and addressing advanced process challenges. - Holding a Bachelors degree in Electrical or Electronics Engineering to support your technical knowledge. - Demonstrating strong problem-solving skills and a collaborative mindset to work effectively within our team. If you are a detail-oriented and skilled Analog Layout Engineer with a passion for high-speed design and a desire to contribute to cutting-edge projects, we encourage you to apply. Join us in our mission to drive innovation and excellence in the field of analog layout engineering.,
Company Description SmartSoC Solutions is a leader in Product Engineering Services, specializing in Semiconductor Design Services, Embedded Systems, Digital Solutions, Artificial Intelligence, Machine Learning, IoT, Networking, and Robotics. We bring cutting-edge technology expertise across industries including Semiconductor, Consumer Electronics, Telecom & Data Networking, Industrial, Automotive, and Agriculture. Our mission is to empower clients to design and build next-generation products through comprehensive services from design to production, with a focus on innovation. With a global presence in countries such as India, the USA, Sweden, Finland, South Korea, Malaysia, Canada, and Israel, our talented team of over 1,250 scientists and engineers is dedicated to driving success. Role Description This is a full-time on-site role for an AMS Characterization Engineer, located in Hyderabad. The AMS Characterization Engineer will be responsible for performing Analog/Mixed-Signal IP characterization, development of characterization plans, and post-silicon validation. Daily tasks include data analysis, generating detailed reports on IP performance, collaborating with design and verification teams, and ensuring the accuracy of characterization data. Qualifications Experience in Analog/Mixed-Signal IP characterization, and post-silicon validation Proficiency in data analysis and report generation Strong collaboration skills with design and verification teams Knowledge of characterization plans and methodologies Bachelor’s degree or higher in Electrical Engineering, Electronics, or a related field Experience in the semiconductor industry is a plus Excellent communication and organizational skills Ability to work effectively on-site in Hyderabad
Company Description SmartSoC Solutions is a leading Product Engineering Services company specializing in Semiconductor Design Services, Embedded Systems, Digital Solutions, Artificial Intelligence, Machine Learning, IoT, Networking, and Robotics. We cater to diverse industries, including Semiconductor, Consumer Electronics, Telecom & Data Networking, Industrial, Automotive, and Agriculture. Our mission is to empower clients to design and build next-generation products, offering comprehensive services from design to production. With a global presence and a talented team of over 1,250 scientists and engineers, we are dedicated to driving success around the world. Role Description This is a full-time, on-site role located in Hyderabad for a DFT (Design for Testability) Lead at SmartSoC Solutions. The DFT Lead will be responsible for developing and implementing DFT architecture, creating and validating test plans, and working closely with design and verification teams to ensure testability. Day-to-day tasks include implementing scan insertion, MBIST, boundary scan, and ATPG, as well as analyzing test coverage and working with clients to address technical issues and provide solutions. Qualifications Strong Analytical Skills and problem-solving abilities Excellent Communication skills for interacting with teams and clients Experience in Consulting and providing technical solutions Strong Customer Service and Sales skills Proficiency in DFT methodologies and tools Familiarity with semiconductor design and testing processes Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field Experience in the semiconductor industry is a plus
Company Description SmartSoC Solutions is a leading Product Engineering Services company specializing in Semiconductor Design Services, Embedded Systems, Digital Solutions, Artificial Intelligence, Machine Learning, IoT, Networking, and Robotics. We serve industries such as Semiconductor, Consumer Electronics, Telecom & Data Networking, Industrial, Automotive, and Agriculture. Our mission is to empower clients to design and build next-generation products with comprehensive services from design to production, while maintaining a focus on innovation. With a global presence in eight countries, our team of over 1,250 scientists and engineers is dedicated to driving success. Role Description This is a full-time on-site role for a Lead DFT Engineer located in Bengaluru South. The Lead DFT Engineer will be responsible for designing and implementing Design for Testability (DFT) techniques in semiconductor devices. The day-to-day tasks include handling scan insertion, ATPG, JTAG, BIST, and MBIST. The role also involves DFT architecture planning and working closely with verification and physical design engineers to ensure that DFT requirements are met. Qualifications Expertise in Design for Testability (DFT) techniques such as scan insertion, ATPG, JTAG, BIST, and MBIST Experience in DFT architecture planning and implementation Ability to work collaboratively with verification and physical design engineers Strong analytical and problem-solving skills Excellent written and verbal communication skills Relevant experience in semiconductor design and related technologies Bachelor's degree in Electrical Engineering, Computer Engineering, or related field Master's degree or higher and experience in a leadership role is a plus
Strong background of ASIC Physical Design: Floor planning, P&R, Extraction, IR Drop Analysis, Static Timing and Signal Integrity. Hands-on experience on technology nodes like 7nm, 14nm, 10nm. Good knowledge of EDA tools from Synopsys , Cadence and Mentor Hands-on experience in floor planning, placement optimizations, CTS and routing. Hands-on experience in cadence or Synopsys tool (Encounter, ICC, PT/PTSI, TEMPUS, DC, RC, VOLTAS) Skills:- Responsive Design, Project coordination, Extraction, Competitor Analysis, EDA, floorplanning, 7nm, 14nm and 10nm
As a High-Speed Analog Layout Engineer at our company, you will be responsible for designing high-speed analog and mixed-signal layouts, focusing on advanced FinFET nodes such as TSMC 2nm, 3nm, 5nm, and 7nm. Your role will require you to have a strong background in custom layout for high-speed IPs like PLLs, SERDES, clock buffers, and data paths. Key Responsibilities: - Hands-on experience in custom layout for high-speed IPs including PLLs, SERDES, clock buffers, and data paths - Proficiency in tools like Cadence Virtuoso, Calibre DRC/LVS, and PEX flows - Demonstrated track record of delivering clean layouts with successful DRC/LVS/EM/IR sign-offs through multiple tapeouts - Expertise in layout techniques for matching, shielding, parasitic control, and achieving GHz-speed performance - Sound understanding of floorplanning, symmetry, and addressing advanced process challenges Qualifications Required: - Bachelor's degree in Electrical or Electronics Engineering - Strong problem-solving skills and a collaborative mindset Join us if you have the required experience and skills to excel in high-speed analog layout design and contribute effectively to our team.,