155 Mbist Jobs - Page 6

General Summary: Qualcomm is a leading technology innovator driving next-generation experiences and digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systemsincluding digital, analog, RF, optical circuits, mechanical systems, equipment, packaging, test systems, FPGA, and DSPthat launch cutting-edge, world-class products. You will collaborate closely with cross-functional teams to develop solutions and meet rigorous performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 3+ years of hardware engineering experience OR Master's degree in the relevant field with 2+ years of hardware engineering experience OR PhD in the relevant field with 1+ year of hardware engineering experience Minimum 5+ years experience in Design for Test (DFT), including ATPG, Scan Insertion, MBIST, and JTAG Core Skills & Experience: Deep knowledge of DFT concepts and hands-on experience with scan and MBIST insertion Expertise in ATPG pattern generation and verification, MBIST verification, and post-silicon bring-up and yield analysis Strong skills in defining test mode timing constraints and resolving timing violations with corrective actions Ability to design and analyze tests for new technologies, including custom RAM and RMA Proficient in scripting languages such as Perl and Shell for automation and tooling Experience simulating test vectors to verify test coverage and correctness Familiarity with equivalence checking and RTL lint tools like SpyGlass Ability to thrive in dynamic, international teams and adapt quickly to new tools and methodologies Strong multitasking abilities to manage multiple high-priority design projects simultaneously Excellent problem-solving skills with a proactive, analytical mindset

Interfacewith design team to ensure DFT design rules andcoveragesare met. Generating high quality manufacturingATPGtest patterns for stuck-at(SAF), transition fault(TDF)modelsthrough the use ofon-chip test compression techniques. MBISTverification(including repair),testpattern generation through Mentor tool. ATPG(SAF, TDF)and MBISTverification usingunit delay and min/maxtiming cornersimulations. Workwith the Product/Testengineering teams on the delivery of manufacturing test patterns for ATE. Responsible for supporting postsilicondebug effort, issue resolution. Responsible for Diagnostic Tool generation for ATPG,MBISTand bring-up on ATE. Developing,enhancingandmaintainingscripts as necessary Minimum Qualifications: Bachelors degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Masters degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.Minimum of1-6yearsexperiencein ASIC/DFT- simulation andSilicon validation Detailed knowledge on DFT concepts, pattern simulation, Silicon debugand yield enhancement In depthknowledge andhands-onexperience in ATPG-coverage analysis. In depth knowledge of Memory verification,repairand failure root-cause analysis. Experience withany of thesetoolsisrequired ATPG -TestKompress MBIST- MentorETVerify Simulation -VCS(preferred),modelsim. Expertisein scripting languages such asPerl, shell, etc is an addedadvantage Ability to work in an international team, dynamic environmentwithgood communicationskills Ability to learn and adapt to newtools,methodologies. Ability to do multi-tasking & work on several high priority designs in parallel

Duration: Fulltime Work Type: Onsite Job Description: Experience in multi-die HBM/Memory testing with Synopsys tools preferred Experience in DFT timing closure preferred Must have experience with Synopsys DFT tools & Flows 4+ yrs "Must have worked on Scan Insertion, MBiST, ATPG, Simulations .

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement. Roles and Responsibilities o Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. o Work closely with design/verification teams within CPU to develop comprehensive test plan. o Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. o Verify power intent through use of methodologies like UPF. o Work closely with system architects, software teams and Soc team to validate system use cases. o Work closely with emulation team to enable verification on emulators and FPGA platforms. o Debug and triage failures in simulation, emulation and/or Silicon. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. o BE/BTech degree in CS/EE with 3+ years"™ experience. o Experience in power management verification. o Implementation of assembly and C language embedded firmware. o Experience in C/C++, scripting languages, Verilog/system Verilog. o Strong understanding of power management features in CPUs and CPU based Socs. o Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc. Preferred Requirements: o Good Understanding of CPU architectures and CPU micro-architectures. o In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture o Experience with advanced verification techniques such as formal and assertions is a plus o Knowledge and verification experience in DFT and structural debug concepts and methodologiesJTAG, IEEE1500, MBIST, scan dump, memory dump is a plus

Position Overview The Tessent division seeks a highly motivated, creative, and energetic individual as Product Engineer, specializing in design-for-test (DFT) and test delivery at chip and system level. Tessent is the market and technology leader of automated tools for insertion of semiconductor design-for-test (DFT) structures, automatic test pattern generation (ATPG), embedded deterministic compression (EDT), memory built-in self-test (MBIST), logic built-in self-test (LBIST), diagnosis-driven yield analysis (DDYA), hierarchical DFT solutions such as Streaming Scan Network (SSN), and analog fault injection and test. This position presents a great opportunity to stay involved technically while getting exposure to marketing and interacting with sales. Responsibilities include but are not limited to: Define and characterize new product capabilities needed to meet customer requirements Work collaboratively with Tessent R&D to prototype, evaluate, and test new products and features within complex IC design flows Lead beta programs and support beta partners Drive product adoption and growth Create and deliver in-depth technical presentations, develop training material, white papers, contributed articles, and application notes Develop and review tool documentation such as user and reference manuals Work with customers as well as Siemens EDA stakeholders such as regional application engineers, global support engineers, and marketing Work through complex technical issues and independently create solutions and new methodologies Present complex principles in simple terms to broad audiences Collaborate and share information across team boundaries in written and spoken forms Some travel, domestic and international Job Qualifications The successful candidate will possess the following combination of education and work experience: BS degree (or equivalent) in Electrical Engineering, Computer Science, Computer Engineering, or related field is required Must have 5-8 years of experience, including 2+ years of experience in DFT for complex ASICs / SOCs, including some of the following areas: Automatic test pattern generation (ATPG), internal scan, embedded scan compression (EDT), packetized test delivery (SSN), memory built-in self-test (MBIST), logic built-in self-test (LBIST), IEEE 1687 IJTAG, analog design and simulation, hierarchical DFT implementation Must have industry experience with DFT tools, preferably Tessent tool suite Industry experience with inserting scan, running ATPG and debugging fault coverage Exposure to one or more adjacent IC disciplines such as the following a plus: o RTL coding and verification using Verilog/ SystemVerilog/VHDL o Synthesis and timing analysis o Place and route o Advanced IC packaging o DFT and test for embedded IP cores o Failure diagnosis o ATE use / test program development Candidate should be high energy, curious individual, self-motivated to learn new DFT methodologies and technologies Able to work as individual contributor and lead technical activities of junior engineers Strong problem-solving, reasoning and deduction skills and the ability to analyze and debug complex design and simulation issues Proficiency in LINUX and Windows environments Proficiency in a scripting language like TCL (preferred) or Python Excellent written and spoken English language communication skills Excellent organizational skills Location can be remote or hybrid in North America, or in-office at one the following Tessent locations: o Ottawa (Canada), Saskatoon (Canada), Wilsonville (Oregon), Fremont (California).

About the Role Senior DFT Engineer (4 - 8 Years) | Hyderabad / Bangalore, India Are you passionate about making complex SoCs more testable, robust, and production-ready? As a Senior DFT Engineer , youll play a hands-on role in implementing critical DFT features that ensure silicon success across next-generation ASICs. You will work alongside experienced leads on advanced nodes (14nm and below), contribute to DFT flow development, and implement key test strategies such as scan compression, MBIST, and JTAG. This is your chance to grow into a technical specialist while playing a central role in the silicon lifecyclefrom RTL to tape-out. Key Responsibilities Support DFT architecture implementation and feature insertion for complex SoCs. Implement Scan Insertion , ATPG , Compression , MBIST , and Boundary Scan (JTAG) . Work with Mentor Graphics, Synopsys , or Cadence DFT tools for flow execution and verification. Generate and validate test vectors , support simulation, and ensure fault coverage goals. Assist with DFT verification , timing closure support , and pre-silicon checks . Collaborate with RTL, PD, and STA teams during integration and tape-out phases. Automate DFT flows using Tcl , Perl , or other scripting tools to improve efficiency. Contribute to post-silicon bring-up and production test debugging , where applicable. Work under the guidance of technical leads while also mentoring junior team members when needed. Required Skills & Qualifications Bachelor’s or Master’s degree in Electronics , Electrical Engineering , or a related discipline. 4–8 years of hands-on DFT experience in SoC/ASIC environments. Practical knowledge of: Scan/Compression Insertion and ATPG MBIST architectures and memory BIST flows Boundary Scan (JTAG / IEEE 1149.x) Exposure to silicon bring-up or production test is a strong advantage. Scripting experience using Tcl, Perl , or similar languages. Strong debugging, documentation, and collaboration skills. Interested? Apply or or know someone great? Reach out via DM or WhatsApp +91 9966034636 / Send your profile to ranjith.allam@cyient.com

About The Role Solid Experience in DFT Architecture. The candidate should have experience with ATPG, JTAG, BSCAN, BIST and MBIST flows. Experience on Hierarchical DFT techniques using Pattern Retargeting in Tessent flow Strong knowledge of the Tessent Shell environment and Tessent tools The desired candidate must have specific emphasis on the following tools Test Kompress / Fastscan ATPG, MBIST, Boundary scan. Hands on experience in simulating scan patterns and debugging pattern mismatches during verification process Experience in helping to debug failing scan patterns on the ATE is highly desirable. Hands on knowledge in state-of-the-art EDA tools for DFT, design and verification.(Mentor, Cadence, Synopsys) Must be able to simulate and debug MBIST testbenches. Ability to come up with a detailed test plan based on the Arch specs Should be knowledgeable in all SOC functions such as Digital design, STA, Synthesis, PnR, DV and ATE test. The candidate should have prior experience in managing and developing teams Required Qualification B.E / B.Tech / M.E / M.Tech in Electrical / Electronic Engineering. experience-10-16 years Preferred experience of handling 10+ team members. Good understanding and exposure to SoC design and architecture Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects Comfortable with VCS / Verdi and excellent debugging skills Logical in thinking and ability to gel well within a team and be a proactive member of the team. Good communication and leadership skills Excellent team player High Integrity Job Type Full Time Job Location Hubballi

Principal DFT Engineer Bangalore (Hybrid ) / Hyderabad (Hybrid ) Principal DFT Engineer Full Time \ Experienced Summary Join an ambitious, experienced team of silicon and distributed systems experts as a Design For Test engineer. You have the opportunity to build a groundbreaking new category of product that revolutionizes the performance and scalability of next-generation distributed computing systems, and to help solve key infrastructure challenges facing our customers. We are looking for talented, motivated candidates with experience building and deploying DFT flows for large-scale networking and computing chips, and who are looking to grow in a fast paced, dynamic startup environment. Roles & Responsibilities As a member of our team, you will work with multi-functional teams, implementing state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression. You will work with 3rd party IP vendors to integrate Memory BIST, scan, PHY I/O BIST, and other DFT logic into a streaming scan fabric with a sequential scan compressor/decompressor You will work with DFT Solutions Vendors to port those patterns at the top-level, to implement Memory BIST interface in high performance processor IP, and to implement high-speed I/O for the logic scan test You will work with Physical Designers to validate the DFT timing constraints You will work with RTL Designers to verify test design rules You will work with Test Engineers to bring up the patterns on the ATE Automated Test Equipment You will help develop and deploy DFT methodologies for our next generation products. Key Qualifications MSEE or equivalent experience 8-13+ years of experience in DFT or related domains You will have a solid knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation Possess excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools Have good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development Strong programming and scripting skills in Perl, Python or Tcl desired Exceptional written and oral and interpersonal skills with the curiosity to work on rare challenges Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Role Description This is a full-time on-site role for DFT Engineer at Incise Infotech Pvt. Ltd. DFT Engineer will be responsible for developing, implementing, and verifying the Design for testability (DFT) on complex system on chips (SOCs). The role also involves working with the physical design team to ensure the DFT requirements are met and with the verification team to ensure the DFT design is meeting the test coverage metrics. The ideal candidate will have experience in SOC level DFT techniques, ATPG, MBIST, JTAG, and boundary scan. Qualifications Bachelor's or Master's degree in Electrical/Electronics Engineering or equivalent 3+ years of experience in DFT domain Expertise in DFT methodologies - scan insertion, scan compression, boundary scan, and memory BIST Experience in DFT tools like Tessent, ATPG, MBIST, and JTAG Experience in the complete scan chain flow (ATPG, simulation, and test pattern generation) on complex SOCs Knowledge of STA, LEC, and physical design aspects related to DFT Experience in Shell/Perl/Tcl and other scripting languages Good communication skills and the ability to work well in a team environment Interested can share resume on Shubhanshi@incise.in

Job Description: We are looking for a skilled DFT Engineer with 13 years of experience in ASIC/SoC test design. The ideal candidate will work on scan insertion, ATPG, MBIST/LBIST, and DFT verification using industry-standard tools. Key Skills: DFT implementation: Scan, MBIST, LBIST, Boundary Scan Tools: Tessent, DFT Compiler, Tetramax, Modus Scripting: Python, Perl, Tcl Good understanding of STA and RTL flows Strong debugging & communication skills.

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Automatic Test Pattern Generation (ATPG) Good to have skills : NA Minimum 7.5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your day will involve overseeing the application development process, coordinating with team members, and ensuring project milestones are met. Roles & Responsibilities: Expected to be an SME Collaborate and manage the team to perform Responsible for team decisions Engage with multiple teams and contribute on key decisions Provide solutions to problems for their immediate team and across multiple teams Lead the application design and development process Coordinate with stakeholders to gather requirements Ensure project milestones are met Professional & Technical Skills: Must To Have Skills:Proficiency in Automatic Test Pattern Generation (ATPG) Strong understanding of software development lifecycle Experience in application architecture design Knowledge of database management systems Hands-on experience in application testing Additional Information: The candidate should have a minimum of 7.5 years of experience in Automatic Test Pattern Generation (ATPG) This position is based at our Bengaluru office A 15 years full-time education is required Qualifications 15 years full time education

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement. Roles and Responsibilities o Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. o Work closely with design/verification teams within CPU to develop comprehensive test plan. o Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. o Verify power intent through use of methodologies like UPF. o Work closely with system architects, software teams and Soc team to validate system use cases. o Work closely with emulation team to enable verification on emulators and FPGA platforms. o Debug and triage failures in simulation, emulation and/or Silicon. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. o BE/BTech degree in CS/EE with 3+ years"™ experience. o Experience in power management verification. o Implementation of assembly and C language embedded firmware. o Experience in C/C++, scripting languages, Verilog/system Verilog. o Strong understanding of power management features in CPUs and CPU based Socs. o Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc. Preferred Requirements: o Good Understanding of CPU architectures and CPU micro-architectures. o In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture o Experience with advanced verification techniques such as formal and assertions is a plus o Knowledge and verification experience in DFT and structural debug concepts and methodologiesJTAG, IEEE1500, MBIST, scan dump, memory dump is a plus

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum of 5+ years"™ experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG -In depth knowledge of DFT concepts. -In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. -Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors. -Knowledge of equivalence check and RTL lint tool (like spyglass). -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem-solving skills

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 3+ years"™ experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG -In depth knowledge of DFT concepts. -In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. -Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors. -Knowledge of equivalence check and RTL lint tool (like spyglass). -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem-solving skills

• Should have worked hands-on extensively on full chip DFT design, • implementation, vector generation/verification, JTAG, Boundary scan & Simulation. • Experience with Scan, Compression, ATPG & Simulations with Mentor/Synopsys/ Cadence tools. Required Candidate profile • Participated in Successful Tapeouts of SoC/ASIC chips at 14nm or below. • Develop/Automate flows & scripts in Perl/Tcl to enhance the DFT methodologies & process. • Logic BIST knowledge is a plus.

Dear Candidates, Greetings!! We are hiring for one of the Globalized Semiconductor Manufacturing MNC that specializes into Design Verification , Embedded software, Analog Layout, Analog Design, RTL Design, Design for test Job Type: FTE Job Role:- DFT Engineer Experience: 8+ Years Location: Bangalore Work Mode: Hybrid Notice Period: Serving to 45 days Budget: As Per Market Standards Mandatory Skills: Good understanding on DFT concepts like SCAN/ATPG/BSCAN/MBIST. Experience in Mbist insertion using tessent and mbist validation Experience in ATPG, drc fix and coverage analysis. Experience in scan synthesis. Hands on experience on Simulations with and without timing. Post silicon debug support. Interested candidates can share their updated resume on Gurpreet@selectiveglobalsearch.com

Position: DFT Lead Engineer ( Cluster porject with 7-8 Junior team) Location: Bangalore, India Experience: 8+ years in ASIC/SoC DFT About the Role We are seeking an experienced Design-for-Test (DFT) Lead Engineer to drive test architecture, strategy, and execution for advanced AI-centric SoCs. This role demands deep technical expertise, leadership skills, and the ability to collaborate closely with cross-functional design teams to ensure high-quality, production-ready silicon. Key Responsibilities Define and own the DFT architecture for complex AI/ML SoCs, including scan, MBIST, LBIST, JTAG, and boundary scan strategies. Drive ATPG, fault modeling, pattern generation, and compression flow for optimal coverage. Collaborate with RTL, physical design, and verification teams to ensure seamless DFT integration. Lead silicon bring-up and production test correlation efforts. Work with test engineering teams to optimize test time and yield. Provide technical guidance, mentoring, and review of junior engineers work. Interface with EDA vendors to evaluate tools, flows, and methodologies for DFT improvements. Required Skills & Experience 8+ years of hands-on DFT design and implementation for large SoCs. Strong experience in scan insertion, ATPG, MBIST/LBIST, boundary scan, and IJTAG . Proficiency in EDA tools such as Synopsys DFTMAX/TetraMAX , Cadence Modus, or equivalent. Solid understanding of ASIC design flow , timing closure, and physical design constraints. Experience in silicon bring-up and production test environments. Excellent leadership, problem-solving, and communication skills. Preferred Qualifications Experience with AI, high-performance computing, or data-center class chips . Knowledge of advanced process nodes (5nm/7nm). Exposure to yield analysis and debug methodologies. Why Join Us? Work on cutting-edge AI processors that are redefining performance, efficiency, and scalability in the next generation of computing. Join a team where innovation meets execution, and your contributions directly shape silicon success.

Required Technical and Professional Expertise in DFT Minimum 6 to 8 years of relevant experience . Proficient in DFT architectures & methodologies that includes Scan insertions, ATPG, MBIST, JTAG, etc. Sound knowledge of DFT tools/methodology from cadence /Synopsys/Mentor tools Good Experience in Python/Perl/TCL scripting

General Summary: Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement. Roles and Responsibilities o Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. o Work closely with design/verification teams within CPU to develop comprehensive test plan. o Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. o Verify power intent through use of methodologies like UPF. o Work closely with system architects, software teams and Soc team to validate system use cases. o Work closely with emulation team to enable verification on emulators and FPGA platforms. o Debug and triage failures in simulation, emulation and/or Silicon. Additional Job Descriptiono BE/BTech degree in CS/EE with 3+ years experience.o Experience in power management verification.o Implementation of assembly and C language embedded firmware.o Experience in C/C++, scripting languages, Verilog/system Verilog.o Strong understanding of power management features in CPUs and CPU based Socs.o Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc.Preferred Requirements:o Good Understanding of CPU architectures and CPU micro-architectures.o In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitectureo Experience with advanced verification techniques such as formal and assertions is a pluso Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

We are seeking an experienced and highly skilled Senior SOC Design for Test Engineer with aminimum of 5 years of hands-on experience in SOC Design for Test. As a key member of our team, you will play a pivotal role in ensuring the testability, manufacturability, and quality of our cutting-edge System on Chip designs Key Responsibilities Lead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution coverage, manufacturability, and quality plans. Develop full chip and block level DFT implementation from the DFx Specifications and product coverage, quality, and manufacturability goals. Define and implement Test controllers at top level and block level, fuse controllers, test clocking strategy, chip I/O test strategy and HSIO test strategy. Define JTAG TAP, boundary scan, I/O Test JTAG access, IEEE1687 iJTAG network and instrument design and implementation. Define the Test Interface for each of the P&R IP blocks for Scan, MBIST and other test interfaces. Define hierarchical block isolation, Test clocking and On Chip Clock controllers and reset methodology. Define scan and MBIST timing at the top level and block level timing. Analyse block level RTL or gates to ensure that scalability and coverage is satisfied as per the design goals. Ensure that DFT is provided to fix the DFT violations to ensure that the design goals are meet. Analyse compression requirements for each of the blocks, define Intest and Extest compression requirements and define the requirements for compression engines. Synthesize compression engines for each of the blocks. Create the collaterals for compression for the IPs. Block level scan insertion as well as development of the scan wrappers for the blocks. Do scan insertion on the blocks, analyse scan DRC, implement DFT fixes. Create scan protocol files for designs, create scan inserted netlist, create scan definitions as well as scan definition files for PD. Perform ATPG on the scan inserted netlist, analyse DRC and coverage violations. Deep knowledge of different scan models Stuck-at, transition test, path-delay, bridging, cell aware, small-delay transition, IDDQ test etc. Ability to analyse coverage for each of the model types. Running GLS with or without timing for the scan vectors. Ability to debug the failures and working with timing and PD teams to fix the timing issues. Understanding of pattern delivery to the post-silicon test engineering teams. Delivering to the Test engineering the Test pin muxing and other full chip requirements for the Test Engineering Team. Understanding tester requirements and delivering the patterns in the formats that the tester teams needs. Implement pattern retargeting. Create grey box models for blocks. Coverage analysis of full chip consolidating Intest and Extest patterns. Knowledge of Top level scan architecture and creating flow to create pattern retargeting. Knowledge of Streaming Scan Network and other Top level scan pin sharing and implementing the block to top level pattern generation for this flow. Implementing Memory Testing and MBIST. Knowledge of Memory defect models and test algorithms. Knowledge of memory bit mapping and redundancy analysis. Implementing memory repair and fuse sharing among various memory. Knowledge of LogicBIST with Test point insertion, X-blocking. Full chip DFT delivery for tapeout including but not limited to DFT netlist verification, pattern delivery, Tester requirements. Debug DFT patterns post silicon, ability to analyse chain test patterns for failures, scan pattern failures. Analyse MBIST pattern failures, yield and repair debug. Ability to perform volume diagnostics on the parts to isolate and improve the patterns. Requirements Bachelors degree in computer science, Electrical/Electronics Engineering, or related field. OR masters degree in computer science, Electrical/Electronics Engineering, or related field. OR PhD in Computer Science, Electrical/Electronics Engineering, or related field. 5+ years of hands-on experience in SOC Design for Test. Expertise in DFT tools and flows in scan intertion, ATPG, GLS simulation, diagnosis flows. Prior experience working on IP level and SOC level DFT projects. Proficient in DFT tools from Siemens (Tessent), Synopsys DFTmax, Tetramax, Spyglass DFT advisor, Genius DFT, Modus, VCS, Xcelium etc. Worked in full chip design or complex IP delivery in the area of DFT. Experience in post silicon debug, diagnosis and yield enhancements is a plus.

General Summary: Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement. Roles and Responsibilities o Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. o Work closely with design/verification teams within CPU to develop comprehensive test plan. o Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. o Verify power intent through use of methodologies like UPF. o Work closely with system architects, software teams and Soc team to validate system use cases. o Work closely with emulation team to enable verification on emulators and FPGA platforms. o Debug and triage failures in simulation, emulation and/or Silicon. o BE/BTech degree in CS/EE with 3+ years experience. o Experience in power management verification. o Implementation of assembly and C language embedded firmware. o Experience in C/C++, scripting languages, Verilog/system Verilog. o Strong understanding of power management features in CPUs and CPU based Socs. o Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc. Preferred Requirements: o Good Understanding of CPU architectures and CPU micro-architectures. o In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture o Experience with advanced verification techniques such as formal and assertions is a plus o Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.

Block & Soc level DFT insertion. Scan insertion & DRC cleanup. ATPG, Pattern generation for Stuck-At, at-speed test, iddq, path delay, fault grading. Coverage debug. Memory testing, MBIST Pattern generation.

• Should have worked hands-on extensively on full chip DFT design, • implementation, vector generation/verification, JTAG, Boundary scan & Simulation. • Experience with Scan, Compression, ATPG & Simulations with Mentor/Synopsys/ Cadence tools. Required Candidate profile • Participated in Successful Tapeouts of SoC/ASIC chips at 14nm or below. • Develop/Automate flows & scripts in Perl/Tcl to enhance the DFT methodologies & process. • Logic BIST knowledge is a plus.

1. Minimum of three years of hands-on Test Development experience (DFT, EDA tools, etc..) 2. Solid knowledge & experience in defining test solutions for multi-million gate SOC (Scan & MBIST) with Mixed Signal IPs (PLL, High Speed SERDES, DDR) 3. Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test 4. Strong understanding of relationships between Hardware, Firmware and Software in FPGA and/or multi-processors SOC. Past experience in leading the team to successful silicon bring-up and problem solving in a complex system 5. Strong planning, project, and people management skills required. Must have experience developing managers and individual contributors 6. Experienced hands-on technical manager not afraid to dig into details to provide technical direction Proven track record of delivering results and meeting quality, cost, and time-to-market objectives 7. Ability to collaborate with overseas colleagues to define strategy, plan, and execute across the larger, global organization 8. Stakeholder influencing and people skills must be excellent. 9. Needs to be able to set aggressive goals and manage risks effectively 10. Must have a thorough understanding of tool development methodology. 11. Ability to manage software development tasks associated with specifying, developing, scheduling, and debugging according to current and future tool requirements. 12. MS or Ph.D. Engineering degree (EE or equivalent) with 3-7 years semiconductor industry experience.

Minimum of ten years of hands-on Test Development experience (DFT, EDA tools, etc..) Solid knowledge & experience in defining test solutions for multi-million gate SOC (Scan & MBIST) with Mixed Signal IPs (PLL, High Speed SERDES, DDR) Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test Strong understanding of relationships between Hardware, Firmware and Software in FPGA and/or multi-processors SOC. Past experience in leading the team to successful silicon bring-up and problem solving in a complex system Strong planning, project, and people management skills required. Must have experience developing managers and individual contributors Experienced hands-on technical manager not afraid to dig into details to provide technical direction Proven track record of delivering results and meeting quality, cost, and time-to-market objectives Ability to collaborate with overseas colleagues to define strategy, plan, and execute across the larger, global organization Stakeholder influencing and people skills must be excellent. Needs to be able to set aggressive goals and manage risks effectively Must have a thorough understanding of tool development methodology. Ability to manage software development tasks associated with specifying, developing, scheduling, and debugging according to current and future tool requirements. MS or Ph.D. Engineering degree (EE or equivalent) with 3-10 years semiconductor industry experience.