155 Mbist Jobs - Page 2

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills. Mandatory Key Skills VHDL,RTL coding,Mentor DfT tools,Cadence tools,scan insertion,JTAG,ATPG,DRC,coverage analysis,simulation debug,timing,SDF,LBIST,Mixed Signal Radar IC,proactive,collaborative,detail-oriented,independent judgment,debug,root cause analysis,Verilog*

Skill : DFT Lead/Manager with 5-15 Years Location : Bangalore/HYD Minimum 5 Years of Relevant DFT Experience Good Experience in Scan Insertion, Scan DRC Checks. Experience in Atpg,Mbist,Simulation,ijtag skills is MUST. Should have working knowledge in LBIST is Preferred. Good communication skills and Leadership skills. Able to manage client interactions and stake holder Management for regular status meetings. Please forward your updated profile to chakradhar.marupuru@quest-global.com below details Current CTC : Expected CTC: Notice Period :

DESCRIPTION The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and re-imagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge. Work hard. Have fun. Make history. We are seeking a seasoned and strategic Sr DFT Engineer to Lead end-to-end Design-for-Test (DFT) planning, execution, and silicon readiness for complex SoCs. This role demands deep technical expertise, hands-on ownership, and proven leadership in taking chips from design to volume production. As a Senior DFT Engineer, you will be both the technical owner and hands-on driver of the DFT strategy and execution across complex, high-performance SoCs. This role requires deep technical expertise, the ability to architect scalable and robust DFT solutions, and the discipline to personally engage in implementation and debug. You will work alongside world-class design, validation, and test teams to ensure first-pass silicon success and scalable production test readiness. Ideal for a seasoned leader, this role combines strategic ownership with direct execution, driving full lifecycle accountability - from early DFT architecture planning to high-volume silicon bring-up and yield ramp. Key job responsibilities Key job responsibilities ? Lead development & implementation of DFT architecture including system level DFT for a full chip ? Write and guide others in writing design flow and project documentation. ? Own DFT planning, milestone tracking, and cross-functional checklist reviews. ? Oversee design, insertion, and verification of DFT logic and components into full SoC and subsystem RTL netlists. ? Review and sign-off SoC level DFT mode timing closure using static timing analysis ? Drive the sign-off on a generation of high-quality test and debug patterns for high coverage on silicon ? Keep informed on and introduce new technology into Design-for-Test process as appropriate. BASIC QUALIFICATIONS Education: BS/BE or MS/ME in Electrical Engineering, Computer Engineering, or related field. Experience: ? 15+ years in SoC/ASIC DFT, including 3+ years Leading DFT. ? Proven DFT experience leading multiple SoCs/ASICs (end-to-end) from architecture to high-volume production. DFT Architecture Expertise: Proven capability in architecting and implementing DFT strategies at both subsystem and top-level, including: ? Scan architecture, compression, and ATPG implementation for high fault coverage and test quality. ? MBIST, BISR, and BIHR flows, including advanced shared-bus memory BIST integration. ? IEEE 1149.x (Boundary Scan), IEEE 1500, and IEEE 1687 (IJTAG) test architectures. ? DFT-Aware STA closure, including constraint generation and timing convergence strategies for shift and capture paths. ? RTL and gate-level debug, including mismatch triage and simulation correlation. ? Insertion and Validation of EFUSE & OTP controllers and related structures during DFT implementation. Tool Proficiency: Deep hands-on experience with Tessent / Industry Std EDA tools, including: ? IJTAG ICL extraction and PDL modeling. ? DFT logic insertion, pattern generation, and diagnostics. Design Background: ? Experience in writing verilog/system verilog RTL related to DFT logic design. ATE Test Readiness: Lead DFT-to-ATE handoff, including: ? Drive generation and sign-off of high-quality test and debug patterns to meet DFT coverage targets. ? Pattern validation, format conversion, and debugging across wafer sort and final test. ? Collaboration with PE/Test teams for silicon correlation and production test optimization, yield improvements. Silicon Debug: ? Drive post-silicon validation, failure triage, and yield learning using SCAN diagnosis and MBIST repair signature analysis. Automation Skills: ? Ability to build and maintain scalable DFT automation flows using Python, Tcl, or Perl. Collaboration: ? Proven success driving cross-functional teams involving RTL, physical design, validation, PE, and manufacturing. Execution Excellence: ? Known for being proactive, detail-oriented, and independently accountable for tapeout and post-silicon success. PREFERRED QUALIFICATIONS Leadership: ? Led multi-site/global DFT teams, mentoring engineers and managing design reviews. ? Drove design-for-test planning in collaboration with customers or design services partners. Technical Depth: ? Strong understanding of DFT-Aware yield improvement and FA, including DPPM reduction strategies. ? Ability to correlate pre-silicon vs ATE pattern behavior and debug marginality/escape issues. ? Exposure to Design-for-Debug (DfD) features like trace buffers, signature capture, and observability enhancement. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit for more information. If the country/region you're applying in isn't listed, please contact your Recruiting Partner.

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills. Mandatory Key Skills JTAG,ATPG DRC,LBIST,RTL coding,VHDL,DFT

Interfacewith design team to ensure DFT design rules andcoveragesare met. Generating high quality manufacturingATPGtest patterns for stuck-at(SAF), transition fault(TDF)modelsthrough the use ofon-chip test compression techniques. MBISTverification(including repair),testpattern generation through Mentor tool. ATPG(SAF, TDF)and MBISTverification usingunit delay and min/maxtiming cornersimulations. Workwith the Product/Testengineering teams on the delivery of manufacturing test patterns for ATE. Responsible for supporting postsilicondebug effort, issue resolution. Responsible for Diagnostic Tool generation for ATPG,MBISTand bring-up on ATE. Developing,enhancingandmaintainingscripts as necessary Minimum Qualifications: Bachelors degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Masters degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.Minimum of1-6yearsexperiencein ASIC/DFT- simulation andSilicon validation Detailed knowledge on DFT concepts, pattern simulation, Silicon debugand yield enhancement In depthknowledge andhands-onexperience in ATPG-coverage analysis. In depth knowledge of Memory verification,repairand failure root-cause analysis. Experience withany of thesetoolsisrequired ATPG -TestKompress MBIST- MentorETVerify Simulation -VCS(preferred),modelsim. Expertisein scripting languages such asPerl, shell, etc is an addedadvantage Ability to work in an international team, dynamic environmentwithgood communicationskills Ability to learn and adapt to newtools,methodologies. Ability to do multi-tasking & work on several high priority designs in parallel

We are looking for a skilled DFT Engineer with 3 to 7 years of experience to join our team in the IT Services & Consulting industry. The ideal candidate will have a strong background in designing and implementing fault detection and testing strategies. Roles and Responsibility Design and develop test plans, test cases, and test scripts for complex systems. Collaborate with cross-functional teams to identify and prioritize testing requirements. Develop and maintain automated testing frameworks and tools. Analyze test results, identify defects, and work with development teams to resolve issues. Participate in agile development methodologies and contribute to process improvements. Stay up-to-date with industry trends and emerging technologies in DFT engineering. Job Requirements Strong understanding of digital logic design principles and microelectronic circuits. Experience with programming languages such as C++, Python, or Java. Familiarity with testing frameworks like JUnit, PyUnit, or Selenium. Knowledge of version control systems like Git. Excellent problem-solving skills and attention to detail. Ability to work effectively in a team environment and communicate technical ideas clearly.

Skills/Experience: Proficient in Scan, specializing in ATPG and Pattern verification at Block and Full chip level. Skilled in Scan insertion, ATPG, DRC analysis, Low Coverage Analysis, JTAG and IJTAG. Experienced in scripting for flow automation, using Siemens tools (Tessent), Synopsys tools (DFTMAX, Tetra MAX, VCS, DFT Compiler), Verdi. Familiar with tools: NC-SIM/Irun, Sim-Vision, XCELIUM. Experience (years) : 3+ Year Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Mirafra Technologies Hiring DFT Engineers: Experience - 5 to 10 years Notice Period - 0 to 90 days (30 days or lesser notice period will be preferred 1st) Location - Bangalore Please find the Job Description Below: 5+ years of relevant work experience in DFT. Good at Scan and ATPG. Hands on experience in various DFT aspects like Scan insertion, MBIST and JTAG, ATPG, Pattern validation at block level as well as Fullchip level. Synopsys tools: DFT MAX, TetraMAX OR Cadence tools: RTL Compiler, Encounter Test OR Mentor Graphics tools: Tessent tool chain, TestKompress - Debussy, VCS/Questa/IUS - PT tool from Synopsys . Tool Experience - Cadence Modus / Synopsys DFTMax/TetraMax / Mentor/Tessent Expertise in coverage improvement techniques Experience in - Stuck at, Transition, Deley faults, Bridging fault, IDDQ ATPG simulation - with SDF - should possess good debug skills Scripting experience - TCL/Shell/Perl/Python Tester/ATE Pattern debug. If Interested, please share your updated resume at ayeshabegum@mirafra.com Thanks and Regards, Ayesha Begum Senior Talent Acquisition Specialist Mirafra Technologies Email - ayeshabegum@mirafra.com Call- +91 - 9611647502

Strong fundamental knowledge of DFT techniques including JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IJTAG. and MBIST/LBIST. Experience in Tessent based ATPG flow, GLS and Post-silicon-debug. Hands-on in Perl/Tcl/Python scripting. Excellent analytical, and problem-solving skills. Perform Core and SOC level ATPG to meet Automotive grade quality. Hierarchical ATPG retargeting and Pattern release for application on ATE. Perform SOC and Core level Timing/Non-timing GLS. Silicon bring-up, diagnosis and support for physical failure analysis. Enable Emulation of Gate level SCAN patterns. Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

We are looking for skilled DFT Engineers with hands-on experience in RTL coding, scan insertion, ATPG, and coverage analysis to join our semiconductor engineering team. Key Responsibilities: Perform scan insertion, JTAG, ATPG DRC, and coverage analysis. Debug simulation with timing/SDF and root cause failures. Work on LBIST and Mixed Signal Radar ICs. Collaborate closely with design and verification teams. Ensure quality deliverables with proactive and detail-oriented work. Key Skills: Verilog / VHDL RTL coding Mentor DfT Tools, Cadence Tools Scan Insertion, JTAG, ATPG, Coverage Analysis LBIST, Mixed Signal Radar ICs (Preferred) Simulation Debug with Timing/SDF Soft Skills: Strong interpersonal and communication skills Proactive, collaborative, and self-motivated Ability to work independently and in a team

Role Overview We are seeking an experienced Lead DFT Engineer to join our team in Bengaluru. This is a full-time, on-site role where you will be responsible for designing and implementing advanced DFT architectures, performing coverage gap analysis, executing silicon debug and pattern reduction, and developing comprehensive test cases. You will lead projects, collaborate with cross-functional teams, and ensure delivery of high-quality solutions that meet or exceed client expectations. Key Responsibilities Lead DFT design and implementation across multiple SoCs. Drive ATPG, MBIST, BSCAN, and silicon bring-up activities. Develop and manage DFT constraints from bring-up to final delivery. Conduct thorough silicon debug, pattern reduction, and coverage analysis. Mentor and guide junior team members to achieve optimal results. Interface effectively with clients, presenting solutions and discussing technical options. Qualifications & Experience Proven experience leading a DFT team for at least two SoC projects . Strong hands-on expertise in ATPG, MBIST, BSCAN , and silicon bring-up. Solid understanding of DFT constraints and their integration in the design process. Excellent leadership, mentoring, and problem-solving skills. Strong communication skills to interact with internal teams and clients. Compensation Competitive and based on experience, including track record in successfully building and managing DFT teams. Show more Show less

You will be responsible for driving DFT implementation in Wireless SoC chips. You will have full ownership of ATPG architecture, design, implementation, verification, and deployment to Silicon testing, collaborating with Test engineers. Your duties will also involve MBIST design, implementation, and verification for all memories in the SoC. You should be capable of generating and debugging DFT patterns on the tester. You will work closely with the design, design-verification, and backend teams to facilitate the integration and validation of the test logic in all phases of the design and backend implementation flow. To excel in this role, you are required to have 8-10 years of experience and a B.Tech/M.Tech degree in ECE or EEE. You must possess full-chip DFT working experience with multiple design Tape Outs and expert knowledge of DFT architecture on complex Designs with multiple clock domains. Furthermore, experience in ATPG for pattern generation and simulation of Test Transition faults, Stuck-at, IDDQ, at-speed faults is essential. Hands-on experience in industry-standard DFT tools like Mentor Tessent suite or Synopsys DFT compiler is also a must-have. Your responsibilities will also include block-level and chip-level SCAN insertion, DRC, Coverage Analysis, and improvements. Expertise in Scan Compression (EDT/OPMISR+), MBIST, ATPG implementation, and verification is crucial. You should have expert knowledge of Test time reduction, good knowledge of cross-functional domains (SYN, LEC, STA, PD) with ownership of constraints developments & LEC. Developing/automating flows and scripts in Perl/Tcl to enhance the DFT methodologies & process is expected from you. Experience working with cross-functional global teams, Low-Power DFT requirements, and Low-Power MBIST architectures and Memory testing is also necessary. Preferred qualifications include experience in DFT related RTL integration, excellent communication and analytical skills, experience in leading junior teams, mentoring/training, and project leadership, as well as exceptional problem-solving skills. In addition to the challenging work environment, you can look forward to benefits such as Equity Rewards (RSUs), Employee Stock Purchase Plan (ESPP), insurance plans with Outpatient cover, National Pension Scheme (NPS), flexible work policy, and childcare support. Join us and be a part of a highly skilled team where every engineer's contribution significantly impacts the product, while also enjoying a good work/life balance and a welcoming and fun work environment.,

Position: Sr. Design Lead- DFT Experience: 8+ relevant experience. Location -India Education: B.Tech/M.Tech To be successful in this role you will: Seeking highly motivated, energetic, team-oriented Individual contributors willing to take the challenge of delivering of complex IPs using the latest advance Designfor Testskillsand Tools . Technical Skillset Required: Good knowledge in DFT Skills Sound knowledge in DFT Architecture and hands on in Scan , ATPG , Simulation & GLS . Prior experience in Synsopsys or Cadence or Mentor toolsLike Tetramax, Modus ,Tessentand DC tools Hands on in MBIST insertion and simulation Knowledgeon JTAG is an added advantage . Good Simulation debugging skills Technical Documentation: uArchitecture Specification, SoC Integration Specification Good exposure to Scripting skills like Perl or Python or Shell or TCL .

Position: Sr. Design Lead- DFT Experience: 8+ relevant experience. Location -India Education: B.Tech/M.Tech To be successful in this role you will: Seeking highly motivated, energetic, team-oriented Individual contributors willing to take the challenge of delivering of complex IPs using the latest advance Designfor Testskillsand Tools . Technical Skillset Required: Good knowledge in DFT Skills Sound knowledge in DFT Architecture and hands on in Scan , ATPG , Simulation & GLS . Prior experience in Synsopsys or Cadence or Mentor toolsLike Tetramax, Modus ,Tessentand DC tools Hands on in MBIST insertion and simulation Knowledgeon JTAG is an added advantage . Good Simulation debugging skills Technical Documentation: uArchitecture Specification, SoC Integration Specification Good exposure to Scripting skills like Perl or Python or Shell or TCL .

Position:Sr. Design Engineer 2- DFT Experience: 6+ relevant experience. Location -India Education: B.Tech/M.Tech To be successful in this role you will: Seeking highly motivated, energetic, team-oriented Individual contributors willing to take the challenge of delivering of complex IPs using the latest advance Designfor Testskillsand Tools . Technical Skillset Required: Good knowledge in DFT Skills Sound knowledge in DFT Architecture and hands on in Scan , ATPG , Simulation & GLS . Prior experience in Synsopsys or Cadence or Mentor toolsLike Tetramax, Modus ,Tessentand DC tools Hands on in MBIST insertion and simulation Knowledgeon JTAG is an added advantage . Good Simulation debugging skills Technical Documentation: uArchitecture Specification, SoC Integration Specification Good exposure to Scripting skills like Perl or Python or Shell or TCL .

Position: Sr. Design Engineer 1 Experience: 4+ relevant experience. Location -India Education: B.Tech/M.Tech To be successful in this role you will: Seeking highly motivated, energetic, team-oriented Individual contributors willing to take the challenge of delivering of complex IPs using the latest advance Designfor Testskillsand Tools . Technical Skillset Required: Good knowledge in DFT Skills Sound knowledge in DFT Architecture and hands on in Scan , ATPG , Simulation & GLS . Prior experience in Synsopsys or Cadence or Mentor toolsLike Tetramax, Modus ,Tessentand DC tools Hands on in MBIST insertion and simulation Knowledgeon JTAG is an added advantage . Good Simulation debugging skills Technical Documentation: uArchitecture Specification, SoC Integration Specification Good exposure to Scripting skills like Perl or Python or Shell or TCL .

Position:Sr. Design Engineer 2- DFT Experience: 6+ relevant experience. Location -India Education: B.Tech/M.Tech To be successful in this role you will: Seeking highly motivated, energetic, team-oriented Individual contributors willing to take the challenge of delivering of complex IPs using the latest advance Designfor Testskillsand Tools . Technical Skillset Required: Good knowledge in DFT Skills Sound knowledge in DFT Architecture and hands on in Scan , ATPG , Simulation & GLS . Prior experience in Synsopsys or Cadence or Mentor toolsLike Tetramax, Modus ,Tessentand DC tools Hands on in MBIST insertion and simulation Knowledgeon JTAG is an added advantage . Good Simulation debugging skills Technical Documentation: uArchitecture Specification, SoC Integration Specification Good exposure to Scripting skills like Perl or Python or Shell or TCL .

Position: Sr. Design Engineer 1 Experience: 4+ relevant experience. Location -India Education: B.Tech/M.Tech To be successful in this role you will: Seeking highly motivated, energetic, team-oriented Individual contributors willing to take the challenge of delivering of complex IPs using the latest advance Designfor Testskillsand Tools . Technical Skillset Required: Good knowledge in DFT Skills Sound knowledge in DFT Architecture and hands on in Scan , ATPG , Simulation & GLS . Prior experience in Synsopsys or Cadence or Mentor toolsLike Tetramax, Modus ,Tessentand DC tools Hands on in MBIST insertion and simulation Knowledgeon JTAG is an added advantage . Good Simulation debugging skills Technical Documentation: uArchitecture Specification, SoC Integration Specification Good exposure to Scripting skills like Perl or Python or Shell or TCL .

Position: Design Lead- DFT Experience: 7+ relevant experience. Location -India Education: B.Tech/M.Tech To be successful in this role you will: Seeking highly motivated, energetic, team-oriented Individual contributors willing to take the challenge of delivering of complex IPs using the latest advance Designfor Testskillsand Tools . Technical Skillset Required: Good knowledge in DFT Skills Sound knowledge in DFT Architecture and hands on in Scan , ATPG , Simulation & GLS . Prior experience in Synsopsys or Cadence or Mentor toolsLike Tetramax, Modus ,Tessentand DC tools Hands on in MBIST insertion and simulation Knowledgeon JTAG is an added advantage . Good Simulation debugging skills Technical Documentation: uArchitecture Specification, SoC Integration Specification Good exposure to Scripting skills like Perl or Python or Shell or TCL .

Position: Design Lead- DFT Experience: 7+ relevant experience. Location -India Education: B.Tech/M.Tech To be successful in this role you will: Seeking highly motivated, energetic, team-oriented Individual contributors willing to take the challenge of delivering of complex IPs using the latest advance Designfor Testskillsand Tools . Technical Skillset Required: Good knowledge in DFT Skills Sound knowledge in DFT Architecture and hands on in Scan , ATPG , Simulation & GLS . Prior experience in Synsopsys or Cadence or Mentor toolsLike Tetramax, Modus ,Tessentand DC tools Hands on in MBIST insertion and simulation Knowledgeon JTAG is an added advantage . Good Simulation debugging skills Technical Documentation: uArchitecture Specification, SoC Integration Specification Good exposure to Scripting skills like Perl or Python or Shell or TCL .

As a Design Manager at Texas Instruments, you will have the opportunity to lead a team of RTL front end, Digital Back end & Design verification engineers. Your primary responsibilities will include directing and guiding the activities of a research or technical design function, overseeing the design, development, modification, and evaluation of digital electronic parts, components, or integrated circuitry for electronic equipment and hardware systems. You will evaluate the final results of research and development projects to ensure the accomplishment of technical objectives. Additionally, you will be involved in preparing and presenting reports outlining the outcomes of technical projects and making recommendations for actions necessary to achieve desired results. In this role, you will play a key part in selecting, developing, and evaluating personnel to ensure the efficient operation of the function. Joining Texas Instruments as a Design Manager (RTL, P&R, Design Verification) will allow you to work with a team of enthusiastic engineers focused on developing highly complex and industry-leading devices for audio applications. You will be involved in developing new Audio converters catering to PE, Automotive, and Industrial market segments, with the digital content including a DSP for digital filters and audio signal processing blocks among various other IPs. Collaboration with various engineering teams within the product line, including analog design, layout, firmware, verification, validation, test, systems, applications, and marketing, will be a part of your role to successfully execute new products from concept to volume production and subsequent support. As a core member of the design team, you will drive flawless execution by finding innovative design architecture and solutions through out-of-the-box thinking to deliver highly differentiated products. This is an exceptional opportunity to be part of a team that is continuously seeking growth opportunities, working with leading customers globally, and developing cutting-edge solutions in consumer electronics, industrial, and automotive markets. To qualify for this position, you must hold a minimum bachelor's degree in electrical engineering and have at least 7 years of experience. Strong aptitude, hands-on experience in RTL frontend design, excellent command of RTL design concepts, and the ability to work with dynamically evolving requirements are some of the key qualifications needed for this role. You should also possess a result-driven attitude, the ability to mentor team members, and familiarity with digital backend flow and design verification flow. Preferred qualifications for this role include establishing strong relationships with key stakeholders, strong verbal and written communication skills, hands-on experience with Digital Back end tools, and the ability to quickly ramp up on new systems and processes. Demonstrated interpersonal, analytical, and problem-solving skills, ability to collaborate effectively with cross-functional teams, and strong time management skills are also desirable qualities for this position. As a Design Manager at Texas Instruments, you will be responsible for leading a team of 7+ engineers and multiple contractors, driving results while striving for excellence in the complete Digital (Front and Backend) & Design verification team. Your role will also involve overseeing the career growth of your team members. If you are passionate about engineering and shaping the future of electronics, Texas Instruments offers a collaborative environment where employees are empowered to own their career and development. Join us to work with some of the smartest people in the industry and contribute to creating a better world through affordable semiconductor technology. Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company dedicated to designing, manufacturing, and selling analog and embedded processing chips for various markets. Our core passion is to make electronics more affordable through innovative semiconductor solutions. We value diversity and inclusion in our work environment and strive to empower our employees to drive innovation forward. At Texas Instruments, we believe in creating a diverse, inclusive work environment and are an equal opportunity employer. If you are interested in this position, please apply to this requisition.,

Strong on Digital Design, SV, UVM. Hands-on experience in any of the DV protocols like PCIe, USB 3.0, DDR 3/4/5, AMBA, Ethernet (10G/100G), SATA, and MIPI (CSI/DSI), UFS, CXL Also Hiring PD, RTL, DFT Apply& Share resume to mansoor@hisoltech.com

KEY RESPONSIBILITIES: Implementation and verification of DFT features likeSCAN, MBIST, LBIST and JTAG SupportSpyglass-DFTDRC debug and coverage correlation Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning PREFERRED EXPERIENCE: Experience in scan-stitching; and has good knowledge of scan-stitching related concepts Exposure to MBIST/BISR implementation and with the Tessent flow of mbist-insertion Excellent hands-on ATPG; and is we'll conversed with the files required to run ATPG Knowledge/experience with Tessent ATPG (mentor) is a plus Knowledge on Spyglass-DFT Excellent hands-on debug skills and scripting skills are critical Knowledge on automation scripts like TCL/AWK/SED is a plus Understands the basics of JTAG Experience with post-silicon bring up is a plus ACADEMIC CREDENTIALS: Bachelors degree w/7+ years or Masters degree w/5+ years in Electronics engineering/Electrical Engineering

We are seeking an experienced and highly skilled Senior SOC Design for Test Engineer with aminimum of 5 years of hands-on experience in SOC Design for Test. As a key member of our team, you will play a pivotal role in ensuring the testability, manufacturability, and quality of our cutting-edge System on Chip designs Key Responsibilities Lead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution coverage, manufacturability, and quality plans. Develop full chip and block level DFT implementation from the DFx Specifications and product coverage, quality, and manufacturability goals. Define and implement Test controllers at top level and block level, fuse controllers, test clocking strategy, chip I/O test strategy and HSIO test strategy. Define JTAG TAP, boundary scan, I/O Test JTAG access, IEEE1687 iJTAG network and instrument design and implementation. Define the Test Interface for each of the P&R IP blocks for Scan, MBIST and other test interfaces. Define hierarchical block isolation, Test clocking and On Chip Clock controllers and reset methodology. Define scan and MBIST timing at the top level and block level timing. Analyse block level RTL or gates to ensure that scalability and coverage is satisfied as per the design goals. Ensure that DFT is provided to fix the DFT violations to ensure that the design goals are meet. Analyse compression requirements for each of the blocks, define Intest and Extest compression requirements and define the requirements for compression engines. Synthesize compression engines for each of the blocks. Create the collaterals for compression for the IPs. Block level scan insertion as well as development of the scan wrappers for the blocks. Do scan insertion on the blocks, analyse scan DRC, implement DFT fixes. Create scan protocol files for designs, create scan inserted netlist, create scan definitions as well as scan definition files for PD. Perform ATPG on the scan inserted netlist, analyse DRC and coverage violations. Deep knowledge of different scan models Stuck-at, transition test, path-delay, bridging, cell aware, small-delay transition, IDDQ test etc. Ability to analyse coverage for each of the model types. Running GLS with or without timing for the scan vectors. Ability to debug the failures and working with timing and PD teams to fix the timing issues. Understanding of pattern delivery to the post-silicon test engineering teams. Delivering to the Test engineering the Test pin muxing and other full chip requirements for the Test Engineering Team. Understanding tester requirements and delivering the patterns in the formats that the tester teams needs. Implement pattern retargeting. Create grey box models for blocks. Coverage analysis of full chip consolidating Intest and Extest patterns. Knowledge of Top level scan architecture and creating flow to create pattern retargeting. Knowledge of Streaming Scan Network and other Top level scan pin sharing and implementing the block to top level pattern generation for this flow. Implementing Memory Testing and MBIST. Knowledge of Memory defect models and test algorithms. Knowledge of memory bit mapping and redundancy analysis. Implementing memory repair and fuse sharing among various memory. Knowledge of LogicBIST with Test point insertion, X-blocking. Full chip DFT delivery for tapeout including but not limited to DFT netlist verification, pattern delivery, Tester requirements. Debug DFT patterns post silicon, ability to analyse chain test patterns for failures, scan pattern failures. Analyse MBIST pattern failures, yield and repair debug. Ability to perform volume diagnostics on the parts to isolate and improve the patterns. Requirements Bachelors degree in computer science, Electrical/Electronics Engineering, or related field. OR masters degree in computer science, Electrical/Electronics Engineering, or related field. OR PhD in Computer Science, Electrical/Electronics Engineering, or related field. 5+ years of hands-on experience in SOC Design for Test. Expertise in DFT tools and flows in scan intertion, ATPG, GLS simulation, diagnosis flows. Prior experience working on IP level and SOC level DFT projects. Proficient in DFT tools from Siemens (Tessent), Synopsys DFTmax, Tetramax, Spyglass DFT advisor, Genius DFT, Modus, VCS, Xcelium etc. Worked in full chip design or complex IP delivery in the area of DFT. Experience in post silicon debug, diagnosis and yield enhancements is a plus.

Location :- Bangalore Experience :- 12-20 years Required Skills And Experience: This role is for a Principal DFT engineer with 15 years plus experience Technical leadership in DFT and ability to train/work with junior team members Experience with Perl, TCL, and/or python with ability to build and deploy generic DFT flows Proficient in Unix/Linux environments One or more core DFT skills are considered crucial for this position including some of the following Knowledge of at-speed testing, test insertion and test coverage assessment, test pattern development, scan compression, Memory BIST, Logic BIST, JTAG, IJTAG, fault simulation, debug, verification, SSN, designing and conducting experiments/tool evaluations. Experience with Siemens, Cadence and/or Synopsys DFT tools Qualified candidates will have a university degree (or equivalent) in Electronic Engineering, Computer Engineering, or other relevant technical subject area.