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Capgemini
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DFT Engineer

DFT Engineer

Capgemini

3 - 7 years

5 - 9 Lacs

bengaluru

Posted:2 days ago| Platform:

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Skills Required

bist atpg scan insertion dft mbist synthesis jtag vlsi design scanning simulation version control digital design rtl vhdl verilog linux perl system verilog tcl ncsim

Work Mode

Work from Office

Job Type

Full Time

Job Description

Job Summary:

We are seeking a skilled DFT Engineer to join our semiconductor design team. The ideal candidate will have experience in implementing design-for-testability techniques to ensure high-quality and testable silicon designs. You will work closely with RTL designers, verification teams, and test engineers to develop and validate DFT strategies for complex SoC designs.

Key Responsibilities:

Develop and implement DFT architectures including scan insertion, ATPG (Automatic Test Pattern Generation), BIST (Built-In Self-Test), and boundary scan.
Collaborate with RTL designers to integrate test logic efficiently without impacting design performance.
Perform test coverage analysis and optimize test patterns to maximize fault coverage.
Support ATPG and fault simulation to validate test patterns.
Work with physical design teams to ensure DFT features are preserved during implementation.
Debug and diagnose silicon failures related to test structures.
Participate in design reviews to ensure DFT compliance and quality.
Develop scripts and tools to automate DFT processes.
Keep updated with the latest DFT methodologies and industry trends.

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DFT Engineer