DFT Engineer

Responsibilities:

• Willbe responsible forDesigning and Implementing DFT techniques.
• Shouldhavaa good understanding of Memory BIST/Scan /OnChipCompression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/LogicBIST oncomplex SOCs to improve testability.
• Test Modes implementation and verification, scan insertion including on-chip compression.
• Implementing,integratingand verifying memory BIST and boundary scan.
• ATPG Test vector (Stuck-at/At-speed/Path delay/SDD/IDDQ/Bridging fault) generation with hightest Coverageand simulations at gate level with timing (SDF).
• Basic understanding of complete SOC design and flow.
• Cross functionalteamsinteraction for issue resolution.
• Participatein driving new DFTmethodologyand solutions to improve quality, reliability andinsystemtest and debug capability.
• Hiringcandidatewith these specific personalcharacteristicand qualifications.
• Mentoring junior engineers anddriveinnovation/automation.
• Excellent in problem solving and analytical skills.
• Excellent communication,team workand networking skills.

Primary Skills

• Should HaveGoodunderstanding of Design and DFT Architecture.
• Should have been partofatlest3TapeoutSoC.
• Well Versed with ATPG Tools & MBIST Tools.

Secondary Skills

• Team Player, Strong Business Acumen with understanding of organizational issues (conflict resolution between stakeholders).
• Familiarity with Desired Flexibility and adaptability with respect to project management.