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8.0 - 12.0 years
38 - 40 Lacs
bengaluru, karnataka, india
On-site
Responsibilities: Willbe responsible forDesigning and Implementing DFT techniques. Shouldhavaa good understanding of Memory BIST/Scan /OnChipCompression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/LogicBIST oncomplex SOCs to improve testability. Test Modes implementation and verification, scan insertion including on-chip compression. Implementing,integratingand verifying memory BIST and boundary scan. ATPG Test vector (Stuck-at/At-speed/Path delay/SDD/IDDQ/Bridging fault) generation with hightest Coverageand simulations at gate level with timing (SDF). Basic understanding of complete SOC design and flow. Cross functionalteamsinteraction for issue resolution. Participa...
Posted 23 hours ago
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