1 Soc Tapeout Jobs

Setup a job Alert
JobPe aggregates results for easy application access, but you actually apply on the job portal directly.

8.0 - 12.0 years

38 - 40 Lacs

bengaluru, karnataka, india

On-site

Responsibilities: Willbe responsible forDesigning and Implementing DFT techniques. Shouldhavaa good understanding of Memory BIST/Scan /OnChipCompression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/LogicBIST oncomplex SOCs to improve testability. Test Modes implementation and verification, scan insertion including on-chip compression. Implementing,integratingand verifying memory BIST and boundary scan. ATPG Test vector (Stuck-at/At-speed/Path delay/SDD/IDDQ/Bridging fault) generation with hightest Coverageand simulations at gate level with timing (SDF). Basic understanding of complete SOC design and flow. Cross functionalteamsinteraction for issue resolution. Participa...

Posted 23 hours ago

AI Match Score
Apply
cta

Start Your Job Search Today

Browse through a variety of job opportunities tailored to your skills and preferences. Filter by location, experience, salary, and more to find your perfect fit.

Job Application AI Bot

Job Application AI Bot

Apply to 20+ Portals in one click

Download Now

Download the Mobile App

Instantly access job listings, apply easily, and track applications.

Featured Companies