9 Memory Bist Jobs

As a Senior DFT engineer with over 10 years of experience in SoC DfT implementation and verification of scan architectures, JTAG, memory BIST, ATPG, and LBIST, you will play a crucial role in ensuring the design quality and functionality of complex semiconductor devices. Your educational background should include a BE/ME/B.Tech/M.Tech degree from reputed institutes with a 1st class degree and a minimum of 5 years of relevant industry experience. Your expertise in Verilog/VHDL RTL coding and proficiency in using Mentor DfT tools and Cadence tools will be essential for success in this role. You will be responsible for tasks such as scan insertion, JTAG, LBIST, ATPG, DRC, and coverage analysis, as well as simulation debug with timing/SDF. It is expected that you have hands-on experience working on at least one SoC project from start to end. In addition to technical skills, you should possess qualities such as proactiveness, collaboration, and attention to detail. The ability to exercise independent judgment, debug issues, and identify root causes of simulation failures is crucial for this position. Strong interpersonal skills, effective communication (both oral and written), and self-motivation are also key attributes that will contribute to your success. At NXP in India, we value individuals who exhibit curiosity, a desire to understand the underlying mechanisms of their work, and a continuous drive for learning and improvement. If you are someone who thrives in a dynamic and challenging environment, where your contributions can make a significant impact, we encourage you to apply and join our team.,

You should have experience in designing and implementing test methodologies for large, complex SoCs. You must be capable of resolving scan issues in complex multi-clock domain designs, developing DFT strategies for complex System-On-Chip designs, and generating & integrating Memory BIST, JTAG, SCAN/ATPG. You should be an expert in analyzing fault coverage, delay fault, and enhancements. Experience in developing and running scan insertion scripts, performing ATPG simulation & analyzing results is required. Expertise in Mentor / Synopsys DFT tools and debug skills in a Verilog design environment is essential. Experience with static timing analysis (STA) & formal verification is desirable. Proficiency in common UNIX scripting languages (perl, tcl, csh, sh) is a must. Kindly email your resume to careers@perfectus.com with Job Code DFT in the subject line.,

Key Responsibilities: Ownership of Scan/ATPG and MBIST flows for complex SoCs Expertise in Synopsys tools , especially SMS (Synopsys Memory Solution) Deep understanding of MBIST architecture and memory repair techniques Hands-on experience with Scan insertion and ATPG for large devices using hierarchical DFT flows Debug and support issues during DFT implementation and silicon bring-up Collaborate closely with RTL, PD, and test engineering teams

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Job Responsibilities Responsible for Corporate Application Engineering (CAE) activities in the Design for Test (DFT) Domain of VLSI systems From a technical stand-point, understanding customer needs on DFT, involve and work with their projects for using right methodologies and Siemens tools for successful project completion Provide DFT Tool support to all the existing customers. Help customers improve the productivity through efficient tool usage. Provide onsite tool support to customers as and when needed Developing and delivering technical training on new features and product updates Tracking and updating customer issues using defined Siemens processes and tracking tools. Developing Technical content for Siemens knowledgebase. Involve and drive the Tool evaluation/benchmark; Technical product presentations; Methodology review; Tool deployment and adoption; drive competitive replacements, provide support to customers during critical project implementation phases. Educational qualifications: Required BE/B.Tech in Electronics & Communications Engineering (E&C), or Electrical and Electronics Engineering (EEE) Work Experience: 4+ years relevant experience in DFT area of VLSI domain. Technical skills: In additional to possessing hands-on knowledge of DFT implementation and verification, the position would need excellent problem solving & communication skills able to work independently to solve complex problems and device new solutions and workarounds for customer issues. Knowledge and experience with VLSI design, HDL Synthesis, VLSI Testing and design for testability. Experience with design, simulation, verification of ASIC/VLSI circuits and systems, design verification and product test generation preferred. In-depth understanding of Design for Test (DFT) structures is required. This includes ATPG/Scan/Compression based testing, Memory BIST, Logic BIST, IJTAG and Boundary Scan (1149.1/6). Knowledge of scan data compression methodologies with EDT is preferred. Preferred experience in specific areas: Operating SystemsUNIX, Linux, Sun Solaris. LanguagesVerilog (Behavioral, RTL, gate level), VHDL (Behavioral, RTL, gate level), Perl, C/C++. CAD ToolsSynthesis, Simulation, ATPG, Memory BIST, Logic BIST, Boundary Scan. Familiarity with Tessent flows and methodologies is a plus. General/soft skills: Work effectively with customers, internally with divisions and R&D Ability to work autonomously Strong verbal and written communication skills; good presentation skills Excellent organizational and time management skills Build and foster relationships with customer and peers with a positive attitude to win business success Good problem solving and debugging skills, Willingness for technical sales Should be a good team player Job may require some domestic and international travel. #DISW #LI-EDA #LI-Hybrid A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! At Siemens, we are always challenging ourselves to build a better future. We need the most innovative and diverse Digital Minds to develop tomorrows reality. Find out more about the Digital world of Siemens here:/digitalminds Siemens Software. Where today meets tomorrow

Roles and Responsibility 5 years to 15 yrsdesign experience. Experience withowning chip level DFT and Post Silicon debug / analysis. Understanding of DFTarchitectures like JTAG, Scan Compression Techniques (XOR, Adaptive, OP-MISRetc.), scan chain insertion and verification. Must have experiencegenerating scan patterns and coverage statistics for various fault models likestuck at(Nominal and VBOX), IDDQ, Transition faults, JTAG BSDL, patterngeneration for Memories(E-fuse etc.). Experience debugging tester failures ofscan patterns, diagnosis and pattern re-generation. Understandinggeneration of functional patterns for ATE Knowledge of atleast any one of an industry standard DFT tools (Cadence Modus, SynopsysTetramax, Mentor Tessent Tools, etc) Design experience inMBIST / LBIST is an added advantage. Good understandingof constraints development for Physical Design Implementation / Static TimingAnalysis. Responsibilities: Must have experience generating scan patterns andcoverage statistics for various fault models like stuck at(Nominal and VBOX),IDDQ, Transition faults, JTAG BSDL, pattern generation for Memories(E- fuseetc.). Experience debugging tester failures of scan patterns, diagnosis andpattern re-generation. Understanding generation of functional patterns forATE Knowledge of at least any one of an industrystandard DFT tools (Cadence Modus, Synopsys Tetramax, Mentor Tessent Tools,etc) Design experience in MBIST / LBIST is an addedadvantage. Good understanding of constraints development forPhysical Design Implementation / Static Timing Analysis. Desired Skills: Preferred Skills/ Experience Experience with TCL / Perl is preferred. Understanding of IC design with Analog circuits andit s design cycles is an added advantage. Effective communication skills to interact with allstakeholders. Team and People Skills: The candidate should havegood people skills to work closely with the systems, analog, layout and testteam Must be highly focused and remain committed toobtaining closure on project goals Role: DFT Engineer Department: Design For Test & Debug Employment Type: Full Time, Permanent

Like Requirements: 5 to 10 years of hands-on experience in DFT methodologies , with expertise in Scan & ATPG, MBIST Strong knowledge of DFT tools such as Synopsys, Mentor Graphics, or Cadence. Experience in fault modeling, pattern generation, and coverage analysis . Proficiency in scripting (TCL, Python, Perl, or Shell) for automation. Excellent problem-solving skills and ability to work in a fast-paced environment. Job Responsibilities: Implement and validate DFT architectures for complex SoCs. Perform scan insertion and ensure proper integration into the design. Develop and optimize ATPG patterns to achieve high fault coverage. Work closely with RTL, verification, and physical design teams to resolve DFT-related issues. Support post-silicon bring-up, debug, and ATE (Automated Test Equipment) testing.

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Understand the design specification , Memory and Memory BIST engine connections Develop the verification environment and test bench and creating testcases. Debug fails using waveform, trace tools and debug RTL code Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5 + years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in DFT Verification - Demonstrated execution experience of verification of Memory BIST Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good object-oriented programming skills in C/C++, and any of scripting languages like Python/Perl Development experience on Linux/Unix environments and in GIT repositories and basic understanding of Continues Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in verification coverage closure Hardware debug skills backed by relevant experience on projects Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , etc Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Role: DFT Engineer Experience Required: 5-15 Years Location: Bangalore, Hyderabad, Noida, Ahmedabad, and Pune Will be responsible for Scan insertion and validation, BIST, MBIST insertion and validation, ATPG, IP Tests, and Pattern validation w/wo Timing, DFT mode timing analysis, and sign off. Be responsible for a comprehensive DFT plan Incumbent to work with DFT and cross-functional teams To architect and implement solutions for Scan and built-in self-test (Memory and Logic BIST) circuitry to test devices in the field ESSENTIAL SKILLS & EXPERIENCE Strong fundamentals on DFT and ASIC cycle. Sound expertise in Tcl, Perl, and Shell scripting. Technically sound & good team player Hands-on experience with DFT implementation using standard EDA and flow is a must. Interested candidates can send in their profile to bindu@logicalhiring.com or careers@logicalhiring.com References are welcome! For other open roles, please visit - www.logicalhiring.com

Role Description This is a full-time on-site role for DFT Engineer at Incise Infotech Pvt. Ltd. DFT Engineer will be responsible for developing, implementing, and verifying the Design for testability (DFT) on complex system on chips (SOCs). The role also involves working with the physical design team to ensure the DFT requirements are met and with the verification team to ensure the DFT design is meeting the test coverage metrics. The ideal candidate will have experience in SOC level DFT techniques, ATPG, MBIST, JTAG, and boundary scan. Qualifications Bachelor's or Master's degree in Electrical/Electronics Engineering or equivalent 3+ years of experience in DFT domain Expertise in DFT methodologies - scan insertion, scan compression, boundary scan, and memory BIST Experience in DFT tools like Tessent, ATPG, MBIST, and JTAG Experience in the complete scan chain flow (ATPG, simulation, and test pattern generation) on complex SOCs Knowledge of STA, LEC, and physical design aspects related to DFT Experience in Shell/Perl/Tcl and other scripting languages Good communication skills and the ability to work well in a team environment Interested can share resume on Shubhanshi@incise.in