1568 System Verilog Jobs

Role Overview: Eridu AI India Private Limited, a subsidiary of Eridu Corporation based in California, USA, is seeking a highly motivated RTL Data Path Engineer to join their R&D center in Bengaluru. As part of the Design Group, you will play a key role in defining, specifying, architecting, executing, and productizing cutting-edge Networking devices to shape the future of AI Networking. Key Responsibilities: - Design and architect solutions for high-speed networking devices, focusing on latency optimization, memory management, and quality of service (QoS) support. - Implement designs on ASIC platforms, ensuring compliance with industry standards and performance benchmarks. Conduct thorough testing and validation for functionality and reliability. - Analyze and optimize memory/buffering to improve performance metrics. - Provide support for various networking protocols and standards related to input and output queues, including Ethernet. - Investigate and resolve complex issues related to packet queuing, working closely with cross-functional teams. Qualifications: - BE/ME with 8-15 years of experience. - Working knowledge of system Verilog and Verilog is mandatory. Prior experience with ownership of memory subsystems. - Proven expertise in designing and optimizing memory algorithms and QoS mechanisms for high-speed networking devices. - Solid understanding of ASIC design methodologies, including simulation and verification tools (e.g. Synopsys, Cadence). - Experience with Ethernet/PCIe networking protocols. - Strong analytical and problem-solving abilities with meticulous attention to detail in troubleshooting complex networking issues. - Excellent verbal and written communication skills, with the ability to collaborate effectively in a team environment and present technical information to diverse audiences.,

Role Overview: At NVIDIA, you will be part of a team passionate about parallel and visual computing, dedicated to transforming the way graphics are utilized to address complex problems in computer science. From simulating human imagination to running deep learning algorithms, NVIDIA's GPUs are at the forefront of technology, driving innovations in various fields like video games, Hollywood films, self-driving cars, and artificial intelligence. As a team member, you will have the opportunity to contribute to amplifying human imagination and intelligence, shaping the future of computing. Key Responsibilities: - Apply best-in-class formal methodologies to verify complex digital designs, IP blocks, and SoCs - Take ownership of verifying a design by developing a robust test plan and collaborating with the design team - Coordinate with other verification team members to ensure closure on verification tasks Qualifications Required: - B.Tech./ M.Tech. with 5+ years of relevant experience - Strong analytical skills to solve challenging problems - Understanding of abstraction techniques for effective verification - Hands-on experience with HDLs such as Verilog / System Verilog - Ability to quickly comprehend RTL design - Understanding of temporal logic assertions No additional details of the company were provided in the job description.,

Role Overview: As an Individual contributor in the field of VLSI Frontend, Backend, or Analog design, you will be responsible for executing internal projects or small tasks of customer projects under minimal supervision from the Lead. Your main task will involve working on any one task of RTL Design/Module in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff. Key Responsibilities: - Analyse and complete the assigned task in the defined domain(s) successfully on-time with minimal support from senior engineers - Ensure quality delivery as approved by the senior engineer or project lead - Deliver clean modules that are easy to integrate at the top level - Ensure functional specifications and design guidelines are met without deviation - Document tasks and work performed - Meet project timelines as provided by the team lead/program manager - Support team members in their tasks and perform additional tasks if necessary - Plan approaches towards repeated work by automating tasks to save design cycle time - Participate in technical discussions Qualifications Required: - Bachelors or Masters degree in Electrical/Electronics Engineering or related field - 2-3 years of AMS Verification experience - Strong knowledge of analog and digital design fundamentals - Experience with simulation and verification tools like Cadence Spectre, Xcelium, AMS Designer, or similar - Familiarity with scripting languages (Python, Perl, or Tcl) for automation - Understanding of UVM or other verification methodologies is a plus - Experience in modeling using Verilog-AMS or SystemVerilog - Prior work on silicon-proven IPs or SoCs - Knowledge of power-aware verification or low-power design techniques About the Company: UST is a global digital transformation solutions provider with over 30,000 employees in 30 countries. UST partners with clients from design to operation, embedding innovation and agility into their clients" organizations. With deep domain expertise and a future-proof philosophy, UST aims to make a real impact through transformation, touching billions of lives in the process.,

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Physical Place and Route. Experience: 3-5 Years.

Dear Candidate We have immediate job openings for Design verification openings Exp : 3-10 years Location : Bangalore NP : less than 45 days Job details : Develop and maintain UVM-based verification environments. Define and review verification test plans with architecture and design teams. Perform design verification using directed and constraint-random tests. Maintain regression runs and debug test failures with designers. Report and analyze verification coverage metrics. Drive verification to achieve full coverage goals. Own verification of IP blocks, sub-systems, and top-level environments. Thanks Gayathri

Dear Candidate We have immediate job openings for Design verification openings Exp : 3-10 years Location : Bangalore NP : less than 45 days Job details : Develop and maintain UVM-based verification environments. Define and review verification test plans with architecture and design teams. Perform design verification using directed and constraint-random tests. Maintain regression runs and debug test failures with designers. Report and analyze verification coverage metrics. Drive verification to achieve full coverage goals. Own verification of IP blocks, sub-systems, and top-level environments. Thanks Gayathri

Job Specs : Expertise in Digital Verification Expertise in Functional Verification Expertise in SOC / IP Verification Expertise in working on system Verilog assertions & test benches Expertise in working on OVM / UVM / VMM based verification flow Expertise in working on ARM processor Expertise in working on AMBA bus protocols (AXI, AHB, APB) Expertise in CXL or PCIe Protocol Verification Expertise in simulation tools (VCS, ModelSim, Questa) Expertise in driving Verification Strategy, writing Test Plan, developing Test Bench, Test cases. Expertise in analysing Code Coverage, Functional Coverage and Assertions. Expertise in verification of complex SoCs. Expertise in Test Plan creation and Verification technologies like Code Coverage, Functional coverage, assertion based verification. Expertise in Verification of complex datapath, DSP based ASICs Expertise in MAC Protocol: USB, WiFi , Bluetooth , PCIe is mandatory Good knowledge in gate-level simulation, and Scripting languages like Python, TCL Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan are the preferred work locations Preferred resources with valid regional work permit.

1. Minimum of three years of hands-on Test Development experience (DFT, EDA tools, etc..) 2. Solid knowledge & experience in defining test solutions for multi-million gate SOC (Scan & MBIST) with Mixed Signal IPs (PLL, High Speed SERDES, DDR) 3. Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test 4. Strong understanding of relationships between Hardware, Firmware and Software in FPGA and/or multi-processors SOC. Past experience in leading the team to successful silicon bring-up and problem solving in a complex system 5. Strong planning, project, and people management skills required. Must have experience developing managers and individual contributors 6. Experienced hands-on technical manager not afraid to dig into details to provide technical direction Proven track record of delivering results and meeting quality, cost, and time-to-market objectives 7. Ability to collaborate with overseas colleagues to define strategy, plan, and execute across the larger, global organization 8. Stakeholder influencing and people skills must be excellent. 9. Needs to be able to set aggressive goals and manage risks effectively 10. Must have a thorough understanding of tool development methodology. 11. Ability to manage software development tasks associated with specifying, developing, scheduling, and debugging according to current and future tool requirements. 12. MS or Ph.D. Engineering degree (EE or equivalent) with 3-7 years semiconductor industry experience.

Job Specs : Work with design and architecture teams to define and generate timing constraints that specify the desired timing requirements for the design. Set up and configure STA tools ( PrimeTime, StarRC, Tempus, Innovus and QRC ) for the analysis, including library characterization, delay models, and clock definitions Perform static timing analysis to evaluate setup and hold times, clock-to-q delays, and other timing metrics. Ensure that the design meets timing requirements for various corners and operating conditions (e.g., process, voltage, temperature variations). Identify and analyze asynchronous signals crossing between different clock domains to ensure proper synchronization and to avoid metastability issues. Define and analyze multicycle paths and false paths to accurately capture the designs timing constraints. Collaborate with RTL and physical design teams to achieve timing closure by optimizing the design or constraints. Perform incremental and formal ECO (Engineering Change Order) analysis to address timing issues. Work with CTS engineers to ensure that the clock tree meets timing requirements and minimizes clock skew and jitter. Perform post-layout STA to account for parasitic capacitance and resistance effects introduced during the physical design phase. Identify and resolve timing violations and sign-off on the final timing closure. Analyze timing margins to account for variability and manufacturing process variations, ensuring robust operation. Prepare detailed timing analysis reports, including timing paths, violations, and suggestions for timing optimization. Collaborate closely with RTL designers, physical designers, DFT (Design for Test) engineers, and verification teams to resolve timing-related issues. Contribute to the development and improvement of STA methodologies and flows to enhance efficiency and accuracy.Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Vietnam are the preferred work locations Preferred resources with valid regional work permit.

Job Description This position involves the development of complex SoC/chip architectures with multi-core, multi-threaded processor subsystems, AI accelerators, interconnects, memory architecture and multi-level caches, multiple clocks and resets, high-speed interfaces, peripherals. The chosen candidate would need to contribute to, and manage a team for, the development of architecture, microarchitecture, and design of SoCs which include RISC-V, ARM or proprietary processor designs, and high-speed interfaces for off-chip memories, along with the integration of wireless systems, power management, and mixed signal IP. The candidate would be responsible for the leading a project through the entire product development process. Responsibilities Lead the development and execution of Wireless SoC s from definition, through execution, and into production Definition and Planning Coordinate with the product marketing teams to develop the SoC requirements. Provide the necessary design collateral to support the product approval gates. Develop and maintain the SoC architecture or technical specification to meet the product requirements, with a key goal to maximize IP reuse. Develop the design schedule, including milestones and resource requirements. Coordinate with cross functional teams (such as software) on dependencies. Project Execution Coordinate with global design functional leads (RF, baseband, verification, etc) to track execution, triage issues, and perform prudent escalation. Represent the design community to provide succinct weekly status and attend the cross functional meeting. Drive design action items to closure. Perform SoC Design Integration and maintain design collateral such as documentation, register libraries, and pinouts delivered to cross functional teams. Follow established quality procedures and processes to achieve first tapeout. Validation to Production Actively support the validation and product test teams during silicon bringup, validation, characterization, and qualification. Triage, track, and resolve issues reported during silicon evaluation. Execute a metal or full layer revision, if necessary Experience Level: 12+ years in Industry Education Requirements: Bachelor or Master s degree in Electrical or Computer Engineering Qualifications: Capable of leading complex IP, SOC development projects execution. Experience coordinating with contractors a plus. Top-down planning and execution of SOC projects. Experience in full-chip development cycle Able to build strong technical team. Hands-on experience in architecture, micro-architecture, digital design processes Knowledge of high-speed interfaces like USB, PCIe, Ethernet, Mobile DDR, Quad/Octa-SPI Knowledge of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, CAN, etc. Knowledge of processors like RISC-V and ARM processors Knowledge of design signoff flows including Lint, CDC, Formal Verification, Synthesis, Constraints and STA Timing Closure Knowledge of DFT including Scan, ATPG, MBIST Knowledge of low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling) Knowledge of hardware accelerators Knowledge of Verilog and System Verilog Knowledge of scripting languages like Perl, Python, Tcl, shell

The Core design and verification team is responsible for development of High performance and Ultralow power x86 microprocessor core . The role provides a unique opportunity to work at the micro-architectural level of the next-gen Core, with exposure to designs that defines the next wave of client (laptops / ultra-books / think-clients) and custom designs. The multi-billion gate complexity and high-frequency (GHz) design development gives the learning experience of the latest and greatest design and verification methodologies, using cutting edge advanced technology nodes. THE PERSON: Candidates should have solid track record of working on complex designs with hands on experience on architecting and developing test-bench, test-bench components, test-planning and execution of testplan, coverage development and closure. Candidate should have working experience with global teams spread across different geography and time-zones. KEY RESPONSIBILITIES: ASIC design verification experience 6 to 10 years. Verification of high performance x86-core ISA features Architecting and development of testbench, test-bench components for high performance Cache, x86 ISA features, clock/reset/power features of processor. Development of detailed test plans and driving the execution of test plan, including functional coverage. Understanding the existing test bench setup and look for opportunities to improve the existing test bench. Adhering to coding guideline practices, develop and implement code review process. Collaborate with global design verification teams and drive effectively the execution of the verification plans. Your commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion. PREFERRED EXPERIENCE: Strong understanding the design and verification life cycle. Hands on verification experience with C/C++/SystemVerilog testbench development. Hands on experience with coverage planning, coding and coverage closure. Experience with x86, ARM or any other industry standard microprocessor ISA. Experience with Cache, Coherency and Data-Consistency verification. Experience in clocking, reset, power-up sequences and power management verification. Knowledge of microprocessor design-for-debug (DFD) logic will be a plus. Understanding of low power design verification techniques is a plus. ACADEMIC CREDENTIALS: Master s degree preferred with emphasis in Electrical/Electronics Engineering, Computer Engineering, or Computer Science with a focus on computer architecture

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience, 4 years of experience in ASIC development with Verilog/SystemVerilog, VHDL, Experience in micro-architecture and design of IPs and Subsystems, Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT), Preferred qualifications: Experience in Networking domain like Packet processing, bandwidth management, congestion control etc Experience with scripting languages (e-g , Python or Perl), Knowledge of bus architectures, fabrics/NoC, processor design, or memory hierarchies, Knowledge of high performance and low power design techniques, About The Job In this role, youll work to shape the future of AI/ML hardware acceleration You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems, In this role, you will develop to accelerate and improve traffic efficiency in data centers You will collaborate with members of architecture, verification, power and performance, physical design, etc to specify and deliver quality designs for next generation data center accelerators You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind, Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them We keep our networks up and running, ensuring our users have the best and fastest experience possible, Responsibilities Own microarchitecture and implementation of IPs and subsystems in the Networking domain, Work with design team members to close feature definitions and develop microarchitecture specifications, Participate in design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams, Work on Power, Performance and Area improvements for the domains owned, Google is proud to be an equal opportunity workplace and is an affirmative action employer We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status We also consider qualified applicants regardless of criminal histories, consistent with legal requirements See also Google's EEO Policy and EEO is the Law If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form , Show more Show less

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience, 4 years of experience in ASIC development with Verilog/SystemVerilog, VHDL, or Chisel, Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT), Experience in one or more SoC integration domains and flows (e-g , clocking, debug, fabrics, security, or low power methodologies), Preferred qualifications: Experience with scripting languages (e-g , Python or Perl), Experience in SoC designs and integration flows, Knowledge of bus architectures, processor design, accelerators, or memory hierarchies, Knowledge of high performance and low power design techniques, About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products You'll contribute to the innovation behind products loved by millions worldwide Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration, The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc ) and Google Cloud Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world, We prioritize security, efficiency, and reliability across everything we do from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers, Responsibilities Own microarchitecture, implementation, and integration of SoC Chassis and subsystems, Perform quality check flows (e-g , Lint, CDC, RDC, VCLP), Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams, Identify and drive power, performance, and area improvements for the domains owned, Google is proud to be an equal opportunity workplace and is an affirmative action employer We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status We also consider qualified applicants regardless of criminal histories, consistent with legal requirements See also Google's EEO Policy and EEO is the Law If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form , Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a passionate and experienced verification engineer eager to make a difference at the forefront of technology With a strong foundation in electronics and a deep understanding of System-on-Chip (SoC) verification, you thrive in collaborative environments where complex problem solving and innovation are key You have hands-on expertise in advanced verification methodologies?particularly UVM, SystemVerilog, and C/C++?and youre familiar with industry-standard protocols such as AXI-AMBA, USB, PCIe, and MIPI Your analytical skills are matched by your ability to mentor and lead, supporting younger engineers while driving project success, You recognize the value of diversity and inclusion and bring an open-minded, adaptable approach to your work Whether working independently or as part of a multidisciplinary team, you are proactive in learning new tools and methodologies, and you consistently deliver high-quality results Your communication skills help you collaborate effectively with architects, designers, and verification teams, and your experience with ARM-based technologies gives you a unique edge You are motivated by the opportunity to solve challenging customer problems and help shape the future of high-performance computing, automotive, aerospace, and defense solutions, What Youll Be Doing: Designing and developing comprehensive verification test plans and infrastructure based on design specifications and customer requirements, Implementing and analyzing SystemVerilog assertions and coverage metrics (code, toggle, functional) to ensure design correctness, Leading verification activities, mentoring junior engineers, and assisting in debugging complex issues, Collaborating closely with architects, designers, and pre & post silicon verification teams to achieve project goals, Adhering to rigorous quality standards and best practices in test and verification processes, Rapidly ramping up on new verification tools and methodologies using Synopsys products to enable customer success, Developing innovative, independent solutions to technical challenges with minimal guidance, Consistently setting and achieving task-level goals and project milestones, Working with Synopsys teams, including Business Unit Application Engineers and Sales, to broaden and deploy tool and IP solutions, The Impact You Will Have: Ensuring the delivery of robust, high-quality SoC solutions for leading-edge customers in diverse industries, Accelerating the verification process, reducing time-to-market for innovative chip designs, Enhancing customer satisfaction by solving complex design and verification challenges, Driving the adoption of Synopsys EDA tools and IP, strengthening the companys market leadership, Enabling the successful launch of products in high-performance computing, automotive, aerospace, and defense sectors, Mentoring and developing junior team members, fostering a culture of excellence and continuous learning, Contributing to the evolution of verification methodologies and best practices, What Youll Need: E/B Proven experience in IP or SoC level verification, including processor-based SoC environments (native, Verilog, SystemVerilog, UVM mixed), Hands-on expertise with verification tools such as VCS, waveform analyzers, and third-party VIP integration (e-g , Synopsys VIPs), Strong proficiency in UVM, SystemVerilog, and C/C++ for verification, Familiarity with AXI-AMBA protocol variants, scripting languages (shell, Makefile, Perl), and ASIC design concepts and flow, Experience with ARM core verification, USB, PCIe, MIPI protocols, and ARM-based technologies (Coresight Debug, Processor architecture) is highly desirable, Excellent problem-solving, analytical, and debugging skills, Effective communication skills for teamwork and customer engagement, Who You Are: Collaborative team player who thrives in a diverse, inclusive environment, Proactive learner, always eager to master new tools and methodologies, Detail-oriented with a strong commitment to quality and excellence, Natural mentor and leader, able to support and guide junior engineers, Resourceful thinker with a passion for solving complex technical challenges, Clear communicator, able to convey technical concepts to various audiences, The Team Youll Be A Part Of: Youll join the System Solutions Group (SSG), a dynamic team delivering expertise in tool, methodology, architecture, design creation, verification, and physical implementation SSG partners with startups, industry leaders, commercial companies, and government agencies to tackle the most challenging SoC projects?from sub-blocks to full turnkey solutions Our team is passionate about enabling customers in high-performance computing, automotive, aerospace, and defense to achieve their goals with innovative, reliable solutions, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process, Show more Show less

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience, 5 years of experience in ASIC/SoC development with Verilog/SystemVerilog, Experience in one or more SoC Integration domains and flows (Clocking or debug or fabrics/NoC or Security or low power methodologies), Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT), Preferred qualifications: Experience with programming languages (e-g , Python, C/C++ or Perl), Experience in SoC designs and integration flows, Knowledge of bus architectures, fabrics/NoC or memory hierarchies, Knowledge of high performance and low power design techniques, About the jobIn this role, youll work to shape the future of AI/ML hardware acceleration You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems, In this role, you will be part of a team developing SoCs used to accelerate machine learning computation in data centers You will solve technical problems with innovative and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind You will collaborate with members of architecture, verification, power and performance, physical design etc to specify and deliver high quality designs for next generation data center accelerators Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them We keep our networks up and running, ensuring our users have the best and fastest experience possible, Responsibilities Own microarchitecture, implementation and Integration of SoC Chassis and subsystems, Perform Quality check flows like Lint, CDC, RDC, VCLP, Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams, Identify and drive Power, Performance and Area improvements for the domains owned, Google is proud to be an equal opportunity workplace and is an affirmative action employer We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status We also consider qualified applicants regardless of criminal histories, consistent with legal requirements See also Google's EEO Policy and EEO is the Law If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form , Show more Show less

Mesh / Coherency Design Verification Engineer in Bangalore, KA, India Mesh / Coherency Design Verification Engineer Description Invent the future with us. Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team we d love to have you apply. Come invent the future with us. About the role: You will work on the verification of a server-class microprocessor-based CPU/Coherent Mesh interconnect. Youll be involved with all aspects of pre-silicon verification at unit and system level to ensure functional correctness and performance of microprocessors. Youll also partner with other teams to accelerate post-silicon validation and debug of the product. In this role, you will be at the forefront of AI innovation, building AmpereOne Aurora, our groundbreaking AI compute solution. Aurora combines high-performance general-purpose CPUs with integrated AI capabilities, offering a compelling combination of efficiency and market reach. This revolutionary product is poised to deliver superior performance while consuming significantly less power. What you ll achieve: Define requirements for block level and subsystem level testing infrastructure Create test plans for unit-level and chip-level verification and post-silicon validation Architect, design and implement test benches and other components of design verification environment Create random test generators to find bugs in design Debug failures and drive speedy resolution of bugs Create coverage monitors and drive coverage to required quality targets Define post-silicon validation plans, and engage in post-silicon activities to accelerate product launch Lead verification activities within a team and guide other engineers to achieve project goals About you: M.Tech in Electronics Engineering or Computer Engineering with 3+ years of semiconductor experience or B.Tech in Electronics Engineering or Computer Engineering with 5+ years of semiconductor experience Solid understanding of high-performance microprocessor architecture concepts Experience using industry standard HDL languages (Verilog, System Verilog, VHDL) and simulation tools Experience developing verification environments in one or more industry standard languages like SVTB UVM/OVM Programming experience in languages common to the industry (e.g., C, C++, Perl, Python) Experience in automating design, verification, and validation tasks Hands on experience in post-silicon validation Knowledge of ARM or x86 architecture and assembly language programming Previous experience in CPU/core design verification is preferred Previous experience in Network-on-chip (NoC) design verification is preferred Previous experience with Arm AMBA (APB/AHB/AXI/ACE/CHI) protocols is preferred Previous experience with formal verification is preferred What we ll offer: At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits highlights include: Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process. #LI-SF1 Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.

Mesh / Coherency Design Verification Engineer in Pune, MH, India Mesh / Coherency Design Verification Engineer Description Invent the future with us. Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team we d love to have you apply. Come invent the future with us. About the role: You will work on the verification of a server-class microprocessor-based CPU/Coherent Mesh interconnect. Youll be involved with all aspects of pre-silicon verification at unit and system level to ensure functional correctness and performance of microprocessors. Youll also partner with other teams to accelerate post-silicon validation and debug of the product. In this role, you will be at the forefront of AI innovation, building AmpereOne Aurora, our groundbreaking AI compute solution. Aurora combines high-performance general-purpose CPUs with integrated AI capabilities, offering a compelling combination of efficiency and market reach. This revolutionary product is poised to deliver superior performance while consuming significantly less power. What you ll achieve: Define requirements for block level and subsystem level testing infrastructure Create test plans for unit-level and chip-level verification and post-silicon validation Architect, design and implement test benches and other components of design verification environment Create random test generators to find bugs in design Debug failures and drive speedy resolution of bugs Create coverage monitors and drive coverage to required quality targets Define post-silicon validation plans, and engage in post-silicon activities to accelerate product launch Lead verification activities within a team and guide other engineers to achieve project goals About you: M.Tech in Electronics Engineering or Computer Engineering with 3+ years of semiconductor experience or B.Tech in Electronics Engineering or Computer Engineering with 5+ years of semiconductor experience Solid understanding of high-performance microprocessor architecture concepts Experience using industry standard HDL languages (Verilog, System Verilog, VHDL) and simulation tools Experience developing verification environments in one or more industry standard languages like SVTB UVM/OVM Programming experience in languages common to the industry (e.g., C, C++, Perl, Python) Experience in automating design, verification, and validation tasks Hands on experience in post-silicon validation Knowledge of ARM or x86 architecture and assembly language programming Previous experience in CPU/core design verification is preferred Previous experience in Network-on-chip (NoC) design verification is preferred Previous experience with Arm AMBA (APB/AHB/AXI/ACE/CHI) protocols is preferred Previous experience with formal verification is preferred What we ll offer: At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits highlights include: Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process. #LI-SF1 Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.

Desired Profile : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering. Expertise in execution and debugging of test-suites at the GPU sub-system level Expertise in GLS (Gate-Level Simulation) Expertise in writing assertions and test benches using system verilog Expertise in UVM methodologies Expertise in Test planning Expertise in sub-system level DV Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations Preferred resources with valid regional work permit

Desired Profile : Bachelor's / Master's degree in engineering from EEE / E&C Expertise in managing and leading technical teams across different continents Expertise in leading business strategy in the VLSI / Semiconductor Services / foundry business industry Expertise in managing end to end projects including tape outs Must be willing to travel at short notice, relocate as per business needs Must be willing to work onsite (customer premises) as per business needs Expertise in working on any of the following technologies is mandatory : ANALOG MIXED SIGNAL LAYOUT - finfet / high speed / planar technology nodes ANALOG DESIGN - data converter / power management / pll ANALOG VERIFICATION ASIC PHYSICAL DESIGN ASIC RTL DESIGN DFT DESIGN - jtag / mbist / lbist / scan DIGITAL VERIFICATION - OVM / UVM / VMM EDA CAD FLOW - tcl / primetime / design compiler Job Specs : Responsible for meeting delivery, revenue, operational, customer satisfaction targets and team management Hire and manage high caliber technical teams across GCC, ODC and onsite Develop, Drive high quality business / technology strategy and oversee the translation of this strategy into tactical action Uphold the organization's culture and long term missions Liaise and negotiate with various partners around the world to bring in new partnership. Synergize all company's resources and talents for the growth of company's business Oversee all sectors and fields of the business to ensure the company's competitiveness Provide leadership, direction, major decision making and resolution support to operations, projects and staff. Build strategic business partnerships and execute these opportunities through collaboration with external partners Location - Bengaluru,Bhubaneswar,Kolkata,Kochi,Mysuru

As an experienced ASIC RTL Design Engineer at MarvyLogic, you will be responsible for designing cutting-edge solutions that impact various industries. Your role will involve working with multiple clock and power domains, integrating and validating MIPI cores, debugging, and implementing CSI/DSI controllers. Your expertise in Verilog/System Verilog will be crucial in creating micro-architecture specifications, reviewing vendor IP integration guidelines, and running integrity check tools to ensure compliance with coding standards. Additionally, you will play a key role in the design verification and physical implementation processes to meet performance goals. **Key Responsibilities:** - Utilize your 10+ years of ASIC RTL Design experience to develop innovative solutions - Demonstrate proficiency in Verilog/System Verilog and experience with multiple clock and power domains - Integrate and validate CSI/DSI/DPHY/CPHY/other MIPI cores, including controllers and SerDes - Debug CSI/DSI issues and design and implement CSI/DSI controllers - Create block-level micro-architecture specifications outlining interfaces, timing behavior, and design tradeoffs - Review vendor IP integration guidelines and ensure compliance throughout the design flow - Run integrity check tools such as Lint/CDC/DFT/LEC/UPF to meet coding and implementation guidelines - Participate in design verification and physical implementation processes to achieve area, power, and performance goals **Qualifications Required:** - 10+ years of ASIC RTL Design experience - Graduate Degree in Electrical/Electronics Engineering (Post Graduate degree is a plus) - Experience with CSI/DSI debug and FPGA netlist releases - Familiarity with ASIC product life cycle (requirements, design, implementation, test, and post-silicon validation) - Strong communication skills and ability to collaborate with multi-site teams At MarvyLogic, we foster a culture that values passion for technology solutions and individual growth. Working with us will provide you with exposure to diverse industries and emerging technologies, helping you evolve both professionally and personally towards a more fulfilling life.,

As an experienced Functional Formal Verification Engineer, you will be leading the formal verification efforts for complex digital designs. You will play a critical role in ensuring the quality and reliability of our digital designs. **Key Responsibilities:** - Lead complete formal verification for single or multiple design blocks and IPs, including developing and implementing formal verification strategies and test plans. - Create comprehensive formal verification test plans and specifications to ensure thorough coverage of design functionality. - Prove design properties, identify bugs, and collaborate with design teams to improve micro-architectures and ensure design correctness. - Craft innovative solutions for verifying complex design architectures, including developing re-usable and optimized formal models and verification code bases. - Mentor junior team members and provide technical leadership in formal verification methodologies, including training and guidance on industry-standard tools and techniques. - Collaborate with cross-functional teams, including design and verification, to ensure seamless integration of formal verification into the overall verification flow. **Qualifications:** - Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or a related field. - 10+ years of experience in formal verification of complex IP/SubSystem/SoCs, with a strong understanding of digital logic design and verification techniques. - Expertise in formal verification tools and property specification languages (e.g., SVA, PSL), as well as proficiency in HDLs such as System Verilog, Verilog, or VHDL. - Experience with industry-standard EDA formal tools. - Experience with scripting languages (e.g., Python, Tcl, Perl) and programming languages such as C/C++/SystemC. - Excellent problem-solving and analytical skills, with the ability to debug complex issues and optimize verification performance. - Strong communication and interpersonal abilities, with experience working in a team environment and collaborating with cross-functional teams. - Proven track record in technical leadership and mentoring, with experience guiding junior engineers and contributing to the development of formal verification methodologies. The company is looking for someone with experience in CPU, GPU, or other complex digital architectures, including knowledge of industry-standard protocols (e.g., AXI, CHI, PCIe). Familiarity with UVM methodology and/or other simulation-based verification methodologies is preferred. Additionally, expertise in Jasper or VC Formal products is highly desirable.,

As a Lead Product Engineer at Cadence, you will have the exciting opportunity to work on cutting-edge technology in an environment that fosters creativity, innovation, and impact. Cadence is a pivotal leader in electronic design, leveraging over 30 years of computational software expertise to deliver software, hardware, and IP solutions that bring design concepts to life. You will be part of a dynamic team working with the world's most innovative companies across various market applications, including consumer electronics, hyperscale computing, 5G communications, automotive, aerospace, industrial, and health sectors. **Key Responsibilities:** - Lead projects with high resource, risk, and complexity, driving the development and success of products and technologies. - Develop and drive large cross-functional programs with a focus on accelerating VIP portfolio adoption at top-tier customers by providing pre-sales technical support. - Be an expert in MIPI domain of Verification IP family, understanding protocols and products to support customer design and verification flows. - Collaborate with R&D, Marketing, and support teams to ensure alignment across all dimensions of the product. - Translate customer requirements into technical specifications and drive product definition that meets customer needs. - Conduct product knowledge transfer sessions, provide training, and develop collaterals for field engineers and customers. - Manage issue resolution with vendors to ensure product quality and functionality, influencing vendor roadmap and product direction. **Qualifications Required:** - 7+ to 12 years of experience in Verification and Design, with a strong background in MIPI (CSI2/DSI/I3C/PHY) protocols. - Proficiency in developing Verification environments using System Verilog and working with the UVM methodology. - Strong problem-solving and debugging skills, with the ability to analyze complex situations and data effectively. - Excellent written, verbal, and presentation skills to communicate complex ideas and persuade stakeholders. - Ability to establish close working relationships with customers and internal teams, operating with integrity and pushing for continuous improvement. - Willingness to travel approximately 20% of the time to engage with customers and support product adoption. At Cadence, you will join a diverse team of passionate individuals dedicated to delivering exceptional electronic products and solutions. The unique One Cadence - One Team culture promotes collaboration and success, providing multiple avenues for learning and development tailored to your interests. You will have the opportunity to make a significant impact while working in an employee-friendly environment that prioritizes your well-being, career growth, and success. Join us in solving challenges and creating solutions that matter in the world of technology.,

As a design engineer at Texas Instruments, you will be working on high-speed mixed-signal communication circuits using state-of-the-art process technology. You will also be involved in designing high-performance digital circuits interfacing with leading-edge analog circuitry within an overall system. Your responsibilities will include: - RTL coding, simulation, synthesis, timing closure, verification, evaluation, and debugging of high-speed communication chips at both circuit and behavioral levels - Preparing test methods and specifications, assisting in the preparation of application information, data sheets, and demo boards - Developing solutions to complex problems through the assessment of various techniques and approaches - Planning and organizing work to ensure the timely completion of multiple independent tasks, with general instructions on routine tasks and detailed instructions on new assignments Minimum Qualifications: - 5+ years of relevant experience - Thorough understanding of digital logic design - Familiarity with Verilog language and simulators - Good understanding of analog functionality and exposure to analog IC design methods - Ability to solve problems using a systematic approach Preferred Qualifications: - Experience with System Verilog - Demonstrated strong analytical and problem-solving skills - Strong verbal and written communication skills - Ability to work in teams and collaborate effectively with individuals in different functions - Strong time management skills for on-time project delivery - Demonstrated ability to build influential relationships - Ability to work effectively in a fast-paced and rapidly changing environment - Ability to take initiative and drive for results Texas Instruments, a global semiconductor company, designs, manufactures, and sells analog and embedded processing chips for various markets. The company's core passion is to create a better world by making electronics more affordable through semiconductors. TI values diverse backgrounds and perspectives to push innovation forward and strengthen the company. If you are looking for a challenging role with opportunities for career ownership and development, consider applying to this requisition.,

We are seeking an experienced System on Chip (SoC) Architect to join our development team. The ideal candidate will be involved in designing, integrating, and optimizing SoC hardware architectures and ensuring seamless software-hardware co-development. You have: Bachelors Degree in Electrical Engineering, Computer Engineering, or a related field (Masters or Ph.D. preferred). Overall,15+ years of experience as a Chip design expert. 8+ years of proven experience in IC design, SoC architecture, or a similar role. Proficiency in hardware description languages: Verilog, VHDL, and System Verilog Expertise in EDA tools for IC design and verification: Mentor Graphics, Cadence, or Synopsys Strong understanding of SoC architecture, including processor, memory subsystem, and interconnects (e.g., AXI, AMBA). Experience with hardware-software co-design and debugging tools. Knowledge of low-power design techniques and methodologies. Strong scripting skills in Python, Tcl, or Perl for automation. Tools : MATLAB/Simulink, Microsoft Visio, Mentor Graphics QuestaSim It would be nice if you also had: Familiarity with high-level modeling tools like SystemC. Knowledge of advanced packaging technologies (e.g., Chiplets, 3D ICs). Exposure to machine learning or AI accelerators in SoC design. Develop SoC architectures for advanced applications, ensuring scalability, performance, and power efficiency Lead hardware design and integration processes, including RTL coding, synthesis, and verification Collaborate with software teams to ensure efficient software-hardware co-design and integration Perform system-level modeling and simulations to validate architectural choices Guide SoC implementation, including floor planning, physical design, and timing closure Follow best practices for IC design and manufacturing Analyze system requirements, identify bottlenecks, and propose innovative solutions

Experience : 3 to 10 Years Qualification : Bachelors or Masters (Electronics and Communication Engineering or equivalent) Job Description: As an Emulation Engineer, youll be an integral part of a dynamic team dedicated to creating cutting-edge ASIC solutions for High-Performance Computing (HPC) systems. Your role will involve defining the validation strategy leading to functional sign-off for these high-performance computing designs. Key functions and responsibilities: Proficient in various emulation technologies, including simulation acceleration, in-circuit emulation, speed bridges, virtual prototyping, and hybrid methods. Familiarity with tools such as Palladium, Protium, Veloce, or Zebu. Good Knowledge of SystemC/C/C++ and UVM/SV verification languages Experience with SystemVerilog and C++ for modelling RTL components and transactors. Ability to develop C/C++/SystemC/SV tests in HDL-HVL (Hardware Description Language-Hardware Verification Language) Co-emulation platforms. Understanding of compilation and build flow. Skilled at building images from scratch, making necessary design modifications to adapt to emulation. Work closely with verification teams to define and implement comprehensive pre and post silicon test plans. Interface effectively with design, verification, validation, and software development teams to understand their needs from an emulation perspective. Experience in architecting emulation systems for various design scales (IP blocks, SOC, multi-chip systems). Balancing performance and ease of debug. Proficient in post-silicon bring-up, debugging, and issue reproduction on emulators. Familiarity with Python and TCL scripting languages. Exposure to domains such as PCIe, CXL, DDR, Flash, Memory, USB, and CPU. Strong communication and collaboration skills to work effectively with cross-functional teams and domain experts. Successfully manage multiple design releases and provide support for debugging customer issues.