2434 System Verilog Jobs - Page 6

Understand the design specification , Memory and Memory BIST engine connections Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 8+ years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in DFT Verification - Demonstrated execution experience of verification of Memory BIST Knowledge ...

About The Role This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; About The Role - Grade Specific Focus on Electrical, Electronics and Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in ...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

Develop/Maintain tests for functional verification at SOC level. Build testbench components to support the next generation IP Maintain or improve current verification libraries to support SOC/Full-chip level verification Provide technical support to other teams Help Hardware emulation team to port the RTL to Palladium/Zebu or HAPS/Protium platforms. PREFERRED EXPERIENCE: Strong Familiarity with Verification Methodologies such as OVM, UVM, or VMM Familiarity with Verilog and General Logic Design concepts Knowledge of system-level architecture including buses like AXI/AHB, bridges, memory controllers such as DDR4/DDR5, and peripherals such as USB, PCIe and Ethernet Strong working knowledge of ...

Develop/Maintain tests for functional verification at SOC level. Build testbench components to support the next generation IP Maintain or improve current verification libraries to support SOC/Full-chip level verification Provide technical support to other teams Help Hardware emulation team to port the RTL to Palladium/Zebu or HAPS/Protium platforms. PREFERRED EXPERIENCE: Strong Familiarity with Verification Methodologies such as OVM, UVM, or VMM Familiarity with Verilog and General Logic Design concepts Knowledge of system-level architecture including buses like AXI/AHB, bridges, memory controllers such as DDR4/DDR5, and peripherals such as USB, PCIe and Ethernet Strong working knowledge of ...

Develop/Maintain tests for functional verification at SOC level. Build testbench components to support the next generation IP Maintain or improve current verification libraries to support SOC/Full-chip level verification Provide technical support to other teams Help Hardware emulation team to port the RTL to Palladium/Zebu or HAPS/Protium platforms. PREFERRED EXPERIENCE: Strong Familiarity with Verification Methodologies such as OVM, UVM, or VMM Familiarity with Verilog and General Logic Design concepts Knowledge of system-level architecture including buses like AXI/AHB, bridges, memory controllers such as DDR4/DDR5, and peripherals such as USB, PCIe and Ethernet Strong working knowledge of ...

Emulation and Silicon Validation of complex System on Chip ASIC design. Define, develop and implement test plans and execute on the test plan Develop system level tests using tcl, itcl, python, C/C++ languages to verify networking switch chips and systems. Create reusable design blocks, libraries and verification components for emulation Debug and resolve Pre / Post Silicon failures, Collaborate Cross-functionally with Architecture, uArch and Design teams Enable and support Software/Firmware teams with Emulation setup Synthesize complex system on chip designs and map into various hardware emulator platforms like Cadence Palladium or Mentor Veloce or Synopsys Zebu. Additional Job Description ...

We are seeking an experienced Hardware Architect with strong expertise in SOC-architecture, Micro-architecture design, RTL coding and system-level performance/power analysis. The ideal candidate will have a track record of owning complex blocks or subsystems from concept through silicon, balancing performance, power, and area (PPA), and working closely with software, asic-design, asic-verification, asic-physicaldesign teams. it requires deep architectural insight and hands-on implementation understanding to help guide design trade-offs and drive the next generation of AI inference accelerators.This is what you are responsible for Architecture & Micro-Architecture Define product feature and c...

Role & responsibilities As a Formal Property Verification (FPV) Engineer at HCLTech, you will play a critical role in ensuring the functional correctness and reliability of complex hardware designs through advanced formal verification techniques. Your expertise will directly contribute to the delivery of high-quality products and solutions, supporting the company's mission to provide innovative and dependable technology services to its global clientele. Detailed Responsibilities Develop, implement, and execute formal property verification strategies for complex hardware and digital designs. Collaborate closely with design, verification, and architecture teams to define verification requireme...

About The Role Project Role : Functional Verification Engineer Project Role Description : Develop and execute testbenches to verify the functional correctness of digital designs at the block and system level. Create constrained-random, directed, and coverage-driven tests using languages like SystemVerilog and UVM. Collaborate with design and architecture teams to identify corner cases and ensure complete functional coverage before tape-out. Must have skills : SAP TM Transportation Management Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Functional Verification Engineer, you will engage in the develo...

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills.

About the Role We are seeking a highly skilled and experienced Hardware Architect to join our dynamic team. The ideal candidate will have a strong background in hardware architecture, particularly in writing architectural models and conducting performance and power analysis of chips. In addition to collaborating closely with our hardware team, the successful candidate will also work with our software department, which focuses on compilers, runtime software, and kernel software, to ensure cohesive and efficient chip design and functionality. This is what you are responsible for Architecture Modeling: Develop architecture models for AI chips Collaborate with cross-functional teams to ensure mo...

Role Overview: You will be a part of the Common Hardware Group (CHG) at Cisco, responsible for delivering silicon, optics, and hardware platforms for core Switching, Routing, and Wireless products. Your role will involve crafting, developing, and testing sophisticated ASICs to shape Cisco's ground-breaking solutions. You will engage in dynamic collaboration with verification engineers, designers, and multi-functional teams to ensure successful verification of the ASIC throughout its lifecycle. Key Responsibilities: - Architect block, cluster, and top-level DV environment infrastructure. - Develop DV infrastructure from scratch. - Maintain and enhance existing DV environments. - Develop test ...

A major part of your responsibility will be to take an independent verification role in developing TB architecture definition and TB infrastructure/test coding development for PCIe/Networking/IP Sub-Systems. Understanding product specifications and deriving the TB architectures. Developing verification plan, test plan, coverage plan, assertions, etc. Developing block-level and multi block-level verification environments & reusable verification components based on SV/UVM methodology. Coverage metrics to ensure conformity, running regressions, debug test failures, and regression management. Knowledge and working experience with any of the complex protocols like PCIe/Ethernet/DMAs/Cryptography/...

In Lattice, we are a global community of engineers, designers, and manufacturing operations specialists working together with sales, marketing, and support teams to develop cutting-edge programmable logic solutions that are revolutionizing the industry. Our focus on research and development, product innovation, and customer service is fueled by our total commitment and competitive spirit. As a SoC RTL Design Engineer at Lattice Semiconductor, you will be a part of the hardware design team concentrating on IP design and full chip integration. This role offers ample opportunities for you to contribute, learn, innovate, and grow within a dynamic team environment. **Role Specifics:** - This is a...

As a SOC Verification Engineer, your role will involve developing and executing C-based test cases for SOC-level verification. You will be responsible for performing processor-based SOC validation, including boot, memory, and peripheral verification. In case of any test failures, it will be your responsibility to debug and analyze them, identify the root causes, and collaborate closely with design and integration teams. Your contribution will be crucial in test plan development, coverage closure, and regression management. Additionally, you will collaborate with cross-functional teams to ensure SOC functionality, performance, and reliability. You will utilize simulation, emulation, and FPGA ...

Job Description BE/ME in ECE, Electronics, or equivalent 8-12 years of experience in RTL design verification for Block/IP/Sub-system/SOC Knowledge in synthesis and timing analysis Experience & Knowledge with verilog and System Verilog for Verification , SVA, UVM - Strong Advantage Deep knowledge of the following tools is an advantage: cadence NCSim, simvision, vmanager, any simulator, and waveform debug EDA tools from mentor, Synopsys Experience with FPGA verification Knowledge simulation environment System Verilog - UVM based - advantage Developing testbench for constraint random environment, Metric driven verification Root-cause design issue and able explain in text form clearly with desig...

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life s work , to amplify human creativity and intelligence. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do thei...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

We are currently seeking a skilled Design Verification Engineer to join our team. As a Design Verification Engineer, you will be responsible for verifying and validating complex digital designs to ensure they meet the required specifications and standards. Key Responsibilities: - Develop and execute verification plans for digital designs - Perform functional verification and debugging of digital designs - Collaborate with design and verification teams to ensure successful tape-out - Utilize industry-standard tools and methodologies for verification Qualifications: - Bachelors degree in Electrical Engineering or related field - Proven experience in digital design verification - Strong underst...

Job Requirements Role Overview We are seeking a highly motivated and skilled SoC RTL Integration & Design Sign-off Engineer to join our cutting-edge semiconductor design team in Bangalore. The ideal candidate will be responsible for the top-level integration of complex System-on-Chip (SoC) designs and ensuring the design quality through various critical sign-off checks (Lint, CDC, RDC, and Low Power VCLP flows). \uD83D\uDD11 Key Responsibilities SoC Top-Level Integration: Own the SoC Top RTL integration using System Verilog for complex multi-core, multi-voltage, and multi-clock domain architectures. Low Power Design & Verification: Implement and verify the Low Power intent using the Unified ...

IP/ SoC level verification,HVL ,System Verilog, UVM/OVM/HDL ,Verilog ARM/DSP CPU, -USB2/3, PCIE Power-aware Verification, GLS, Test vector generation,Version managers like Clearcase/perforce,Scripting-Perl,Python Contact-gagan@bestnanotech.in

Role : Hardware Emulation engineer What youll do: Own and bring up emulation cutdowns cutdowns for large SoC and IP blocks to improve emulation performance and turnaround time. Adapt and port test benches to run efficiently on hardware emulation platforms. Debug and resolve issues related to AVIPs and transactors within the emulation environment. Lead the bring-up and setup of emulation platforms (Palladium, Zebu) to ensure readiness for verification runs. Collaborate closely with RTL designers, verification, and emulation infrastructure teams to ensure high coverage and quality. Troubleshoot test failures on emulators and provide actionable feedback to design and DV teams. Release validated...

Job Description We are looking for an experienced Design Verification Engineer to join our Semiconductor/ASIC Verification team. The ideal candidate will have strong hands-on experience in SystemVerilog, UVM, and functional verification of complex IP/SoCs. The role involves testbench development, coverage closure, debugging, and working on high-performance silicon products. Key Responsibilities Perform block/IP/Sub-System/SoC level design verification using SV/UVM methodology. Develop UVM-based testbenches, sequences, drivers, monitors, and scoreboard . Create and execute test plans using constrained-random and directed testing . Drive functional coverage and code coverage closure. Debug sim...

Lead the design and development of FPGA debug engine in Lattice EDA suite. Architect and refactor the FPGA debug IP and guide the UI team to enhance existing functionality and new features. As a principal RTL Engineer, you will work closely with marketing requirements and generate functional architecture and specifications for new FPGA debug IP functionality and guide the QA teams and ensure that implementations match design intent. Mentor and guide junior RTL & UI engineers working on FPGA debug IP, fostering a culture of continuous improvement and innovation. Maintain high standards of architecture, implementation quality, performance, and reliability. Improve development methodologies and...